Early Memories Early Memories

Memory

Prof. Stephen A. Edwards [email protected]

NCTU, Summer 2005 Williams Tube CRT-based random access memory, 1946. Used on the Manchester Mark I. 2048 bits. Mercury acoustic delay line. Used in the EDASC, 1947. 32 × 17 bits

Memory – p. 1/23 Memory – p. 2/23 Memory – p. 3/23

Early Memories Early Memories Modern Memory Choices

Family Programmed Persistence Mask ROM at fabrication ∞ PROM once ∞ EPROM 1000s, UV 10 years FLASH 1000s, block 10 years EEPROM 1000s, byte 10 years Magnetic core memory, 1952. IBM. NVRAM ∞ 5 years

Magnetic drum memory. 1950s & 60s. SRAM ∞ while powered Secondary storage. DRAM ∞ 64 ms

Memory – p. 4/23 Memory – p. 5/23 Memory – p. 6/23

ROMs EPROMs EEPROM and FLASH

Slow write

Fowler- Oxide Nordheim Tunneling

floating gate Word Line EEPROM: bit at a time Drain (bit line) FLASH: block Source Channel at a time

Source: SST

Memory – p. 7/23 Memory – p. 8/23 Memory – p. 9/23 Static RAM Cell Standard SRAM: 6264 Standard SRAM: 6264

19±15,13±11

Word D[7:0] ¡£¢ ¤ ¡£¢ ¤ 10±2,25±23,21 8K × 8 Addr[12:0] CS1 ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ 22 Can be very fast: 1CY 626 4

OE ¡£¢ ¡£¢ ¤ ¤ 27 Cypress sells a 55ns WE CS2 20 version ¢ ¢ ¢ ¢ ¢ ¢ ¢ CS1 PRELIMINARY 26 Simple, asynchronous ¡£¢ ¤ CY6264 CS2 WE interface ¢ ¢

8K x 8 Static RAM ¡£¢ ¤ Bit Bit OE Features over 70% when deselected. The CY6264 is packaged in a ¢ 450-mil (300-mil body) SOIC. • 55, 70 ns access times An active LOW write enable signal (WE) controls the writ- ¥ ¥ ¥ ¨ § § § § ¥¦ ¥ ¥ §¨ § § § § § § ¥¦ ¥ • CMOS for optimum speed/power ing/reading operation of the memory. When CE1 and WE in- Addr • Easy memory expansion with CE1, CE2, and OE fea- puts are both LOW and CE2 is HIGH, data on the eight data tures input/output pins (I/O0 through I/O7) is written into the memory

• TTL-compatible inputs and outputs location addressed by the address present on the address § § § § § § § § § § pins (A through A ). Reading the device is accomplished by • Automatic power-down when deselected 0 12 © © © © © © © © © selecting the device and enabling the outputs, CE1 and OE Data Memory – p. 10/23 Memory – p. 11/23 Memory – p. 12/23 Functional Description active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location ad- The CY6264 is a high-performance CMOS static RAM orga- dressed by the information on address pins is present on the nized as 8192 words by 8 bits. Easy memory expansion is eight data input/output pins. provided by an active LOW chip enable (CE1), an active HIGH The input/output pins remain in a high-impedance state unless chip enable (CE2), and active LOW output enable (OE) and the chip is selected, outputs are enabled, and write enable three-state drivers. Both devices have an automatic pow- (WE) is HIGH. A die coat is used to insure alpha immunity. × × er-downStandar feature (CE1)d, reduSRAM:cing the power co6264nsumption by Toshiba TC55V16256J 256K 16 Toshiba TC55V16256J 256K 16

Logic Block Diagram Pin Configuration 38±35,32±29,16±13,10±7 SOIC D[15:0] Top View 23,22,18±21,24±27,42±44,1±5 NC 1 28 VCC Addr[17:0] A4 2 27 WE 40 A5 3 26 CE2 UB I/O0 A6 4 25 A3 A7 5 24 A2 39 INPUT BUFFER A8 6 23 A1 LB I/O1 A9 7 22 OE 41 A10 8 21 A0 OE A11 9 20 CE1 A1 I/O2 A12 10 19 I/O7 17 A2 I/O0 11 18 I/O6 WE A 3 I/O3 I/O1 12 17 I/O5 6 A4 256 x 32 x 8 I/O2 13 16 I/O4 GND I/O CE A5 ARRAY 14 15 3 I/O4 A6 CY6264-2 A7 I/O A8 5 12 or 15 ns access time I/O6 Asynchronous interface POWER CE1 DOWN I/O7 CE2 COLUMN DECODER WE UB, LB select bytes OE

CY6264-1 Memory – p. 13/23 Memory – p. 14/23 Memory – p. 15/23

Selection Guide

CY6264-55 CY6264-70

DynamicMaximum Access Time (ns)RAM Cell 55 70 Ancient DRAM: 4164 Basic DRAM read and write cycles Maximum Operating Current (mA) 100 100 Maximum Standby Current (mA) 20/15 20/15 Shaded area contains advanced information. 64K × 1

Row Apple IIe vintage ¤ ¡£¢ ¤ ¡£¢ RAS

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ October 1994 – Revised June 1996

9,13,10±12,6,7,5 ¡£¢ ¤ ¡£¢ ¤ Addr[7:0] CAS 2 DIN DOUT 14 ¢ ¢ ¢ ¢ ¢

Column 3 ¥ ¥ ¥ ¥ ¨ § § § § ¥¦ ¥ ¥ ¥ ¥ ¨ § § § § ¦ WE 15 Addr Row Col Row Col CAS

4     RAS Basic problem: Leakage WE ¢ ¢

Solution: Refresh ¥ ¥ ¥ ¨ § § ¥¦ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ Din § § § © © © © © © © © © © © © © © © © © © © © © Dout © Memory – p. 16/23 Memory – p. 17/23 Memory – p. 18/23 Page mode read cycle Samsung 8M × 16 SDRAM SamsungSDRAM 128Mb E-die8M (x4, x8,× x16)16 SDRAM CMOS SDRAM

FUNCTIONAL BLOCK DIAGRAM

21,20 Bank address BA[1:0] I/O Control ¤ ¡£¢ LWE RAS Addr[11:0] Address (multiplexed) Data Input Register ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ LDQM DQ[15:0] Data I/O Bank Select ¡£¢ ¡£¢ ¡£¢ ¤ ¤ 39 Refresh Co

Upper byte enable O

UDQM Row Deco 8M x 4 / 4M x 8 / 2M x 16 Sense AMP u Row Buf

CAS tput Buf ¢ ¢ ¢ ¢ 15 Lower byte enable 8M x 4 / 4M x 8 / 2M x 16 LDQM Addre DQi 8M x 4 / 4M x 8 / 2M x 16 f unter f der er

3 er ¥ ¥ ¥ §¨ § ¦ ¥ §¨ § ¦ ¥ ¥ ¥ ¨ § § § § ¦ CLK Write enable s WE s Register 8M x 4 / 4M x 8 / 2M x 16 Addr Row Col Col Col 15 CAS Column Address Strobe ADD

LRAS LCBR Column Decoder

15 Col. Buf

      RAS Row Address Strobe 37 Latency & Burst Length f WE CKE Clock Enable er 38 LCKE CLK Clock Programming Register

¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ LRAS LCBR LWE LCAS LWCBR LDQM Din Synchronous interface Timing Register

§ § § § § § § § § Designed for burst-mode operation CLK CKE CS RAS CAS WE L(U)DQM © Dout© © © © © © © © © Four separate banks; pipelined operation Memory – p. 19/23 Memory – p. 20/23 * Samsung Electronics reserves the right to change products or specification without notice. Memory – p. 21/23

SDRAM: Control Signals SDRAM: Timing with 2-word bursts Load Active Write Read Refresh ¡ ¤ ¡ ¤ ¡ ¤ ¡ ¤ ¡ ¤ ¡ ¤ ¡ ¤ ¡ ¤ ¡ ¤ ¡ ¤ ¡ ¤ Clk RAS CAS WE action ¢ ¤ ¡ ¤ ¡ ¤ ¡ 1 1 1 NOP RAS 0 0 0 Load mode register ¤ ¡ ¤ ¡ ¤ ¡ ¤ ¡ 0 1 1 Active (select row) CAS Rev. 1.2 May. 2003 1 0 1 Read (select column, start burst) ¤ ¡ ¤ ¡ 1 0 0 Write (select column, start burst) WE 1 1 0 Terminate Burst ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¨ ¥¦ ¥ ¥ ¥ ¨ ¦ ¥ ¥ ¥ ¥ ¨ ¥¦ ¥ ¥ ¥ ¨ ¦ 0 1 0 Precharge (deselect row) Addr Op R C C 0 0 1 Auto Refresh ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¨ ¥¦ ¥ ¥ ¥ ¨ ¥¦ ¥ ¥ ¥ ¨ ¦ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ BA B B B Mode register: selects 1/2/4/8-word bursts, CAS

latency, burst on write ¦ ¨ © © © © © © © © © © © © © © © © © © © © © © © DQ© © © © © © W W R R Memory – p. 22/23 Memory – p. 23/23