DOCSLIB.ORG

Memory.9Up.Pdf

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Memory.9Up.Pdf Early Memories Early Memories Memory Prof. Stephen A. Edwards [email protected] NCTU, Summer 2005 Williams Tube CRT-based random access memory, 1946. Used on the Manchester Mark I. 2048 bits. Mercury acoustic delay line. Used in the EDASC, 1947. 32 × 17 bits Memory – p. 1/23 Memory – p. 2/23 Memory – p. 3/23 Early Memories Early Memories Modern Memory Choices Family Programmed Persistence Mask ROM at fabrication 1 PROM once 1 EPROM 1000s, UV 10 years FLASH 1000s, block 10 years EEPROM 1000s, byte 10 years Magnetic core memory, 1952. IBM. NVRAM 1 5 years Magnetic drum memory. 1950s & 60s. SRAM 1 while powered Secondary storage. DRAM 1 64 ms Memory – p. 4/23 Memory – p. 5/23 Memory – p. 6/23 ROMs EPROMs EEPROM and FLASH Slow write Fowler- Oxide Nordheim Tunneling floating gate Word Line EEPROM: bit at a time Drain (bit line) FLASH: block Source Channel at a time Source: SST Memory – p. 7/23 Memory – p. 8/23 Memory – p. 9/23 Static RAM Cell Standard SRAM: 6264 Standard SRAM: 6264 19±15,13±11 Word D[7:0] ¡£¢ ¤ ¡£¢ ¤ 10±2,25±23,21 8K × 8 Addr[12:0] CS1 ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ 22 Can be very fast: 1CY 626 4 OE ¤ ¡£¢ ¤ ¡£¢ 27 Cypress sells a 55ns WE CS2 20 version ¢ ¢ ¢ ¢ ¢ ¢ ¢ CS1 PRELIMINARY 26 Simple, asynchronous ¡£¢ ¤ CY6264 CS2 WE interface ¢ ¢ 8K x 8 Static RAM ¡£¢ ¤ Bit Bit OE Features over 70% when deselected. The CY6264 is packaged in a ¢ 450-mil (300-mil body) SOIC. • 55, 70 ns access times An active LOW write enable signal (WE) controls the writ- ¥ ¥¦ § § § § § § §¨ ¥ ¥ ¥¦ § § § ¨ § ¥ ¥ ¥ • CMOS for optimum speed/power ing/reading operation of the memory. When CE1 and WE in- Addr • Easy memory expansion with CE1, CE2, and OE fea- puts are both LOW and CE2 is HIGH, data on the eight data tures input/output pins (I/O0 through I/O7) is written into the memory • TTL-compatible inputs and outputs location addressed by the address present on the address § § § § § § § § § § pins (A through A ). Reading the device is accomplished by • Automatic power-down when deselected 0 12 © © © © © © © © © selecting the device and enabling the outputs, CE1 and OE Data Memory – p. 10/23 Memory – p. 11/23 Memory – p. 12/23 Functional Description active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location ad- The CY6264 is a high-performance CMOS static RAM orga- dressed by the information on address pins is present on the nized as 8192 words by 8 bits. Easy memory expansion is eight data input/output pins. provided by an active LOW chip enable (CE1), an active HIGH The input/output pins remain in a high-impedance state unless chip enable (CE2), and active LOW output enable (OE) and the chip is selected, outputs are enabled, and write enable three-state drivers. Both devices have an automatic pow- (WE) is HIGH. A die coat is used to insure alpha immunity. × × er-downStandar feature (CE1)d, reduSRAM:cing the power co6264nsumption by Toshiba TC55V16256J 256K 16 Toshiba TC55V16256J 256K 16 Logic Block Diagram Pin Configuration 38±35,32±29,16±13,10±7 SOIC D[15:0] Top View 23,22,18±21,24±27,42±44,1±5 NC 1 28 VCC Addr[17:0] A4 2 27 WE 40 A5 3 26 CE2 UB I/O0 A6 4 25 A3 A7 5 24 A2 39 INPUT BUFFER A8 6 23 A1 LB I/O1 A9 7 22 OE 41 A10 8 21 A0 OE A11 9 20 CE1 A1 I/O2 A12 10 19 I/O7 17 A2 I/O0 11 18 I/O6 WE A 3 I/O3 I/O1 12 17 I/O5 6 A4 256 x 32 x 8 I/O2 13 16 I/O4 GND I/O CE A5 ARRAY 14 15 3 I/O4 A6 CY6264-2 A7 I/O A8 5 12 or 15 ns access time I/O6 Asynchronous interface POWER CE1 DOWN I/O7 CE2 COLUMN DECODER WE UB, LB select bytes OE CY6264-1 Memory – p. 13/23 Memory – p. 14/23 Memory – p. 15/23 Selection Guide CY6264-55 CY6264-70 DynamicMaximum Access Time (ns)RAM Cell 55 70 Ancient DRAM: 4164 Basic DRAM read and write cycles Maximum Operating Current (mA) 100 100 Maximum Standby Current (mA) 20/15 20/15 Shaded area contains advanced information. 64K × 1 Row Apple IIe vintage ¡£¢ ¤ ¡£¢ ¤ RAS Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ October 1994 – Revised June 1996 9,13,10±12,6,7,5 ¡£¢ ¤ ¡£¢ ¤ Addr[7:0] CAS 2 DIN DOUT 14 ¢ ¢ ¢ ¢ ¢ Column 3 ¦ § § § ¨ § ¥ ¥ ¥ ¥ ¥¦ § § § ¨ § ¥ ¥ ¥ ¥ WE 15 Addr Row Col Row Col CAS 4 RAS Basic problem: Leakage WE ¢ ¢ Solution: Refresh ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥¦ § ¨ § ¥ ¥ ¥ Din § § § © © © © © © © © © © © © © © © © © © © © © Dout © Memory – p. 16/23 Memory – p. 17/23 Memory – p. 18/23 21/23 . p – y Memor E LW LDQM DQi I/O Control Output Buffer DQM L CMOS SDRAM L(U)DQM Rev. 1.2 May. 2003 notice. Sense AMP R ster ation without CB gister W L Re 8 / 2M x 16 8 / 2M x 16 8 / 2M x 16 8 / 2M x 16 & Burst Length or specific s Input a Column Decoder ogramming Regi r Dat 4 / 4M x 4 / 4M x 4 / 4M x 4 / 4M x oduct WE SDRAM P Latency x x x x 8M 8M 8M 8M hange pr CAS S 16 A LC ming Register right to c Row Decoder Col. Buffer i T × the RAS E W L S C lect 8M ics reserves R e Row Buffer LCBR n Refresh Counter LRAS LCB DIAGRAM Bank S KE C LRAS * Samsung Electro Address Register CLK LCKE CLK ADD FUNCTIONAL BLOCK SDRAM 128Mb E-die (x4, x8, x16) Samsung 20/23 23/23 . p p – – y y ¥ © ¥ ¡ © ¥ ¥ ¤ ¤ Memor Memor ¥ © ¥ ¤ ¥ © ¥ ¡ ¡ sts © ¥ ¥ ¡ ¥ ¥ Refresh ¥ ¥ ¤ ur ¥ ¥ R ed) ¥ ¥ ¡ b x Strobe ¥ ¥ le le ¥ ¥ ¤ d ¥ ¥ R Strobe ¥ ¥ ¡ ¥ © ¥ © ¥ ¥ enab or enab ¤ ultiple le ation le © ¥ ¥ ¥ © ¥ ¡ (m © ¤ Address yte yte © ¤ b b oper ¨ © ¡ ¨ Enab 2-w enab C B address © I/O ¡ Address ation k k ¥¦ ¥¦ Read er ¥ ¥ ¤ ite w w ¥ ¥ SDRAM W ¥ ¥ ¡ oper ¦ ¤ ¤ Cloc Cloc Lo Wr Column Ro Bank Address Data Upper ¤ with ¨ ¡ ¡ ¨ ¨ ite C B W 16 ¡ pipelined © ¥ ¥¦ ¦ Wr ¥ © ¥ ¤ × © ¥ ¥ ace © ¥ ¥ ¡ © ¤ © ¤ e © ¡ ¨ ¨ banks; urst-mode R B interf © ¡ 8M b ¥ © ¥¦ ¦ Activ Timing ¥ © ¤ ¥ BA[1:0] Addr[11:0] DQ[15:0] UDQM LDQM WE CAS RAS CKE CLK ate or ¥ ¥ © f ¥ © ¡ ¥ 3 ¥ © ¤ ¤ ¤ 39 15 15 15 37 38 ¤ ¥ © ¥ © ¡ ¡ ¡ ¨ Op ¥ © Load separ 21,20 ¢ ¦ our Clk RAS CAS WE Addr BA DQ F Synchronous Designed Samsung SDRAM: 19/23 22/23 . p p – – y y Memor Memor urst) urst) b b t t CAS w) , star star ro ursts b ¥ § ¥ w) ¥ ¤ § ¤ ¥ ¥ § ¥ ro column, column, ¥ ord ¢ ¥ ¢ register (deselect ¥ ¢ © ¡£¢ §¨ Burst le ¢ ¥ § ¢ ¥ Col ¥ ¢ § ¤ ¢ ¥ ¥ § ¦ (select yc (select (select ¥ ¢ § mode Refresh Signals e ¥ ¢ ¢ c ¢ ¥ ¢ §¨ 1/2/4/8-w minate ite ¥ ¢ © ¡£¢ § ¥ ¢ Col uto ol er ¢ ¥ Precharge A T NOP Load Wr Read Activ action ite ¥ ¢ ¤ ¥ § ¦ ¥ § ¢ ¥ wr ¢ ¥ § ¥ read ¥ ¢ ¢ selects 0 1 0 1 0 0 1 1 ¥ ¢ ¢ : on WE ¢ ¡£¢ § ¥ © ¨ ¥ © ¢ § Contr ¥ © ¢ Col ¢ ¥ © ¥ © ¡£¢ § urst 1 0 1 0 1 0 0 1 w § ¥ © b ¥ © , CAS Ro mode ¥ © register ¦ e 0 0 1 0 1 1 1 0 g Mode latency RAS CAS Addr WE Din Dout RAS a P SDRAM:.
Load more

Recommended publications
  • The Design of a Drum Memory System
    Scholars' Mine Masters Theses Student Theses and Dissertations 1967 The design of a drum memory system Frederick W. Lynch Follow this and additional works at: https://scholarsmine.mst.edu/masters_theses Part of the Electrical and Computer Engineering Commons Department: Recommended Citation Lynch, Frederick W., "The design of a drum memory system" (1967). Masters Theses. 5163. https://scholarsmine.mst.edu/masters_theses/5163 This thesis is brought to you by Scholars' Mine, a service of the Missouri S&T Library and Learning Resources. This work is protected by U. S. Copyright Law. Unauthorized use including reproduction for redistribution requires the permission of the copyright holder. For more information, please contact [email protected]. THE DESIGN OF A DRUM MEMORY SYSTEM BY FREDERICK W. LYNCH A l'HESIS 129533 submitted to the faculty of the UNIVERSITY OF MISSOURI AT ROLLA in partial fulfillment of the requirements for the Degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING Rolla, Missouri I"",,--;;'d I ~ 1967 rfJ·.dfl c, I ii ABSTRACT Three methods for obtaining an auxiliary memory for an SeC-6S0 (Scientific Control Corporation) digital computer are presented. A logic design is then developed on the basis of using the drum and write circuits from an available IBM-6S0 digital computer and con­ structing the remaining logic functions. The results of the logic design are the transfer equations necessary to implement the memory system. iii ACKNOWLEDGMENT The author wishes to express his sincere appreciation to his major professor, Dr. James Tracey, for guidance and support in the preparation of this thesis. iv TABLE OF CONTENTS Page ABSTRACT ii ACKNm>JLEDGlVIENT iii LIST OF FIGURES v LIST OF TABLES vi I.
    [Show full text]
  • DRAM EMAIL GIM Teams!!!/Teaming Issues •Memories in Verilog •Memories on the FPGA
    Memories & More •Overview of Memories •External Memories •SRAM (async, sync) •Flash •DRAM EMAIL GIM teams!!!/teaming Issues •Memories in Verilog •Memories on the FPGA 10/18/18 6.111 Fall 2018 1 Memories: a practical primer • The good news: huge selection of technologies • Small & faster vs. large & slower • Every year capacities go up and prices go down • Almost cost competitive with hard disks: high density, fast flash memories • Non-volatile, read/write, no moving parts! (robust, efficient) • The bad news: perennial system bottleneck • Latencies (access time) haven’t kept pace with cycle times • Separate technology from logic, so must communicate between silicon, so physical limitations (# of pins, R’s and C’s and L’s) limit bandwidths • New hopes: capacitive interconnect, 3D IC’s • Likely the limiting factor in cost & performance of many digital systems: designers spend a lot of time figuring out how to keep memories running at peak bandwidth • “It’s the memory - just add more faster memory” 10/18/18 6.111 Fall 2018 2 How do we Electrically Remember Things? • We can convey/transfer information with voltages that change over time • How can we store information in an electrically accessible manner? • Store in either: • Electric Field • Magnetic Field 10/18/18 6.111 Fall 2018 3 Mostly focus on rewritable • Punched Cards have existed as electromechanical program storage since ~1800s • We’re mostly concerned with rewritable storage mechanisms today (cards were true Computer program in punched card format ROMs) https://en.wiKipedia.org/wiKi/Computer_programming_in_the_
    [Show full text]
  • Magnetic Storage- Magnetic-Core Memory, Magnetic Tape,RAM
    Magnetic storage- From magnetic tape to HDD Juhász Levente 2016.02.24 Table of contents 1. Introduction 2. Magnetic tape 3. Magnetic-core memory 4. Bubble memory 5. Hard disk drive 6. Applications, future prospects 7. References 1. Magnetic storage - introduction Magnetic storage: Recording & storage of data on a magnetised medium A form of „non-volatile” memory Data accessed using read/write heads Widely used for computer data storage, audio and video applications, magnetic stripe cards etc. 1. Magnetic storage - introduction 2. Magnetic tape 1928 Germany: Magnetic tape for audio recording by Fritz Pfleumer • Fe2O3 coating on paper stripes, further developed by AEG & BASF 1951: UNIVAC- first use of magnetic tape for data storage • 12,7 mm Ni-plated brass-phosphorus alloy tape • 128 characters /inch data density • 7000 ch. /s writing speed 2. Magnetic tape 2. Magnetic tape 1950s: IBM : patented magnetic tape technology • 12,7 mm wide magnetic tape on a 26,7 cm reel • 370-730 m long tapes 1980: 1100 m PET –based tape • 18 cm reel for developers • 7, 9 stripe tapes (8 bit + parity) • Capacity up to 140 MB DEC –tapes for personal use 2. Magnetic tape 2014: Sony & IBM recorded 148 Gbit /squareinch tape capacity 185 TB! 2. Magnetic tape Remanent structural change in a magnetic medium Analog or digital recording (binary storage) Longitudinal or perpendicular recording Ni-Fe –alloy core in tape head 2. Magnetic tape Hysteresis in magnetic recording 40-150 kHz bias signal applied to the tape to remove its „magnetic history” and „stir” the magnetization Each recorded signal will encounter the same magnetic condition Current in tape head proportional to the signal to be recorded 2.
    [Show full text]
  • Influence of U.S. Cryptologic Organizations on the Digital Computer Industry
    UNCLASSIFIED Influence of U.S. Cryptologic Organizations on the Digital Computer Industry SAMUELS. SNYDER This article was originally published in two parts in the Fall 1977 and Winter 1978 issues o{Cryptologic Spectrum (Vol. 7, No. 4 and Vol. 8, No. 2). INTRODUCTION An unfortunate aspect of historical accounts of computer lore in open sources is the omission - conspicuously to some of us - of mention of the U.S. cryptologic organizations, or of the contributions by these organizations which helped in laying the foundation of the computer industry. NSA, and other cryptologic organizations, have been required over the years to observe a policy of anonymity, and with good reason. But in the age of maturing appreciation of the role of computers in nearly all civilized endeavors, it is time to acknowledge, for the first time, their outstanding contributions to the computer industry. The reader will notice the absence of remarks concerning software efforts by cryptologic organizations. While this side of their operations received its proper share of support, space restrictions preclude its inclusion in this article. Also, the Army and Navy cryptologic services have frequently changed organizational titles throughout the years. Therefore, to avoid confusion in this article, they are, previous to 1945, referred to as "Army," "Navy," "service cryptologic organizations," and the like. Too, NSA's predecessor organization, AFSA, was established in 1949, and NSA in 1952. Consequently, references to "NSA" and "Agency" are, on occasion, used interchangeably, the particular agency referred to depending upon the time period being discussed. EARLY DEVELOPMENTS The development of the U.S. computer industry might have been delayed for years ifit had not been for the stimulus and financial support of the U.S.
    [Show full text]
  • Computer Peripheral Memory System Forecast
    OF NBS H^^LK,!,, STAND S. TECH PUBLICATIONS | COMPUTER SUici^CZ^i TECHNOLOGY: COMPUTER PERIPHERAL MEMORY SYSTEM FORECAST QC 100 U57 NBS Special Publication 500-45 #500-45 U.S. DEPARTMENT OF COMMERCE 1979 National Bureau of Standards NATIONAL BUREAU OF STANDARDS The National Bureau of Standards' was established by an act of Congress March 3, 1901 . The Bureau's overall goal is to strengthen and advance the Nation's science and technology and facilitate their effective application for public benefit. To this end, the Bureau conducts research and provides: (1) a basis for the Nation's physical measurement system, (2) scientific and technological services for industry and government, (3) a technical basis for equity in trade, and (4) technical services to promote public safety. The Bureau's technical work is performed by the National Measurement Laboratory, the National Engineering Laboratory, and the Institute for Computer Sciences and Technology. THE NATIONAL MEASUREMENT LABORATORY provides the national system of physical and chemical and materials measurement; coordinates the system with measurement systems of other nations and furnishes essential services leading to accurate and uniform physical and chemical measurement throughout the Nation's scientific community, industry, and commerce; conducts materials research leading to improved methods of measurement, standards, and data on the properties of materials needed by industry, commerce, educational institutions, and Government; provides advisory and research services to other Government Agencies; develops, produces, and distributes Standard Reference Materials; and provides calibration services. The Laboratory consists of the following centers: Absolute Physical Quantities^ — Radiation Research — Thermodynamics and Molecular Science — Analytical Chemistry — Materials Science.
    [Show full text]
  • 2129710142200313CSE312 Amir Adel Salah.Pdf
    استمارة جقييم الزسائل البحثيت ملقزر دراس ي اوﻻ : بياهاث جمل بمعزفت الطالب اسم الطالبـــــــــــ :أم ري عادل صﻻح عبد العظيم كلية : الهندســــه القسم: الحاسبات و النظم الفرقة/المستوى : الثالثة الشعبة : اسم المقرر :بنية الحاسب كود المقرر : CSE312 استاذ المقرر : د.طارق مراد جمعة ر ال رييد اﻻلكيون [email protected] : للطالب عنوان الرسالة البحثية : Modern Computers Memory ثاهيا: بياهاث جمل بمعزفت لجىت املمتحىيين هل الزسالت البحثيت املقدمت متشابت جشئيا او كليا ☐ وعم ☐ ﻻ فى حالت الاجابت بىعم ﻻ يتم جقييم املشزوع البحثى ويعتبر غير مجاس جقييم املشزوع البحثى م عىاصز التقييم الوسن التقييم اليسبى 1 الشكل العام للزسالت البحثيت 2 جحقق املتطلباث العلميت املطلوبت 3 يذكز املزاجع واملصادر العلميت 4 الصياغت اللغويت واسلوب الكتابت جيد هتيجت التقييم النهائى 100/ ☐ هاجح ☐ راسب جوقيع لجىت التقييم 1. .2 .3 .4 .5 جزفق هذه الاستمارة كغﻻف للمشزوع البحثى بعد استكمال البياهاث بمعزفت الطالب وعلى ان ﻻ جشيد عً صفحت واحدة Computers Memory Introduction At the beginning of the age of technology , A new term name called Memory has appeared .The memory is the most important thing in Computer . it is the main item which is responsible for data storage. The memories were designed by different ways and through multiple stages. At the beginning of memory manufacturing, the memory was produced by vacuum tubes from 1946 to 1959 .Vacuum tubes were basic components which was used to make the first generation of memories . Also the vacuum tubes used to make circuitry of CPU (Central Processing unit).In this generation ,the basic programming language was machine code which used in computers used vacuum tubes in the memory.
    [Show full text]
  • Memory Krste Asanovic [email protected]
    CS252 Graduate Computer Architecture Fall 2015 Lecture 11: Memory Krste Asanovic [email protected] http://inst.eecs.berkeley.edu/~cs252/fa15 CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 Last Time in Lecture 10 VLIW Machines § Compiler-controlled stac scheduling § Loop unrolling § SoEware pipelining § Trace scheduling § Rotang register file § Predicaon § Limits of stac scheduling CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 2 Early Read-Only Memory Technologies Punched cards, From early 1700s through Jaquard Loom, Punched paper tape, Babbage, and then IBM instrucCon stream in Harvard Mk 1 Diode Matrix, EDSAC-2 µcode store IBM Balanced Capacitor ROS IBM Card Capacitor ROS CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 3 Early Read/Write Main Memory Technologies Babbage, 1800s: Digits stored on mechanical wheels Williams Tube, Manchester Mark 1, 1947 Mercury Delay Line, Univac 1, 1951 Also, regenerave capacitor memory on Atanasoff-Berry computer, and rotang magneCc drum memory on IBM 650 CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 4 MIT Whirlwind Core Memory CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 5 Core Memory § Core memory was first large scale reliable main memory - invented by Forrester in late 40s/early 50s at MIT for Whirlwind project § Bits stored as magneCzaon polarity on small ferrite cores threaded onto two-dimensional grid of wires § Coincident current pulses on X and Y wires would write cell and also sense original state (destrucCve reads) § Robust, non-volale storage § Used on space shugle computers § Cores threaded onto wires by hand (25 billion a year at peak producCon) § Core access Cme ~ 1µs DEC PDP-8/E Board, 4K words x 12 bits, (1968) CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 6 Semiconductor Memory § Semiconductor memory began to be compeCCve in early 1970s - Intel formed to exploit market for semiconductor memory - Early semiconductor memory was Stac RAM (SRAM).
    [Show full text]
  • Lecture 8: Main Memory System
    18-740/640 Computer Architecture Lecture 8: Main Memory System Prof. Onur Mutlu Carnegie Mellon University Fall 2015, 9/28/2015 Required Readings Required Reading Assignment: • Sec. 1 & 3 of B. Jacob, “The Memory System: You Can’t Avoid It, You Can’t Ignore It, You Can’t Fake It,” Synthesis Lectures on Computer Architecture, 2009. Recommended References: • O. Mutlu and L. Subramanian, “Research Problems and Opportunities in Memory Systems,” Supercomputing Frontiers and Innovations, 2015. • Lee et al., “Phase Change Technology and the Future of Main Memory,” IEEE Micro, Jan/Feb 2010. • Y. Kim, W. Yang, O. Mutlu, “Ramulator: A Fast and Extensible DRAM Simulator,” IEEE Computer Architecture Letters, May 2015. 2 State-of-the-art in Main Memory… Onur Mutlu and Lavanya Subramanian, "Research Problems and Opportunities in Memory Systems" Invited Article in Supercomputing Frontiers and Innovations (SUPERFRI), 2015. 3 Recommended Readings on DRAM DRAM Organization and Operation Basics Sections 1 and 2 of: Lee et al., “Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture,” HPCA 2013. http://users.ece.cmu.edu/~omutlu/pub/tldram_hpca13.pdf Sections 1 and 2 of Kim et al., “A Case for Subarray-Level Parallelism (SALP) in DRAM,” ISCA 2012. http://users.ece.cmu.edu/~omutlu/pub/salp-dram_isca12.pdf DRAM Refresh Basics Sections 1 and 2 of Liu et al., “RAIDR: Retention-Aware Intelligent DRAM Refresh,” ISCA 2012. http://users.ece.cmu.edu/~omutlu/pub/raidr-dram- refresh_isca12.pdf 4 Simulating Main Memory How to evaluate future main memory systems? An open-source simulator and its brief description Yoongu Kim, Weikun Yang, and Onur Mutlu, "Ramulator: A Fast and Extensible DRAM Simulator" IEEE Computer Architecture Letters (CAL), March 2015.
    [Show full text]
  • Random Access Memory (Ram)
    www.studymafia.org A Seminar report On RANDOM ACCESS MEMORY (RAM) Submitted in partial fulfillment of the requirement for the award of degree of Bachelor of Technology in Computer Science SUBMITTED TO: SUBMITTED BY: www.studymafia.org www.studymafia.org www.studymafia.org Acknowledgement I would like to thank respected Mr…….. and Mr. ……..for giving me such a wonderful opportunity to expand my knowledge for my own branch and giving me guidelines to present a seminar report. It helped me a lot to realize of what we study for. Secondly, I would like to thank my parents who patiently helped me as i went through my work and helped to modify and eliminate some of the irrelevant or un-necessary stuffs. Thirdly, I would like to thank my friends who helped me to make my work more organized and well-stacked till the end. Next, I would thank Microsoft for developing such a wonderful tool like MS Word. It helped my work a lot to remain error-free. Last but clearly not the least, I would thank The Almighty for giving me strength to complete my report on time. www.studymafia.org Preface I have made this report file on the topic RANDOM ACCESS MEMORY (RAM); I have tried my best to elucidate all the relevant detail to the topic to be included in the report. While in the beginning I have tried to give a general view about this topic. My efforts and wholehearted co-corporation of each and everyone has ended on a successful note. I express my sincere gratitude to …………..who assisting me throughout the preparation of this topic.
    [Show full text]
  • History Timeline by Jeff Drobman (C) 2015 === 1889 - Punch Cards - Herman Hollerith (Of IBM Forerunner) Invented "IBM" Punch Cards to Be Used for the 1890 Census
    Computer Memory History Timeline by Jeff Drobman (C) 2015 === 1889 - Punch cards - Herman Hollerith (of IBM forerunner) invented "IBM" punch cards to be used for the 1890 census. 1932 - Drum memory 1947 - Delay line memory 1949 - Magnetic CORE memory 1950 - Magnetic TAPE memory 1955 - Magnetic DISK memory - IBM RAMAC was first one 1957 - Plated wire memory 1962 - Thin film memory 1968 (ca) - Paper tape - Had beginnings dating back to 1846, but became widely used with teletype machines such as the Teletype Model 33 ASR, which were adopted early on by minicomputers as a primitive terminal. 1970 - Bubble memory 1970 - DRAM - Invented by Intel, first device was the 1101, organized as 256x1, followed by the 4x larger (1024x1) 1103(A) -- regarded as the world's first commercial DRAM (intro in October 1970). 1971 - Bipolar SRAM - Fairchild 256x1 (note IBM made a 16-bit SRAM in late 1960s. AMD made a second source of a 64x1 SRAM by Fairchild in 1971.) 1971 - EPROM - Invented by Dov Frohman of Intel as the i1702, a 2K-bit (256x8) EPROM. 1971 - "Floppy" disks -- First were 8-inch, hence very flexible ("floppy"). The 8" became commercially available in 1971. 1973 (ca) - Magnetic TAPE CASSETTE memory 1976 - Shugart Associates introduced the first 5¼-inch floppy (flexible) disk drive 1977 - EEPROM - invented by Eli Harari at Hughes - a BYTE erasable device 1979 - CMOS SRAM (static RAM, 4T/6T cell, implemented as a latch) - first introduced by HP then its spinoff as Integrated Device Technology. I believe first devices were 1K (1024x1), and later organized as x4 then x8.
    [Show full text]
  • History of Digital Storage White Paper
    History of Digital Storage Dean Klein Vice President of System Memory Development Micron Technology, Inc. December 15, 2008 Purpose Introduction: Throughout modern history many and various digital The Need to Store Data storage systems have been researched, developed, Since men first scribbled on cave walls, humanity has manufactured, and eventually surpassed in an effort to recognized the instrinic value of information and has address ever-increasing demands for density, operating employed a variety of ways and means to safely store speed, low latency, endurance, and economy.1 This cycle it. The ability to reference numbers for calculation or to of innovation has lead us to a new generation of NAND review information for planning, learning, and action Flash memory-based solid state drives (SSDs) that repre- is fundamental since “all computations, either mental, sent the next evolutionary step in both enterprise and mechanical, or electronic require a storage system of consumer storage applications. some kind, whether the numbers be written on paper, remembered in our brain, counted on the mechanical This paper surveys the memory storage landscape of devices of a gear, punched as holes in paper, or translated the past 50 years—starting at the beginning of digital into electronic circuitry.”2 storage and paying homage to IBM’s groundbreaking RAMAC disk storage unit and StorageTek’s DRAM-based In day-to-day life, this fundamental need to store data SSD; then enumerating the benefits of modern NAND generates innumerable documents, spreadsheets, files, Flash memory and advanced SSDs; and finally looking e-mails, and trillions of other work-related bytes all forward to the near-future possibilities of nonvolatile stored on disks around the globe.
    [Show full text]
  • History of Computer Memory * in 1932 Gustav Tauschek Invents Drum
    History of Computer Memory * In 1932 Gustav Tauschek invents drum memory in Austria. * 1936 Konrad Zuse applies for a patent for his mechanical memory to be used in his computer. This computer memory is based on sliding metal parts. * 1939 Helmut Schreyer invents a prototype memory using neon lamps. * 1942 The Atanasoff-Berry Computer has 60 50-bit words of memory in the form of capacitors mounted on two revolving drums. For secondary memory it uses punch cards. * 1947 Frederick Viehe of Los Angeles, applies for a patent for an invention that uses magnetic core memory. Magnetic drum memory is independently invented by several people. * 1949 Jay Forrester conceives the idea of magnetic core memory as it is to become commonly used, with a grid of wires used to address the cores. The first practical form manifests in 1952-53 and renders obsolete previous types of computer memory. * 1950 Ferranti Ltd. completes the first commercial computer with 256 40-bit words of main memory and 16K words of drum memory. Only eight were sold. * 1951 Jay Forrester files a patent for matrix core memory. * 1952 The EDVAC computer is completed with 1024 44-bit words of ultrasonic memory. A core memory module is added to the ENIAC computer. * 1955 An Wang was issued U.S. patent #2,708,722 with 34 claims for magnetic memory core. * 1966 Hewlett-Packard releases their HP2116A real-time computer with 8K of memory. The newly formed Intel starts sell a semiconductor chip with 2,000 bits of memory. * 1968 USPTO grants patent 3,387,286 to IBM's Robert Dennard for a one-transistor DRAM cell.
    [Show full text]