Early Memories Early Memories Memory Prof. Stephen A. Edwards [email protected] NCTU, Summer 2005 Williams Tube CRT-based random access memory, 1946. Used on the Manchester Mark I. 2048 bits. Mercury acoustic delay line. Used in the EDASC, 1947. 32 × 17 bits Memory – p. 1/23 Memory – p. 2/23 Memory – p. 3/23 Early Memories Early Memories Modern Memory Choices Family Programmed Persistence Mask ROM at fabrication 1 PROM once 1 EPROM 1000s, UV 10 years FLASH 1000s, block 10 years EEPROM 1000s, byte 10 years Magnetic core memory, 1952. IBM. NVRAM 1 5 years Magnetic drum memory. 1950s & 60s. SRAM 1 while powered Secondary storage. DRAM 1 64 ms Memory – p. 4/23 Memory – p. 5/23 Memory – p. 6/23 ROMs EPROMs EEPROM and FLASH Slow write Fowler- Oxide Nordheim Tunneling floating gate Word Line EEPROM: bit at a time Drain (bit line) FLASH: block Source Channel at a time Source: SST Memory – p. 7/23 Memory – p. 8/23 Memory – p. 9/23 Static RAM Cell Standard SRAM: 6264 Standard SRAM: 6264 19±15,13±11 Word D[7:0] ¡£¢ ¤ ¡£¢ ¤ 10±2,25±23,21 8K × 8 Addr[12:0] CS1 ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ 22 Can be very fast: 1CY 626 4 OE ¤ ¡£¢ ¤ ¡£¢ 27 Cypress sells a 55ns WE CS2 20 version ¢ ¢ ¢ ¢ ¢ ¢ ¢ CS1 PRELIMINARY 26 Simple, asynchronous ¡£¢ ¤ CY6264 CS2 WE interface ¢ ¢ 8K x 8 Static RAM ¡£¢ ¤ Bit Bit OE Features over 70% when deselected. The CY6264 is packaged in a ¢ 450-mil (300-mil body) SOIC. • 55, 70 ns access times An active LOW write enable signal (WE) controls the writ- ¥ ¥¦ § § § § § § §¨ ¥ ¥ ¥¦ § § § ¨ § ¥ ¥ ¥ • CMOS for optimum speed/power ing/reading operation of the memory. When CE1 and WE in- Addr • Easy memory expansion with CE1, CE2, and OE fea- puts are both LOW and CE2 is HIGH, data on the eight data tures input/output pins (I/O0 through I/O7) is written into the memory • TTL-compatible inputs and outputs location addressed by the address present on the address § § § § § § § § § § pins (A through A ). Reading the device is accomplished by • Automatic power-down when deselected 0 12 © © © © © © © © © selecting the device and enabling the outputs, CE1 and OE Data Memory – p. 10/23 Memory – p. 11/23 Memory – p. 12/23 Functional Description active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location ad- The CY6264 is a high-performance CMOS static RAM orga- dressed by the information on address pins is present on the nized as 8192 words by 8 bits. Easy memory expansion is eight data input/output pins. provided by an active LOW chip enable (CE1), an active HIGH The input/output pins remain in a high-impedance state unless chip enable (CE2), and active LOW output enable (OE) and the chip is selected, outputs are enabled, and write enable three-state drivers. Both devices have an automatic pow- (WE) is HIGH. A die coat is used to insure alpha immunity. × × er-downStandar feature (CE1)d, reduSRAM:cing the power co6264nsumption by Toshiba TC55V16256J 256K 16 Toshiba TC55V16256J 256K 16 Logic Block Diagram Pin Configuration 38±35,32±29,16±13,10±7 SOIC D[15:0] Top View 23,22,18±21,24±27,42±44,1±5 NC 1 28 VCC Addr[17:0] A4 2 27 WE 40 A5 3 26 CE2 UB I/O0 A6 4 25 A3 A7 5 24 A2 39 INPUT BUFFER A8 6 23 A1 LB I/O1 A9 7 22 OE 41 A10 8 21 A0 OE A11 9 20 CE1 A1 I/O2 A12 10 19 I/O7 17 A2 I/O0 11 18 I/O6 WE A 3 I/O3 I/O1 12 17 I/O5 6 A4 256 x 32 x 8 I/O2 13 16 I/O4 GND I/O CE A5 ARRAY 14 15 3 I/O4 A6 CY6264-2 A7 I/O A8 5 12 or 15 ns access time I/O6 Asynchronous interface POWER CE1 DOWN I/O7 CE2 COLUMN DECODER WE UB, LB select bytes OE CY6264-1 Memory – p. 13/23 Memory – p. 14/23 Memory – p. 15/23 Selection Guide CY6264-55 CY6264-70 DynamicMaximum Access Time (ns)RAM Cell 55 70 Ancient DRAM: 4164 Basic DRAM read and write cycles Maximum Operating Current (mA) 100 100 Maximum Standby Current (mA) 20/15 20/15 Shaded area contains advanced information. 64K × 1 Row Apple IIe vintage ¡£¢ ¤ ¡£¢ ¤ RAS Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ October 1994 – Revised June 1996 9,13,10±12,6,7,5 ¡£¢ ¤ ¡£¢ ¤ Addr[7:0] CAS 2 DIN DOUT 14 ¢ ¢ ¢ ¢ ¢ Column 3 ¦ § § § ¨ § ¥ ¥ ¥ ¥ ¥¦ § § § ¨ § ¥ ¥ ¥ ¥ WE 15 Addr Row Col Row Col CAS 4 RAS Basic problem: Leakage WE ¢ ¢ Solution: Refresh ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥¦ § ¨ § ¥ ¥ ¥ Din § § § © © © © © © © © © © © © © © © © © © © © © Dout © Memory – p. 16/23 Memory – p. 17/23 Memory – p. 18/23 21/23 . p – y Memor E LW LDQM DQi I/O Control Output Buffer DQM L CMOS SDRAM L(U)DQM Rev. 1.2 May. 2003 notice. Sense AMP R ster ation without CB gister W L Re 8 / 2M x 16 8 / 2M x 16 8 / 2M x 16 8 / 2M x 16 & Burst Length or specific s Input a Column Decoder ogramming Regi r Dat 4 / 4M x 4 / 4M x 4 / 4M x 4 / 4M x oduct WE SDRAM P Latency x x x x 8M 8M 8M 8M hange pr CAS S 16 A LC ming Register right to c Row Decoder Col. Buffer i T × the RAS E W L S C lect 8M ics reserves R e Row Buffer LCBR n Refresh Counter LRAS LCB DIAGRAM Bank S KE C LRAS * Samsung Electro Address Register CLK LCKE CLK ADD FUNCTIONAL BLOCK SDRAM 128Mb E-die (x4, x8, x16) Samsung 20/23 23/23 . p p – – y y ¥ © ¥ ¡ © ¥ ¥ ¤ ¤ Memor Memor ¥ © ¥ ¤ ¥ © ¥ ¡ ¡ sts © ¥ ¥ ¡ ¥ ¥ Refresh ¥ ¥ ¤ ur ¥ ¥ R ed) ¥ ¥ ¡ b x Strobe ¥ ¥ le le ¥ ¥ ¤ d ¥ ¥ R Strobe ¥ ¥ ¡ ¥ © ¥ © ¥ ¥ enab or enab ¤ ultiple le ation le © ¥ ¥ ¥ © ¥ ¡ (m © ¤ Address yte yte © ¤ b b oper ¨ © ¡ ¨ Enab 2-w enab C B address © I/O ¡ Address ation k k ¥¦ ¥¦ Read er ¥ ¥ ¤ ite w w ¥ ¥ SDRAM W ¥ ¥ ¡ oper ¦ ¤ ¤ Cloc Cloc Lo Wr Column Ro Bank Address Data Upper ¤ with ¨ ¡ ¡ ¨ ¨ ite C B W 16 ¡ pipelined © ¥ ¥¦ ¦ Wr ¥ © ¥ ¤ × © ¥ ¥ ace © ¥ ¥ ¡ © ¤ © ¤ e © ¡ ¨ ¨ banks; urst-mode R B interf © ¡ 8M b ¥ © ¥¦ ¦ Activ Timing ¥ © ¤ ¥ BA[1:0] Addr[11:0] DQ[15:0] UDQM LDQM WE CAS RAS CKE CLK ate or ¥ ¥ © f ¥ © ¡ ¥ 3 ¥ © ¤ ¤ ¤ 39 15 15 15 37 38 ¤ ¥ © ¥ © ¡ ¡ ¡ ¨ Op ¥ © Load separ 21,20 ¢ ¦ our Clk RAS CAS WE Addr BA DQ F Synchronous Designed Samsung SDRAM: 19/23 22/23 . p p – – y y Memor Memor urst) urst) b b t t CAS w) , star star ro ursts b ¥ § ¥ w) ¥ ¤ § ¤ ¥ ¥ § ¥ ro column, column, ¥ ord ¢ ¥ ¢ register (deselect ¥ ¢ © ¡£¢ §¨ Burst le ¢ ¥ § ¢ ¥ Col ¥ ¢ § ¤ ¢ ¥ ¥ § ¦ (select yc (select (select ¥ ¢ § mode Refresh Signals e ¥ ¢ ¢ c ¢ ¥ ¢ §¨ 1/2/4/8-w minate ite ¥ ¢ © ¡£¢ § ¥ ¢ Col uto ol er ¢ ¥ Precharge A T NOP Load Wr Read Activ action ite ¥ ¢ ¤ ¥ § ¦ ¥ § ¢ ¥ wr ¢ ¥ § ¥ read ¥ ¢ ¢ selects 0 1 0 1 0 0 1 1 ¥ ¢ ¢ : on WE ¢ ¡£¢ § ¥ © ¨ ¥ © ¢ § Contr ¥ © ¢ Col ¢ ¥ © ¥ © ¡£¢ § urst 1 0 1 0 1 0 0 1 w § ¥ © b ¥ © , CAS Ro mode ¥ © register ¦ e 0 0 1 0 1 1 1 0 g Mode latency RAS CAS Addr WE Din Dout RAS a P SDRAM:.