CPU Technologies for Networks and Multimedia 40 CPU Technologies for Networks and Multimedia

Kunio Uchiyama OVERVIEW: Hitachi has put the H8/300 and H8/300L series 8-bit Hirofumi Mukai microcomputers, the H8/300H, H8S/2000 and H8S/2600 series 16-bit microcomputers and the SuperH RISC engine series 32-bit microcomputer Ikuya Kawasaki into commercial production to meet the various requirements placed on Tsuguji Tachiuchi electronic appliances in the consumer product, information, communications and industrial fields. Upward compatibility is maintained throughout the H8/H8S series, from the H8/300L at the low end to the H8S/2600 model at the high end. The series includes inexpensive and reduced power consumption models with limited numbers of pins, the world’s highest level CPU core for 16-bit microcomputer performance, large amounts of on- chip flash memory and a variety of peripheral modules, and allows you to select the combination that best suits your system. The SuperH RISC engine series allows you to freely select from among CPU cores with 26 to 360 MIPS (million instructions per second) performance based on our 16-bit, fixed-length instruction RISC (reduced instruction set computer) architecture. This series includes SH2-DSP/SH3-DSP models that incorporate DSPs (digital signal processors) and vector-type FPUs (floating- point units) for which there is strong demand from the network and multimedia fields. Hitachi has also developed the SH-5 with performance in the 1,000-MIPS class and an architecture expanded to 64 bits as the next-generation processor. Hitachi has also developed middleware for voice, image, audio and communications applications, to be run mainly on the SuperH RISC engines. It is very easy to construct products for network and multimedia applications on the basis of the middleware.

INTRODUCTION are absolutely necessary for constructing systems MICROCOMPUTERS are used in a variety of around these CPUs (central processing units) and electronic appliances in the consumer product, microcomputers, in view of the current trends in the information, communications and industrial fields. twin areas of network and multimedia technologies. These appliances have become more widely used as a result of the widespread use of the Internet and advance H8/H8S SERIES in multimedia, and the result has been a need for a Product Development more diverse range of microcomputers. Hitachi has commercially produced H8/300 and Hitachi has put the H8/300 and H8/300L series 8- H8/300L series 8-bit microcomputers and H8/300H bit microcomputers, the H8/300H, H8S/2000 and H8S/ and H8S (H8S/2000, H8S/2600) series 16-bit 2600 series 16-bit microcomputers and the SuperH microcomputers to meet various requirements for RISC engine series 32-bit microcomputers into electronic appliances in the consumer-product, commercial production to meet a variety of information and industrial fields (see Fig. 2). All of requirements for performance, price, power the series provide upward-compatibility at the object consumption and functionality (see Fig. 1). level, allowing easy migration to higher-level models We will also explain the current situation regarding when users require improved performance. The H8S our development of middleware, i.e., programs that series achieves the world’s highest rate of operation Hitachi Review Vol. 50 (2001), No. 2 41

RISC: reduced instruction set computer DSP: digital signal processor MIPS: million instructions per second

1,000 SH-5 SuperH RISC engine series SH-4 SH3-DSP SH-3 100 (a) SH3-DSP SH2-DSP H8S series SH-2 SH-1 H8S/2600 H8S/2000 Performance (MIPS) 10 H8/300H Fig. 1— Product Development of the H8/300H Tiny H8, H8S and SuperH RISC Engine H8/300 Series. H8/300L H8 series Hitachi has developed a wide range of CPUs, from the 8-bit H8 series to 1 (b) H8S/2636F the 32- to 64-bit SuperH RISC engine series.

or Flexible Zero Turnaround Time versions). This 0.18-µm technology allows programs to be written or modified on the board; 100 the mass assembly lines can thus be simplified; and 0.35-µm technology H8S/xxx maintenance after shipment is easy. These products allow internal flash memory capacities of up to 512 ¥ Printer H8S/2600 ¥ Industrial network kbytes. H8/yyy ¥ Optical disc H8S/2000 ¥ Pager, Bluetooth Applications 10 H8/300H H8/300H Tiny Fig. 2 shows representative fields of application H8/300 ¥ Home network for each series. For the H8/300H Tiny series, Hitachi ¥ Personal computer peripherals H8/300L has succeeded in realizing a low price for a product

CPU operating frequency (MHz) with fewer than 64 pins. Products in the series can be 8-bit microcomputer 16-bit microcomputer configured to contain a variety of modules that 1 represent intellectual property (IPs); the I2C bus, the LPC (low pin count) bus advocated by Intel Corp., or Fig. 2— Product Development and Major Applications of the the USB (universal serial bus) for application to home H8/H8S Series. networks and personal computer peripherals. Products The H8/H8S series meet the various requirements of electronic in the H8S/2000 series are ideal for use in mobile appliances in the consumer product, information, and industrial appliances that call for low power consumption. fields. Typical applications include pagers, Bluetooth devices, MD (mini-disc) players, etc. The H8/300H and H8S/ 2600 series can be used in applications to do with at 18.9 MIPS (for operation on 3.3 V at 33 MHz), optical discs [CD-R/RWs (compact disc, recordable/ where each basic instruction is executed within 1 cycle rewritable), DVD-ROMs (digital versatile disc, read- and the internal memory is accessed within 1 cycle. only memory)], printers, and automobile/industrial Products in the series are also able to execute networks. An IP module for USB and CAN (controller multiplication and multiply & accumulate operations area network) realizes a high-speed and highly reliable in 4 cycles. In both the H8 and H8S series, products communications protocol, and is available for are also available with internal flash memory (F-ZTAT, connection to the CPU cores of this series. CPU Technologies for Networks and Multimedia 42 SuperH RISC engine SERIES H8S/2636F Product Development 128-kbyte The SuperH RISC engine series, which is suitable flash memory CPU 4-kbyte RAM for use in small mobile information appliances and TPU DTC × 1 channel SCI × 3 channels digital appliances, was developed to meet requirements for well-balanced performance, power consumption PWM timer (10 bits) A/D × 12 channels (10 bits) and price. Fig. 4 shows the development of products in this series. Development of the CPU cores, from CAN × 2 channels the SH-1 to SH-4 was based on a compact, low power consumption CPU with a 16-bit, fixed-length High-speed CAN Low-speed CAN instruction RISC (reduced instruction set computer)

TPU: timer pulse unit PWM: pulse width modulation architecture, to which a cache memory, an MMU DTC: data transfer controller A/D: analog/digital (memory-management unit), a DSP (digital signal SCI: serial communication interface processor), an FPU (floating-point unit) and the Fig. 3— Functions of the H8S/2636F for Controlling superscalar method have been added. The architecture Automobile/Industrial Networks. of the SH-5, designed for next-generation networks The H8S/2636F provides a gateway function for two CAN- and multimedia products, has been expanded from 32 interface channels. bits to 64 bits and uses SIMD (single instruction, multiple data) instructions. This series is also ideal for use in a variety of applications, thanks to product Fig. 3 shows the functions of the H8S/2636F that development that has covered a wide range of variants is in commercial production as a product for the control in terms of frequency, flash memory, ROM, RAM of automobile/industrial networks. This (random access memory), and peripheral functionality. microcomputer incorporates the high-speed CPU core By 1999, Hitachi had shipped more than 100 of the H8S/2600 series and 128 kbytes of flash million SuperH RISC engines. The series has been memory. It has two 1 Mbit/s CAN interface channels widely adopted for industrial, OA (office automation)/ and is able to control high-speed and low-speed CAN computer, consumer product, communications and buses as well as the interfaces required to exchange automotive applications, and Hitachi intends to information on both buses. positively develop this series further in the future.

64-bit SIMD architecture SH-5 SH8000 series 700 Ð 1,000 MIPS Superscalar with internal FPU SH-4 230 Ð 360 MIPS SH7750 series High-speed peripherals Internal DSP SH3-DSP 173 MIPS/266 MOPS SH7720 series High-speed edition Internal MMU and cache memory SH-3 59 Ð 173 MIPS SH7700 series High-speed edition Internal DSP Flash memory and development of new models SH-DSP SH7610 series SH7060 series Next-generation, high- 78 MIPS/120 MOPS performance, single chip Internal cache memory Flash memory, timers and peripherals Fig. 4— Development SH-2 SH7050 series SH7600 series Single chip for controlling of the SuperH RISC 37 MIPS SH7040 series next-generation engines engine Series. SH-1 SH7030 series The SuperH RISC 26 MIPS SH7020 series engine series provides a wide Core development Product development range of solutions for Processor development Single-chip development network-related and MOPS: mega operations per second multimedia equipment. Hitachi Review Vol. 50 (2001), No. 2 43

CPU core with built-in RISC and DSP Human-machine interface control System control RISC SH3-DSP core Fig. 5— Design Concept of the SH3- General-purpose processing ¥ 173 MIPS DSP. (OS, high-level ¥ 266 MOPS The SH3-DSP architecture programming ¥ 16-kbyte cache language) incorporates both RISC and DSP memory Graphics processing ¥ 16-kbyte RAM units, allowing the efficient Voice processing DSP ¥ Internal MMU execution of both general-purpose Communications processing High-speed signal ¥ Single-cycle multiply processing and signal-processing operations by & accumulate the CPU.

MH: modified huffman MR: modified read MMR: modified modified read SH-4 PIAFS: personal handyphone system Internet Data access forum standard ADPCM: adaptive differential pulse code modulation Modem Voice JBIG: joint bi-level image experts group SH-3 56 kbps 33.6 kbps * Java, and all trademarks and logos related to 28.8 kbps Java, are trademarks or registered trademarks of Sun Microsystems, Inc. in the U.S.A. and other Voice recognition Audio countries. SH-2 Java* Voice CODEC AAC G.723, G.729 PIAFS Dolby-AC3 H.323 Voice SH-1 synthesis MPEG1 MPEG4 Audio ADPCM H.263 Image V42.bis Fig. 6— Development of Middleware Digital signature Character Three-dimensional Products. recognition graphics Cipher Electronic A variety of middleware has been JBIG watermarks provided for use with the SuperH MH/MR/MMR JPEG RISC engine series and eases the development of appliances.

An Architecture for Multimedia and Its modem, voice synthesizer, voice/image CODEC, etc., Applications at high speed. In various multimedia applications, it Hitachi has developed the SH3-DSP that is suitable achieves a performance better than two or three times for application in networks and multimedia. In today’s that of an SH-3 running at the same frequency. Internet society, multimedia products require RISC Applications include pocket personal computers, microcomputers to control both the human-machine modems and digital still cameras. interface and the system, and DSPs to process image and voice signals. The SH3-DSP was developed by MIDDLEWARE integrating the RISC and DSP in the CPU core, Hitachi has developed the following middleware realizing strong performance and low power for applications in the network and multimedia fields. consumption (see Fig. 5). This CPU has a built-in cache These modules are mainly intended for the SuperH memory and MMU and supports Windows CE* and RISC engine series (see Fig. 6), and enable the easy many other operating systems. It also has a processing construction of customer systems. function that is equivalent to a general-purpose DSP (1) Image middleware such as JPEG (joint and executes middleware for operation as a software photographic expert group) for encoding and decoding still images used for digital cameras and MPEG4 (moving picture expert group 4) for encoding and *Windows is a registered trademark of Microsoft Corp. in the U.S.A. and other countries. decoding motion pictures. CPU Technologies for Networks and Multimedia 44

TABLE 1. Programming Results for the Voice CODEC ABOUT THE AUTHORS The architecture of the SH2-DSP/SH3-DSP with its RISC and DSP realizes an efficient voice CODEC. Kunio Uchiyama Joined Hitachi, Ltd. in 1978, and now works at the Method G.711 G.726 G.729A System LSI Research Department, Central Research Program size 1 kbyte 2 kbytes 26 kbytes Laboratory. He is currently engaged in the research and development of microprocessors. Mr. Uchiyama Required data memory 256 bytes 1 kbyte 7 kbytes can be reached by e-mail at Required frequency (MHz) [email protected]. Encoding 0.1 12 22 Decoding 0.1 12 5 Hirofumi Mukai Joined Hitachi, Ltd. in 1984, and now works at the Business Unit 9, Semiconductor & Integrated Circuits. He is currently engaged in the development of the H8/H8S series. Mr. Mukai can be reached by (2) Audio middleware such as AAC (advance audio e-mail at [email protected]. coding), Dolby-AC3 (audio code number 3) and MP3 (MPEG1 audio layer 3) used for solid audio. Ikuya Kawasaki (3) Voice-related middleware for voice recognition and Joined Hitachi, Ltd. in 1982, and now works at the Mobile LSI Processor 1st Design Department, Mobile synthesis for car navigation systems, and for voice LSI Business Unit, Semiconductor & Integrated encoding and decoding for use in Internet telephony. Circuits. He is currently engaged in the development (4) Data communications middleware such as 56-kbps of the SuperH RISC engine series. Mr. Kawasaki can modem module. be reached by e-mail at A practical example of using a voice CODEC with [email protected]. the SuperH RISC engine is described below. With the Tsuguji Tachiuchi advent of the Internet, data is easily transmitted Joined Hitachi, Ltd. in 1974, and now works at the worldwide and there are great expectations for the Middleware Development, Software Technology transmission of voice signals via a voice CODEC Division, Software & Hardware Technologies, Semiconductor & Integrated Circuits. He is currently called the VoIP (voice-over-Internet protocol). Table engaged in the development of voice CODEC and 1 shows the results of programming according to three image-handling middleware. Mr. Tachiuchi can be voice CODEC methods (G.711, G.726 and G.729A) reached by e-mail at developed for the SH2-DSP and SH3-DSP. Both [email protected]. architectures, with their combination of RISC and DSP, enable G.729A transmission of high-quality voice signals at a high compression ratio with processing of the data at a rate below 30 MHz per channel.

CONCLUSIONS We have outlined Hitachi’s CPU technologies for network and multimedia applications. In this field, appliances must meet a variety of requirements. These include high levels of performance in handling multimedia data and in network control, and low power consumption. Appliances must fulfill these requirements at a low price. Hitachi intends to further develop all of its microcomputer product ranges, from the H8/H8S series to the SuperH RISC engine series, and provides flexible ways of satisfying the above needs and meeting the requirements of customers.