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Superh (SH) 64-Bit RISC Series SH-5 CPU Core, Volume 1: Architecture

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Superh (SH) 64-Bit RISC Series SH-5 CPU Core, Volume 1: Architecture SuperHTM (SH) 64-Bit RISC Series SH-5 CPU Core, Volume 1: Architecture Last updated 22 February 2002 SuperH, Inc. 05-CC-10001 V1.0 SH-5 CPU Core, Volume 1: Architecture ii This publication contains proprietary information of SuperH, Inc., and is not to be copied in whole or part. Issued by the SuperH Documentation Group on behalf of SuperH, Inc. Information furnished is believed to be accurate and reliable. However, SuperH, Inc. assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SuperH, Inc. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SuperH, Inc. products are not authorized for use as critical components in life support devices or systems without the express written approval of SuperH, Inc. is a registered trademark of SuperH, Inc. SuperH is a registered trademark for products originally developed by Hitachi, Ltd. and is owned by Hitachi Ltd. © 2001 SuperH, Inc. All Rights Reserved. SuperH, Inc. San Jose, U.S.A. - Bristol, United Kingdom - Tokyo, Japan www.superh.com SuperH, Inc. SH-5 CPU Core, Volume 1: Architecture 05-CC-10001 V1.0 Contents Preface xv SuperH SH-5 document identification and control xv SuperH SH-5 CPU core documentation suite xvi 1Overview 1 1.1 Introduction 1 1.2 Instruction set architecture 2 1.2.1 SHmedia 2 1.2.2 SHcompact 5 1.2.3 Mode switch 6 1.3 CPU control and configuration 7 1.4 SH compatibility model 8 1.4.1 User-mode compatibility 8 1.4.2 Limits of compatibility 10 2 Architectural state 13 2.1 Overview 13 2.2 User and privileged operation 13 2.3 Effective addresses 13 2.4 Notation 14 SuperH, Inc. 05-CC-10001 V1.0 SH-5 CPU Core, Volume 1: Architecture iv 2.5 User state 14 2.5.1 Mode: MD 15 2.5.2 Instruction set architecture: ISA 15 2.5.3 Program counter: PC 16 2.5.4 General-purpose registers: R 16 2.5.5 Target registers: TR 16 2.5.6 User-accessible control registers: CR 16 2.5.7 Memory: MEM 17 2.5.8 Floating-point status and control register: FPSCR 17 2.5.9 Floating-point registers: FR, DR, FP, FV, MTRX 17 2.6 Privileged state 22 2.6.1 Privileged control registers: CR 23 2.6.2 Configuration registers: CFG 23 2.7 The status register 24 2.8 Register subsets 25 2.9 SHcompact state 26 2.9.1 SHcompact non-floating-point register state 26 2.9.2 SHcompact floating-point register state 27 2.9.3 SHcompact memory 29 3 Data representation 31 3.1 Introduction 31 3.2 Bit conventions 31 3.3 Data types 32 3.4 IEEE754 floating-point numbers 33 3.4.1 Values 33 3.4.2 Single-precision format 34 3.4.3 Double-precision format 35 3.5 Data formats for general-purpose registers 37 3.6 Data formats for floating-point registers 41 3.7 Data representation in memory 43 SuperH, Inc. SH-5 CPU Core, Volume 1: Architecture 05-CC-10001 V1.0 v 3.8 Effective address representation 49 3.9 Program counter overflow 51 3.10 Pointer representation 51 3.11 Other register representations 52 3.11.1 Register naming 53 3.11.2 Register conventions 53 3.11.3 Field conventions 54 4 SHmedia instructions 57 4.1 Overview 57 4.2 Instruction naming conventions 58 4.2.1 Type modifiers 58 4.2.2 Hint modifiers 60 4.3 Format conventions 60 4.3.1 Format bit-fields 60 4.3.2 Major and minor formats 62 4.3.3 Format names 63 4.4 Major formats 64 4.5 Reserved bits 65 4.6 Assembly notation 67 5 SHmedia integer instructions 69 5.1 Overview 69 5.1.1 Control flow 69 5.1.2 64-bit integer operations 70 5.1.3 32-bit integer operations 70 5.1.4 Other integer operations 71 5.2 Constant loading instructions 71 5.3 Control flow instructions 72 SuperH, Inc. 05-CC-10001 V1.0 SH-5 CPU Core, Volume 1: Architecture vi 5.3.1 Prepare-target instructions 73 5.3.2 The unconditional branch instruction 75 5.3.3 Conditional branch instructions 76 5.3.4 The GETTR instruction 79 5.4 Arithmetic instructions 80 5.5 Comparison instructions 83 5.6 Bitwise instructions 84 5.7 Shift instructions 86 5.8 Miscellaneous instructions 88 5.9 General-purpose register move 90 6 SHmedia memory instructions 91 6.1 Overview 91 6.2 Aligned load and store instructions 92 6.3 Misaligned access support 94 6.4 Memory properties 97 6.5 Synchronization 98 6.5.1 Atomic swap 98 6.5.2 Instruction synchronization 99 6.5.3 Data synchronization 99 6.5.4 Implementation aspects 100 6.6 Cache instructions 101 6.6.1 Prefetch 102 6.6.2 Allocate 103 6.6.3 Cache coherency 104 6.7 Example code sequences 107 6.7.1 Synchronizing fetch with data writes 107 7 SHmedia multimedia instructions 109 SuperH, Inc. SH-5 CPU Core, Volume 1: Architecture 05-CC-10001 V1.0 vii 7.1 Overview 109 7.2 Multimedia formats 110 7.2.1 Mathematics 112 7.2.2 Rounding 112 7.2.3 MOSTPOS and MOSTNEG 113 7.3 Multimedia conversions 114 7.4 Multimedia addition and subtraction 115 7.5 Multimedia absolute value 117 7.6 Multimedia sum of absolute differences 118 7.7 Multimedia left shifts 119 7.8 Multimedia arithmetic right shifts 120 7.9 Scalar arithmetic right shift with saturation 121 7.10 Multimedia logical right shifts 122 7.11 Multimedia comparisons 123 7.12 Multimedia full-width multiplies 124 7.13 Multimedia multiplies 125 7.14 Multimedia multiply with rounding 126 7.15 Multimedia multiply and sum 127 7.16 Multimedia fractional multiply accumulate 128 7.17 Multimedia fractional multiply subtract 129 7.18 Multimedia shuffles 130 7.19 Multimedia bitwise conditional move 131 7.20 Multimedia permute 132 7.21 Multimedia extract 133 8 SHmedia floating-point 135 8.1 Introduction 135 8.2 Floating-point disable 135 8.3 IEEE754 floating-point support 136 SuperH, Inc. 05-CC-10001 V1.0 SH-5 CPU Core, Volume 1: Architecture viii 8.3.1 Formats 136 8.3.2 Rounding 136 8.3.3 Hardware operations 137 8.3.4 Software operations 138 8.3.5 Zeroes, infinities, NaNs and sign 138 8.3.6 Exceptional conditions 139 8.3.7 Denormalized numbers 142 8.3.8 Exception launch 143 8.3.9 Recommended functions and predicates 144 8.3.10 Future FPU architecture 144 8.4 Non-IEEE754 floating-point support 145 8.4.1 Treat denormalized numbers as zero 145 8.4.2 Fused multiply accumulate support 145 8.4.3 Special-purpose instructions 146 8.5 Floating-point status and control register 147 8.6 General-purpose floating-point instructions 148 8.6.1 Floating-point status and control 148 8.6.2 Floating-point dyadic arithmetic 149 8.6.3 Floating-point monadic arithmetic 149 8.6.4 Floating-point multiply-accumulate 150 8.6.5 Floating-point conversions 150 8.6.6 Floating-point comparisons 151 8.6.7 Floating-point moves 153 8.7 Special-purpose floating-point instructions 154 8.7.1 Mathematical properties 154 8.7.2 FIPR.S and FTRV.S calculation 155 8.7.3 FIPR.S and FTRV.S accuracy specification 156 8.7.4 FCOSA.S, FSINA.S and FSRRA.S 158 8.8 Floating-point memory instructions 159 8.8.1 Displacement addressing 160 8.8.2 Indexed addressing 161 SuperH, Inc. SH-5 CPU Core, Volume 1: Architecture 05-CC-10001 V1.0 ix 9 SHmedia system instructions 163 9.1 Overview 163 9.2 Event handling instructions 163 9.3 Control registers 164 9.3.1 Control register set 164 9.3.2 Control register instructions 165 9.4 Configuration registers 166 9.4.1 Configuration register space 166 9.4.2 Configuration register instructions 166 10 SHcompact instructions 169 10.1 Overview 169 10.2 Formats 170 11 SHcompact integer instructions 171 11.1 Overview 171 11.2 Control flow instructions 172 11.3 Arithmetic instructions 174 11.4 Comparison instructions 175 11.5 No-operation 175 11.6 Bitwise instructions 176 11.7 Rotate and shift instructions 177 11.8 Miscellaneous instructions 178 11.9 Special instructions 179 12 SHcompact memory instructions 181 12.1 Load/store instructions 182 12.2 Test and set instruction 185 SuperH, Inc. 05-CC-10001 V1.0 SH-5 CPU Core, Volume 1: Architecture x 12.3 Synchronization 186 12.4 Cache instructions 186 13 SHcompact floating-point 189 13.1 Overview 189 13.2 Floating-point disable 189 13.3 Floating-point register set 190 13.4 FPSCR 190 13.5 FPUL 191 13.6 Floating-point instructions 192 13.6.1 Floating-point special register access 192 13.6.2 Floating-point constant loading 192 13.6.3 Floating-point dyadic arithmetic 193 13.6.4 Floating-point monadic arithmetic 193 13.6.5 Floating-point multiply and accumulate 194 13.6.6 Floating-point comparisons 194 13.6.7 Floating-point conversions 195 13.6.8 Special-purpose floating-point instructions 195 13.6.9 Floating-point width and bank change 197 13.6.10 Floating-point move instructions 197 13.6.11 Floating-point load/store instructions 198 13.7 Reserved floating-point behavior 200 14 SHcompact system instructions 205 14.1 System instructions 205 15 Control registers 207 15.1 Control register set 207 15.2 Control register descriptions 209 15.2.1 SR 210 SuperH, Inc.
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