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Powerpc User Instruction Set Architecture Book I Version 2.02 Version 2.02 PowerPC User Instruction Set Architecture Book I Version 2.02 January 28, 2005 Manager: Joe Wetzel/Poughkeepsie/IBM Technical Content: Ed Silha/Austin/IBM Cathy May/Watson/IBM Brad Frey/Austin/IBM Junichi Furukawa/Austin/IBM Giles Frazier/Austin/IBM i Version 2.02 The following paragraph does not apply to the United Kingdom or any country or state where such provisions are inconsistent with local law. The specifications in this manual are subject to change without notice. This manual is provided “AS IS”. Inter- national Business Machines Corp. makes no warranty of any kind, either expressed or implied, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. International Business Machines Corp. does not war- rant that the contents of this publication or the accom- panying source code examples, whether individually or as one or more groups, will meet your requirements or that the publication or the accompanying source code examples are error-free. This publication could include technical inaccuracies or typographical errors. Changes are periodically made to the information herein; these changes will be incorpo- rated in new editions of the publication. Address comments to IBM Corporation, Internal Zip 9630, 11400 Burnett Road, Austin, Texas 78758-3493. IBM may use or distribute whatever information you supply in any way it believes appropriate without incur- ring any obligation to you. The following terms are trademarks of the International Business Machines Corporation in the United States and/or other countries: IBM PowerPC RISC/System 6000 POWER POWER2 POWER4 POWER4+ IBM System/370 Notice to U.S. Government Users—Documentation Related to Restricted Rights—Use, duplication or dis- closure is subject to restrictions set fourth in GSA ADP Schedule Contract with IBM Corporation. © Copyright International Business Machines Corpora- tion, 1994, 2003. All rights reserved. ii PowerPC User Instruction Set Architecture Version 2.02 Preface This document defines the PowerPC User Instruction Set Architecture. It covers the base instruction set and related facilities available to the application program- mer. Other related documents define the PowerPC Virtual Environment Architecture, the PowerPC Operating Environment Architecture, and PowerPC Implementa- tion Features. Book II, PowerPC Virtual Environment Architecture defines the storage model and related instructions and facilities available to the application programmer, and the time-keeping facilities available to the application programmer. Book III, PowerPC Oper- ating Environment Architecture defines the system (privileged) instructions and related facilities. Book IV, PowerPC Implementation Features defines the imple- mentation-dependent aspects of a particular implemen- tation. As used in this document, the term “PowerPC Architec- ture” refers to the instructions and facilities described in Books I, II, and III. The description of the instantiation of the PowerPC Architecture in a given implementation includes also the material in Book IV for that implemen- tation. Note: Change bars indicate changes from Version 2.01. Preface iii Version 2.02 iv PowerPC User Instruction Set Architecture Version 2.02 Table of Contents Chapter 1. Introduction . 1 2.3.1 Condition Register . 18 1.1 Overview. 1 2.3.2 Link Register . 19 1.2 Computation modes . 1 2.3.3 Count Register . 19 1.3 Instruction Mnemonics and Operands1 2.4 Branch Processor Instructions . 20 1.4 Compatibility with the POWER Archi- 2.4.1 Branch Instructions . 20 tecture . 2 2.4.2 System Call Instruction . 26 1.5 Document Conventions . 2 2.4.3 Condition Register Logical Instruc- 1.5.1 Definitions and Notation. 2 tions . 27 1.5.2 Reserved Fields and Reserved Val- 2.4.4 Condition Register Field ues . 3 Instruction . 30 1.5.3 Description of Instruction Operation 4 1.6 Processor Overview . 6 Chapter 3. Fixed-Point Processor . 31 1.7 Instruction formats . 7 3.1 Fixed-Point Processor Overview. 31 1.7.1 I-Form . 8 3.2 Fixed-Point Processor 1.7.2 B-Form. 8 Registers . 31 1.7.3 SC-Form . 8 3.2.1 General Purpose Registers . 31 1.7.4 D-Form . 8 3.2.2 Fixed-Point Exception Register . 32 1.7.5 DS-FORM . 8 3.3 Fixed-Point Processor Instructions . 33 1.7.6 X-FORM . 9 3.3.1 Fixed-Point Storage Access Instruc- 1.7.7 XL-FORM . 9 tions . 33 1.7.8 XFX-FORM . 9 3.3.1.1 Storage Access Exceptions. 33 1.7.9 XFL-FORM . 9 3.3.2 Fixed-Point Load Instructions. 33 1.7.10 XS-FORM . 9 3.3.3 Fixed-Point Store Instructions . 40 1.7.11 XO-FORM . 9 3.3.4 Fixed-Point Load and Store with Byte 1.7.12 A-FORM . 10 Reversal Instructions . 44 1.7.13 M-FORM . 10 3.3.5 Fixed-Point Load and Store Multiple 1.7.14 MD-FORM . 10 Instructions . 46 1.7.15 MDS-FORM. 10 3.3.6 Fixed-Point Move Assist Instruc- 1.7.16 Instruction Fields . 10 tions . 47 1.8 Classes of Instructions . 12 3.3.7 Other Fixed-Point Instructions . 50 1.8.1 Defined Instruction Class. 12 3.3.8 Fixed-Point Arithmetic Instructions51 1.8.2 Illegal Instruction Class . 12 3.3.9 Fixed-Point Compare Instructions 60 1.8.3 Reserved Instruction Class . 12 3.3.10 Fixed-Point Trap Instructions . 62 1.9 Forms of Defined Instructions. 13 3.3.11 Fixed-Point Logical Instructions . 65 1.9.1 Preferred Instruction Forms. 13 3.3.12 Fixed-Point Rotate and Shift 1.9.2 Invalid Instruction Forms . 13 Instructions . 71 1.10 Optionality. 14 3.3.12.1 Fixed-Point Rotate Instructions 71 1.11 Exceptions . 14 3.3.12.2 Fixed-Point Shift Instructions . 77 1.12 Storage Addressing . 14 3.3.13 Move To/From System Register 1.12.1 Storage Operands . 14 Instructions . 81 1.12.2 Effective Address Calculation . 15 Chapter 4. Floating-Point Processor. Chapter 2. Branch Processor . 17 85 2.1 Branch Processor Overview . 17 4.1 Floating-Point Processor Overview. 85 2.2 Instruction Execution Order . 17 4.2 Floating-Point Processor Registers. 86 2.3 Branch Processor Registers. 18 Table of Contents v Version 2.02 4.2.1 Floating-Point Registers . .86 Chapter 5. Optional Facilities and 4.2.2 Floating-Point Status and Control Instructions . 123 Register . .87 5.1 Fixed-Point Processor Instructions 124 4.3 Floating-Point Data . .89 5.1.1 Move To/From System Register 4.3.1 Data Format . .89 Instructions . 124 4.3.2 Value Representation . .90 5.2 Floating-Point Processor Instructions. 4.3.3 Sign of Result . .91 124 4.3.4 Normalization and 5.2.1 Floating-Point Arithmetic Instructions Denormalization . .92 125 4.3.5 Data Handling and Precision. .92 5.2.1.1 Floating-Point Elementary Arith- 4.3.5.1 Single-Precision Operands . .92 metic Instructions . 125 4.3.5.2 Integer-Valued Operands . .93 5.2.2 Floating-Point Select Instruction 126 4.3.6 Rounding. .93 5.3 Little-Endian . 127 4.4 Floating-Point Exceptions . .94 5.3.1 Byte Ordering . 127 4.4.1 Invalid Operation Exception . .96 5.3.2 Structure Mapping Examples. 127 4.4.1.1 Definition . .96 5.3.2.1 Big-Endian Mapping . 127 4.4.1.2 Action . .97 5.3.2.2 Little-Endian Mapping. 128 4.4.2 Zero Divide Exception. .97 5.3.3 PowerPC Byte Ordering . 128 4.4.2.1 Definition . .97 5.3.3.1 Controlling PowerPC Byte Order- 4.4.2.2 Action . .97 ing . 128 4.4.3 Overflow Exception . .98 5.3.3.2 PowerPC Little-Endian Byte Order- 4.4.3.1 Definition . .98 ing . 128 4.4.3.2 Action . .98 5.3.4 PowerPC Data Addressing in Little- 4.4.4 Underflow Exception . .98 Endian Mode. 130 4.4.4.1 Definition . .98 5.3.4.1 Individual Aligned Scalars . 130 4.4.4.2 Action . .98 5.3.4.2 Other Scalars . 130 4.4.5 Inexact Exception . .99 5.3.4.3 Page Table . 131 4.4.5.1 Definition . .99 5.3.5 PowerPC Instruction Addressing in 4.4.5.2 Action . .99 Little-Endian Mode . 131 4.5 Floating-Point Execution Models . .100 5.3.6 PowerPC Cache 4.5.1 Execution Model for IEEE Opera- Management Instructions in tions . .100 Little-Endian Mode . 133 4.5.2 Execution Model for 5.3.7 PowerPC I/O in Multiply-Add Type Instructions . .101 Little-Endian Mode . 133 4.6 Floating-Point Processor Instructions . 5.3.8 Origin of Endian. 133 103 4.6.1 Floating-Point Storage Access Instructions . .103 Chapter 6. Optional Facilities and 4.6.1.1 Storage Access Exceptions . .103 Instructions that are being Phased 4.6.2 Floating-Point Load Instructions .103 Out . 135 4.6.3 Floating-Point Store Instructions .106 6.1 Move To Condition Register from 4.6.4 Floating-Point Move Instructions. 110 XER. 135 4.6.5 Floating-Point Arithmetic Instructions 111 Appendix A. Suggested Floating- 4.6.5.1 Floating-Point Elementary Arith- metic Instructions . 111 Point Models . 137 4.6.5.2 Floating-Point Multiply-Add Instruc- A.1 Floating-Point Round to Single-Preci- tions . 113 sion Model. 137 4.6.6 Floating-Point Rounding and Con- A.2 Floating-Point Convert to Integer version Instructions. 115 Model . 142 4.6.7 Floating-Point Compare Instructions. A.3 Floating-Point Convert from Integer 119 Model . 145 4.6.8 Floating-Point Status and Control Register Instructions. .120 Appendix B. Assembler Extended Mnemonics . 151 B.1 Symbols . 151 vi PowerPC User Instruction Set Architecture Version 2.02 B.2 Branch Mnemonics .
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