POWER8: The first OpenPOWER processor

Dr. Michael Gschwind Senior Technical Staff Member & Senior Manager IBM Power Systems

#OpenPOWERSummit

Join the conversation at #OpenPOWERSummit 1 OpenPOWER is about choice in large-scale data centers

The choice to The choice to The choice to differentiate innovate grow

. build workload • collaborative • delivered system optimized innovation in open performance solutions ecosystem • new capabilities . use best-of- • with open instead of breed interfaces technology scaling components from an open ecosystem

Join the conversation at #OpenPOWERSummit Why Power and Why Now?

. Power is optimized for server workloads

. Power8 was optimized to simplify application porting

. Power8 includes CAPI, the Coherent Accelerator Processor Interconnect • Building on a long history of IBM workload acceleration

Join the conversation at #OpenPOWERSummit POWER8 Processor

Cores • 12 cores (SMT8)  96 threads per chip • 2X internal data flows/queues • 64K data cache, 32K instruction cache Caches • 512 KB SRAM L2 / core • 96 MB eDRAM shared L3 • Up to 128 MB eDRAM L4 (off-chip) Accelerators • Crypto & memory expansion • • VMM assist • Data Move / VM Mobility • Coherent Accelerator Processor Interface (CAPI)

Join the conversation at #OpenPOWERSummit 4 POWER8 Core

•Up to eight hardware threads per core (SMT8) •8 dispatch •10 issue •16 execution pipes: •2 FXU, 2 LSU, 2 LU, 4 FPU, 2 VMX, 1 Crypto, 1 DFU, 1 CR, 1 BR •Larger Issue queues (4 x 16-entry) •Larger global completion, Load/Store reorder queue •Improved branch prediction •Improved unaligned storage access •Improved data prefetch

Join the conversation at #OpenPOWERSummit 5 POWER8 Architecture

. High-performance LE support – Foundation for a new ecosystem . Organic application growth Power evolution – Instruction Fusion 1600 PowerPC . Workload optimized 1400 Power ISA – Power SIMD Extensions 1200 – Coherent Accelerator Processor Interface 1000 . Parallel programming productivity 800 – Transactional Memory 600 . Cloud ready instructions – Cloud Mode 400 – Reduced context switch overhead 200 – Improved Interrupt performance 0 . Dynamic System Optimization May-90 Oct-95 Apr-01 Oct-06 Apr-12 Sep-17 – Performance Monitoring – Dynamic Code Optimization

Join the conversation at #OpenPOWERSummit 6

Source: Hot Chips 26

Join the conversation at #OpenPOWERSummit Workload-optimized acceleration with coherent accelerators

. Attached accelerators • Accelerate workloads with functions that are not a good fit for traditional general purpose CPU

. Coherent integration in system architecture • Data sharing • Programming • Performance

Join the conversation at #OpenPOWERSummit Workload-optimized acceleration

. On-chip integrated accelerators (SoC design) • Compute accelerator ( BE) • Compression (P7+) • Encryption (P7+) • Random number generation (P7+) Cell BE • …

. SoC design offers highest integration, but… • New chip design to introduce new accelerator • Long time to market • Requires very high volumes POWER7+

Join the conversation at #OpenPOWERSummit CAPI: Coherent Accelerator Processor Interface

. Integrate accelerators into system architecture with standardized, coherent protocol • CAPI functional protocol Coherence Bus • PCIe signaling protocol CAPP . Modular interface enables third parties to provide high value-add components POWER8

. Create workload-optimized innovative solutions • Faster time to market PSL • Lower bar to entry • Variety of implementation options . FPGAs, ASICs

Join the conversation at #OpenPOWERSummit CAPI accelerator programming Virtual Addressing • Accelerator can work with same virtual memory addresses that the processors use • CAPI shares page tables and provides address translation Coherence Bus • Pointers de-referenced same as the host CAPP application • Peer-to-peer programming between CPU and accelerator with Hardware Managed Coherence in-memory data sharing • No need for memory pinning • Data fetched by accelerator based on accelerator application flow PSL • Accelerator participates in locks • Low latency communication

Join the conversation at #OpenPOWERSummit POWER8: expanding choice for data formats

. Big-Endian: Most Significant First 0 1 2 3 • Traditional enterprise server data format • The standard internet data format (“network byte order”) • Process five decades of database content • Protect investment into data storage and curation

. Little-Endian: Least Significant Byte First 3 2 1 0 • Traditional small system format (PC, mobile) • High-volume hardware components often little-endian • Participate in rich standard ecosystem • Simplify application portability for those seeking to upgrade to Power

Join the conversation at #OpenPOWERSummit

Summary

. POWER8 introduce traditional microarchitecture improvements • More Instruction level parallelism • More Data level parallelism • Larger caches and queues  Best-in-class systems performance for scale-out and scale-up

. New foundational capabilities for OpenPOWER • High-performance little- and big-endian . Improved integration of industry standard ecosystem hardware . Improved application portability to OpenPOWER • CAPI enables system architects to extend processor capabilities . Create a broad range of workload optimized offerings

Join the conversation at #OpenPOWERSummit Implementation / HPC / Research

Software

System / Integration

I/O / Storage / Acceleration

Boards / Systems

Chip / SOC

Join the conversation at #OpenPOWERSummit 14 © 2015 OpenPOWER Foundation

Special Notices

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© 2015 International Business Machines Corporation Michael Gschwind, The Little-Endian OpenPOWER Software Development Environment Special Notices (cont.)

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© 2015 International Business Machines Corporation Michael Gschwind, The Little-Endian OpenPOWER Software Development Environment Thank you! OpenPOWER: Progress by the Numbers 80

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© 2015 International Business Machines Corporation Michael Gschwind, The Little-Endian OpenPOWER Software Development Environment