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NVAX-Microprocessor VAX Systems NVAX-microprocessor VAX Systems Digital Technical Journal Digital Equipment Corporation Volume 4 Number 3 Summer 1992 Editorial Jane C. Blake, Editor Kathleen M. Stetson, Associate Editor Helen L. Patterson, Associate Editor Circulation Catherine M. Phillips, Administrator Sherry L. Gonzalez Production Terri Autieri, Production Editor Anne S. Katzeff, Typographer Peter R. Woodbury, Illustrator Advisory Board Samuel H. Fuller, Chairman Rid1ard W Beane Richard./. Hollingsworth Alan G. Nemeth Victor A. Vyssotsky Gayn B. Winters The Digital Technical journal is published quarterly by Digital Equipment Corporation, 146 Main Street MLO l-3/B68, Maynard, Massachusetts 01754-2571. Subscriptions to the journalare $40.00 for four issues and must be prepaid i11 U.S. funds. University and college professors and Ph.D. students in the electrical engineering and computer science fields receive complimentary subscriptions upon request. Orders, inquiries, and address changes should be sent to the Digital Technical}ournal at the published-by address. Inquiries can also be sent electronically to 01]@CRL.DEC. COM. Single copies and back issues are available for $16.00 each from Digital Press of Digital Equipment Corporation, 1 Burli11gton Woods Drive, Burlington, MA 01830-4597. Digital employees may send subscription orders on the ENET to RDVAX::JOURNAL or by interoffice mail to mailstop ML01-3/B68. Orders should include badge number, site location code, and address. All employees must advise of changes of address. Comments on the content of any paper are welcomed and may be sent to the editor at the published-by or network address. Copyright© 1992 Digital Equipment Corporation. Copying without fee is permitted provided that such copies are made for use in educational illstitutions by faculty members and are not distributed for commercial advantage. Abstracti11g with credit of Digital Equipment Corporation's authorship is permitted. All rights reserved. The information ill thejounwl is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in the journal. ISSN 0898-901X Documentation Number EY-j884E-DP The followillg are trademarks of Digital Equipment Corporation: Alpha AXP, DEC, DECchip 21064, DECstation, DECwindows, Digital, the Digital logo, KA50, KA52, KA675, KA680, KA690, MicroVAX, MS44, MS670, MS690, Q- bus, Q22-bus, ThillWire, TURBOchannel, ULTRIX, VAX, VAX-11/780, VAX 4000, VAX 6000, VAX 7000, VAX 10000, VAXcluster, VAX MACRO, VAXstation, VMS, and VXT 2000. MACH is a trademark and PAL is a registered trademark of Cover Design Advanced Mkro Devices, Inc. The NVAX microprocessor is Digital's fastest VAXimplementation SPEC, SPECfp, SPECint, and SPECmark are registered trademarks of and the common theme of papers in this issue. Our cover graphic the Standard Performance Evaluation Cooperative. joins the NVAX project code name with an image of speed - the SPICE is a trademark of the University of California at Berkeley. chip's most salient characteristic and the performanceadvantage TPC Benchmark and tpsA-Iocal are trademarks of the Transaction it brings to a range of new VAX systems. Processing Performance Council. The cover design is byDeb Anderson of Quantic Communications, inc. Book production was clone by Quantic Communications, Inc. I Contents 9 Foreword Robert M. Supnik NVAX-microprocessor VAX Systems II The NVAXand NVAX+ High-performance VAX Microprocessors G. Michael Uhler, Debra Bernstein, Larry L. Biro, john F Brown III,jolu1 H. Edmondson,jeffrey D. Pickholtz, and Rebecca L. Stamm 24 The NVAX CPU Chip: Design Challenges, Methods, and CAD Tools Dale R. Donchin, Timothy C. Fischer, Thomas F Fox, Victor Peng. Ronald P Preston, and William R. Wheeler 38 Logical Verification of the NVAX CPU Chip Design Wa lker Anderson 47 The VAX6000 Model 600 Processor Lawrence Chisvin, Gregg A. Bouchard, and Thomas M. We nners 60 Design of the VAX 4000Model 400, 500, and 600 Systems Jonathan C. Crowell, Kwong-Tak A. Chui, Thomas E. Kopec, Samyojita A. Naclkarni, and Dean A. Sovie 75 The Design of the VAX 4000Model lOOand MicroVAX 3100 Model90 Desktop Systems Jonathan C. Crowell and David W Maruska 82 The VAXstation 4000Model90 Michael A. Callander, Sr., Lauren M. Carlson, Andrew R. Ladd, and Mitchell 0. Norcross 92 VAX 6000 Error Handling: A Pragmatic Approach Brian Porter I Editor's Introduction paper on the new mid-range VAX 6000 multipro­ cessing system, Larry Chisvin, Gregg Bouchard, and To m Wenners explain the moc.lule design decisions that supported the goals of oOOO -series compatibil­ ity ami time to market. Of particular interest are the schedule and performance benefits derivec.l from developing a routing ami control interface ch ip. The engineers for new low-end c.leskside systems also chose to develop custom chips-a memory controller chip, memory moc.lule, and an 1/0 con­ troller. Jon Crowell, Kwong Ch ui, Tom Kopec, Sam Nadkarni, and Dean Sovie c.liscuss the chip func­ Jane Blake C. tions that were key to exceeding the performance Editor goal of three times that of the previous VAX 4000. For the low-end VAX 4000 Model 100 system and The microprocessor is a high-performance, NVt'v'< the Micro VAX 3100 desktop servers, designers sa\'ed single-chip implementation of the VAX architecture. significant time by "borrowing" existing compo­ It is toc.lay's fastest VA X microprocessor anc.l the CPU nents from proven systems. Jon Crowell and Dave at the heart of the mic.l-range, low-end, and work­ Maruska relate decisions that allowed them to c.lou­ station systems described in this issue of the Digital ble performance and complete the work within the Te ch nical.fournal. extraordinarily short time of nine months. The NVt'v'Cchip is not only fast, with cycle times as The newest VAXstation workstation, based on low as 11 ns, but also holds a unique position in the l\fVAX, is the Moclel 90. Mike Callander, Lauren Digital family of microprocessors: NVA X is both an Carlson, Andy Ladd, anc.l Mitch Norcross present upgrade path for existing VAX systems and a migra­ their design methodology. Most significant for tion path to Alpha A.XP systems. In their paper on development was the decision to implement new the NVAX and NVA.X+ chips, Mike Uhler, Debra logic in programmable technology, which allowed Bernstein, Larry Biro, John Brown, John Edmonc.l­ bug fixes in minutes rather than weeks. son, Jeff Pickholtz, and Rebecca Stamm present an Not about system design but rather error han­ overview of the comp.lex microprocessor designs dling in 6000 systems, Brian Porter's paper and relate how RJSC techniques are used in this CISC describes an approach that reduces the amount of machine to achieve dramatic increases in perfor­ unique coding traclitional.ly required for error han­ mance over previous implementations. dling. He c.letails the development of sophisticated Increases in performance are also attributable to error hand I ing routines that accommodate the the CMOS-4 0.75-micrometer process technology in complexity of the symmetric multiprocessing VAX which the NVAX is implemented. In their paper 6000 moc.lels. about the verification of the physical design, Dale The ec.litors thank Mike Uhler of the Semi­ Donchin, Tim Fischer. Frank Fox, Victor Peng, Ro n conductor Engi neering Group, who ensured that Preston, and Bi 11 Wheeler c.lescrihe the methods and the standards of excellence applied to NVAX devel­ the CAD tools created to manage the complexity of opment were appl iec.l to the development of this a chip with 13 million transistors. issue. Also, this issue is notable editorially because The rigorous use of the CAD t.oo.lsancl thorough it is the first in which papers have been formally simulation-based testing resulted in highly hlllc­ refereed. I thank Gene Hoffnagle, editor of the tional first-pass chips. In his paper about the logical JB,H Systetns .Tournai, for encouraging the use of verification, Walker Anderson discusses the suc­ the referee process in any journal worthy of the cessful strategies used to ensure no "show stopper" name. D1J issues will continue to be refereed so bugs existec.l in the design. Highl ighting major that we may offer engineering and academic read­ strategies, he reviews the behavioral models anc.l ers informative and relevant technical discussions. pseudorandom exercisers at the core of the verifi­ cation effort. Each system design team chose a different approach to take advantage of NVAXperf ormance and to meet system-specific requirements. In a 2 Biographies I Walker Anderson Principal engineer Wa lker Anderson is a member of the Models, To ols, and Ve rification Group in the Semiconductor Engineering Group. Currently a co-leader of the logical verification team fo r a future chip design, he Jed the NVAX logicalverifi cation effort. Before joining Digital in 198H, Wa lker was a diagnostic and testability engineer in a CPU development group at Data General Corporation fo r eight years. He holds a B.S.E.E. (1980) fro m Cornell University and an M.B.A (1985) from Boston University. Debra Bernstein Debra Bernstein is a consultant engineer in the Semi­ conductor Engineering Group. She worked on the CP design and architecture fo r the NVA)( microprocessor and the VAX 8700/8800 systems and is currently co-architecture leader for a future Alpha t\.-'\P processor. Deb received a B.S. in computer science (1982, cum laude) from the University of Massachusetts in Amherst. She holds one patent, has two patent applications pending, and has coautbored several technical papers. Larry L. Biro Larry Biro joined the Electronic Storage Development (ESD) Group in 1983, after receiving an M.S.E.E. from Rensselaer Polytechnic Institute. While in ESD, he contributed to the advanced development of solid-state disk products.
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