ReX:ReX: AA dNTSCdNTSC™™ ReceiverReceiver System-on-ChipSystem-on-Chip
SlobodanSlobodan Simovich,Simovich, IvanIvan P.P. Radivojevic,Radivojevic, T.T. J.J. Endres,Endres, TomTom Bentson,Bentson, RayRay Bingham,Bingham, TonyTony Blair,Blair, TomTom Cowling,Cowling, MarkMark Eylander,Eylander, RoryRory Fagan,Fagan, ChrisChris Long,Long, JimJim Longino,Longino, DanDan Olson,Olson, RollenRollen Subia, Subia, DougDoug WhitcombWhitcomb
Dotcast,Dotcast, Inc.Inc.
1 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document ContentContent
GeneralGeneral overviewoverview ofof thethe dNTSCdNTSCTMTM technologytechnology dNTSCdNTSCTMTM receiverreceiver technologytechnology ReXReX architecturearchitecture ReXReX microarchitecturemicroarchitecture andand implementationimplementation ConfigurableConfigurable StreamStream ProcessorProcessor (CSP)(CSP) ApplicationsApplications ofof thethe dNTSCdNTSCTMTM technologytechnology SummarySummary
2 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document dNTSCdNTSC™™ -- GGeneraleneral OverviewOverview
DatacastingDatacasting –– transfer transfer ofof datadata overover televisiontelevision dNTSCdNTSCTMTM –– technology technology forfor datacastingdatacasting overover analoganalog NTSCNTSC television:television: –– UpUp toto 4.5Mbit/sec4.5Mbit/sec perper analoganalog TVTV channelchannel –– ReceivableReceivable withinwithin TVTV station’sstation’s A-contourA-contour atat 1010-8-8 bitbit errorerror raterate (example:(example: A-contourA-contour inin LosLos AngelesAngeles -- 1.67 1.67 millionmillion households)households) ObtainedObtained FCCFCC licenselicense forfor thethe deploymentdeployment ofof dNTSCdNTSCTMTM inin JuneJune 20022002 TechnologyTechnology developeddeveloped andand productized:productized: modulator,modulator, receiver,receiver, antennaantenna (for(for indoorindoor reception)reception) CommercialCommercial serviceservice basedbased onon dNTSCdNTSCTMTM technologytechnology –– the the MovieBeamMovieBeamTMTM ServiceService byby WaltWalt DisneyDisney Corp.,Corp., scheduledscheduled forfor deploymentdeployment laterlater thisthis yearyear
3 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document dNTSCdNTSC™™ -- GGeneraleneral OverviewOverview
Visual data is modulated in VISUAL Visual data is modulated in CARRIER AURAL quadraturequadrature withwith NTSCNTSC CARRIER visualvisual carriercarrier andand auralaural datadata isis negativenegative amplitudeamplitude modulatedmodulated onon auralaural carriercarrier -- first first implementationimplementation usesuses visualvisual carrier,carrier, onlyonly VISUAL AM AURAL FM DataData insertedinserted coherentcoherent withwith NTSCNTSC framingframing –– symbol symbol raterate ~613KHz~613KHz DataData spectrumspectrum isis pre-pre- filteredfiltered andand subcarriersubcarrier VISUAL DATA carefullycarefully spacedspaced toto QUADRATURE AM minimizeminimize visualvisual impairmentimpairment withwith NTSCNTSC televisiontelevision
4 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document ReceiverReceiver DSPDSP ArchitectureArchitecture
Algorithm Video Sync implemented Processing in software
Feedforward Automatic Gain Control Fine Carrier Recovery
Video Isolation Adaptive Downconversion, Coarse Data Equalization, Forward A/D Decimation, and Carrier Video Data Error Converter I/Q split Recovery Cancellation, and Framer Correction Joint Controller Data Isolation Algorithm implemented Feedback in software Automatic Gain Control
ReX Receiver Chip
5 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document ReXReX DSPDSP ArchitectureArchitecture
DSPDSP ArchitecturalArchitectural Features:Features: VisualVisual subcarriersubcarrier only,only, 1-31-3 Mbps,Mbps, usingusing 4,16,32,4,16,32, 64,64, oror 128128 QAMQAM onon singlesingle subcarriersubcarrier thatthat isis aboutabout –26–26 dBdB belowbelow videovideo (relative(relative toto peakpeak ofof video)video) DataData spectrumspectrum occupiesoccupies aboutabout 1/61/6 ofof TVTV channel,channel, withoutwithout perceptiblyperceptibly corruptingcorrupting TVTV broadcastbroadcast TimingTiming recovery,recovery, automaticautomatic gaingain ccontrol,ontrol, andand datadata framingframing derivedderived fromfrom visualvisual TVTV signalsignal PatentPatent pendingpending adaptiveadaptive equalizequalizationation andand videovideo cancellationcancellation techniquestechniques forfor robustrobust (re)-acquisition(re)-acquisition inin harshharsh indoorindoor environmentenvironment Self-optimizingSelf-optimizing jointjoint controllercontroller (p(patentatent pending)pending) forfor optimumoptimum system-system- levellevel performanceperformance isis highlyhighly prograprogrammablemmable withwith performance-drivingperformance-driving featuresfeatures Field-provenField-proven errorerror correctioncorrection ususinging concatenatedconcatenated TrellisTrellis CodedCoded ModulationModulation andand aa Reed-SolomonReed-Solomon blockblock codecode
6 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document ReXReX ASICASIC ArchitectureArchitecture
Design Requirements: Functional robustness – must handle a wide variety of known and less-known phenomena in the field High computational performance –the dNTSC decoding algorithm alone requires >15 billion operations/sec (BOPS) Low cost – targeted to fit within a budget of a consumer electronics product.
7 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document ReXReX ASICASIC ArchitectureArchitecture
ASIC Design Philosophy: Simplicity Configurability and Programmability Low-risk fabrication technology
Implementation Goal: design a robust and reliable mass production part (on a tight schedule, of course)
8 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document ReXReX ASICASIC MicroarchitectureMicroarchitecture
ADC PCI Memory System GPIO Interface Tuner Interface Interface I/F Interface System-on-Chip: D S PCI SRAM MEMC Down- P CPU Subsystem – conversion I2C I2C GPIO Video Sync G system administrative Processing NPB Bus a Carrier Bridge functions: system I/O, Recovery t e TMR system interrupts, Video & Data w INTC Isolation a selected DSP y CPU DMA Subsystem Cntrl applications Video & Data CSP V850 CPU Equalization, VSB Bus Core Feedback AGC Bridge DSP Subsystem – DSP Framer Cache TM Subsystem dNTSC decoding Cntrl algorithm, FEC, general FEC MPEG I/F DSU I$ iROM D$ signal processing
DTV System JTAG MPEG MPEG Interface Interface
9 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document ReXReX ASICASIC MicroarchitectureMicroarchitecture
CPU Subsystem: Silicon Technology – NEC’s CB-10 (0.25 micron, 5 metal layer) CPU core NU85E (NEC) System Interface PCI, I2C, GPIO, MPEG Serial Tuner Interface I2C Clock speed 160/80 MHz On-chip SRAM 128 KByte On-chip ROM 16 KByte Instruction/Data Cache 8/4 KByte Debug Support N-Wire/JTAG External Memory Support ROM, FLASH, SRAM OS ThreadX
Note: CPU Subsystem is ~1/3 of the die area
10 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document ReXReX ASICASIC MicroarchitectureMicroarchitecture
MPEG I/F FEC DSP Subsystem: D-bus branch0
Feedback SLICER FRAMER Bus-based system - D-bus AGC
D-bus agents: EQ- EQCTRL adapt-1 D-bus branch1 – Dedicated programmable - DSP Gateway System FIRs, mixers, FEC, etc. Bus EQ- EQ- (VSB) adapt-2 adapt-3 – Fully programmable –CSP Coarse Connectivity: D-bus, and SYNC Carrier CSP_0 Recover D-bus dedicated connections branch7
Down- ADCNCO convert
Note: DSP Subsystem is ~2/3 of the die area
11 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document CSPCSP ArchitectureArchitecture
Configurable Stream Processor – CSP:
Proprietary general-purpose DSP core (patent pending) optimized for processing of data streams ISA consists of scalar and vector instructions - implies scalar and vector registers Configurable and programmable hardware buffers Input/output data stream transfer in parallel with pipe accesses Explicit and implicit buffer synchronization mechanisms
12 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document CSPCSP ArchitectureArchitecture
CPU CSP Pipe: Interface
CSEG Control 52 instructions (Instruction Registers (scalar, vector, bit- Memory)
wise, push/pop, etc.) Instruction Fetch 8-stage pipe and Decode 3 memory segments: Address Generation – CSEG (code) RF GDSEG DMA (Register File) (Buffer Memory) Interface
– GDSEG (buffers) scalar vector operands operands – LDSEG (data) Execution LDSEG Configurable buffers - Units (Data Memory) number and size RF/Buffer Writeback Interrupt support
13 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document CSPCSP ArchitectureArchitecture
Programmable Buffers: Input data supplied Coefficients loaded by the master CPU or via DMA input initialized under CSP program control Programmable number of channel buffers - 1 to 16 Buff0 Buff1 Buff2 Read Ptr Read Ptr
V0 D0 C0 D0 Programmable buffer (length = D1 V1 C1 V2 D1 4) D2 C2 D2 size – 128, 256, 512, 1K D3 C3 Write D3 D4 Ptr D9 D5 D8 locations D6 A vector register (or, a vector) is a portion of a Resulting vector V2 (in Buff2) could be read out buffer – vector length is by the DMA output round programmable channel or further MULTIPLY processed by other Vectors are accessed vector instructions. via vector instructions ACCUMULATE Conceptual view of Vector Multiplication SATURATE/ Implicit process FORMAT V2 = V0 x V1 ; synchronization - vector i=0...3 (V1 is a constant instruction will not start vector) “on an empty vector” 14 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document CSPCSP ArchitectureArchitecture
CSP Multiprocessing
CSP_1 CSP_2 CSP_3 CSP_4
CSP_5 CSP_6
DMA CSP_8
CSP_7 C x V x V C 1 2 Write Read Ptr Ptr Multiply C x V1
Multiply Write Read V V1 1 DMA Ptr Ptr DMA Write Read Ptr Ptr Write Read Ptr Ptr
Write Read Ptr Ptr
15 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document ReXReX ImplementationImplementation
Vital statistics:
0.25 micron (NEC) 5 metal layers ~3M gates 12.5mm x 12.5mm 160MHz max freq 352TBGA package taped out: 12/02 productized: 3/03 in the box: 5/03 in the field: 7/03
16 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document ApplicationsApplications ofof dNTSCdNTSCTMTM
ReX-based wireless set-top box
17 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document ApplicationsApplications ofof dNTSCdNTSCTMTM
dNTSCTM broadcast pipe delivers over 25GByte of raw media assets per day per antenna.
dNTSCTM is piggybacked on the existing TV infrastructure => extremely low cost distribution channel
Customer dot with Dotcast- TV Enabled Text Movi e s-On - Demand Player
Customer with Dotcast-Enabled Portable Device
18 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document SummarySummary
dNTSCdNTSCTMTM –– technology technology forfor datacastingdatacasting overover analoganalog NTSCNTSC televisiontelevision supportingsupporting upup toto 4.5Mbit/sec4.5Mbit/sec @@ 1010-8-8 BERBER withinwithin TVTV station’sstation’s AA contourcontour ReXReX –– first first ASICASIC implementationimplementation ofof thethe dNTSCdNTSCTMTM receiverreceiver technologytechnology supportingsupporting upup toto 3M3Mbit/secbit/sec overover visualvisual subcarriersubcarrier dNTSCdNTSCTMTM decodingdecoding algorithmalgorithm implementedimplemented inin ReXReX asas aa combinationcombination ofof dedicated-dedicated- and and fully-programmablefully-programmable processingprocessing elementselements (CSPs)(CSPs) ConfigurableConfigurable StreamStream ProcessorProcessor (CSP)(CSP) –– general-purpose general-purpose DSPDSP corecore optimizedoptimized forfor strstreameam processingprocessing applicationsapplications ReXReX productizedproductized andand willwill bebe ususeded inin aa consumerconsumer devicedevice scheduledscheduled forfor commercialcommercial depldeploymentoyment inin 20032003 –– Disney’s Disney’s MovieBeamMovieBeamTMTM ServiceService
19 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document www.www.dotcastdotcast.com.com
Dotcast Inc. 20425 72nd Avenue South, Suite 200 Kent, Washington 98032 U.S.A. 253-867-2000
email: [email protected]
20 © 2003 Dotcast Inc. - All Rights Reserved - Confidential Document