Microcontroller Serial Interfaces
Dr. Francesco Conti [email protected] Microcontroller System Architecture
Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU
Example: STM32F101 MCU Microcontroller System Architecture
Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU • Memory • RAM (from 512B to 256kB) • FLASH (from 512B to 1MB)
Example: STM32F101 MCU Microcontroller System Architecture
Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU • Memory • RAM (from 512B to 256kB) • FLASH (from 512B to 1MB) • Peripherals • DMA • Timer • Interfaces • Digital Interfaces • Analog Timer
DMAs Example: STM32F101 MCU Microcontroller System Architecture
Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU • Memory • RAM (from 512B to 256kB) • FLASH (from 512B to 1MB) • Peripherals • DMA • Timer • Interfaces • Digital • Analog • Interconnect Example: STM32F101 MCU • AHB system bus (ARM-based MCUs) • APB peripheral bus (ARM-based MCUs) Microcontroller System Architecture
Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU • Memory • RAM (from 512B to 256kB) • FLASH (from 512B to 1MB) • Peripherals • DMA • Timer • Interfaces • Digital • Analog • Interconnect Example: STM32F101 MCU • AHB system bus (ARM-based MCUs) • APB peripheral bus (ARM-based MCUs) MCU Interfaces
• Digital • Several protocols for inter-chip communication UART, I2C, SPI, USB,… • Serial communication protocols • Meant for short distances “inside the box” / on-board • Low complexity • Low cost • Low speed ( a few Mb/s at the fastest ) • Serial communication is employed where it is not practical, either in physical or cost terms, to move data in parallel between systems. MCU Interfaces
• Digital • Several protocols for inter-chip communication UART, I2C, SPI, USB,… • Serial communication protocols • Meant for short distances “inside the box” / on-board • Low complexity • Low cost • Low speed ( a few Mb/s at the fastest ) • Serial communication is employed where it is not practical, either in physical or cost terms, to move data in parallel between systems. • Analog • ADC (Analog-to-Digital Converter) • DAC (Digital-to-Analog Converter) • Comparator Memory-Mapped Peripherals Peripherals such as external interfaces in a microcontroller system are accessible via memory-mapped registers: • for peripheral configuration • for I/O addresses Memory Map
memory mapped Cortex-M3 load/store MCU core Memory-Mapped Peripherals Suppose our purpose is to blink a LED (i.e., a GPIO pin):
GPIOC_LED0_ADDR Memory-Mapped Peripherals Suppose our purpose is to blink a LED (i.e., a GPIO pin):
GPIOC_LED0_ADDR Memory-Mapped Peripherals Suppose our purpose is to blink a LED (i.e., a GPIO pin):
STORE GPIOC_LED0_ADDR,0x1
GPIOC_LED0_ADDR Memory-Mapped Peripherals Suppose our purpose is to blink a LED (i.e., a GPIO pin):
STORE GPIOC_LED0_ADDR,0x1
GPIOC_LED0_ADDR Memory-Mapped Peripherals Suppose our purpose is to blink a LED (i.e., a GPIO pin):
STORE GPIOC_LED0_ADDR,0x1
GPIOC_LED0_ADDR Microcontroller External Pins Configuration
MCUs are often pin-limited • Not enough I/O pins for all I/O peripherals and functions! Microcontroller External Pins Configuration
MCUs are often pin-limited • Not enough I/O pins for all I/O peripherals and functions! • Pins have to be multiplexed (shared) between peripherals and functions Microcontroller External Pins Configuration
MCUs are often pin-limited • Not enough I/O pins for all I/O peripherals and functions! • Pins have to be multiplexed (shared) between peripherals and functions
Most pins can be configured for several functions: • As input or output pin • As an interrupt pin • Setup a pull-up / pull-down internal resistor (NO floating pins!) Microcontroller External Pins Configuration
MCUs are often pin-limited • Not enough I/O pins for all I/O peripherals and functions! • Pins have to be multiplexed (shared) between peripherals and functions
Most pins can be configured for several functions: • As input or output pin • As an interrupt pin • Setup a pull-up / pull-down internal resistor (NO floating pins!) • Assigned as general-purpose I/O (GPIO) or to a specific peripheral • Digital peripherals such as UARTs, SPIs, I2Cs • Analog peripherals such as ADCs or DACs Microcontroller External Pins Configuration Example to understand how this functionality works in a MCU • the specific circuit and register may change wildly between MCUs
Memory-Mapped registers
Function Select Register PxSEL Interrupt Edge Select Register PxIES
Interrupt Enable Register PxIE Interrupt Flag Register PxIFG PAD 1 Direction Register PxDIR Output Register PxOUT Input Register PxIN
7 6 5 4 3 2 1 0 Serial Interface Standards
https://xkcd.com/927/ I2C: Inter-Integrated Circuit Bus - 1
• Usually pronounced “I-Squared-C” • Introduced by Philips (now NXP Semiconductors) in 1982 I2C: Inter-Integrated Circuit Bus - 1
• Usually pronounced “I-Squared-C” • Introduced by Philips (now NXP Semiconductors) in 1982 • Used for communication with external peripherals, for example: • EEPROMs • thermal sensors • real-time clocks I2C: Inter-Integrated Circuit Bus - 1
• Usually pronounced “I-Squared-C” • Introduced by Philips (now NXP Semiconductors) in 1982 • Used for communication with external peripherals, for example: • EEPROMs • thermal sensors • real-time clocks • Also used as a control interface for signal processing devices with separate data interfaces, for example: • radio frequency tuners • video decoders and encoders • audio processors I2C: Inter-Integrated Circuit Bus - 2
• Three supported speed modes: • slow (under 100 Kbps) • fast (400 Kbps) • high-speed (3.4 Mbps) – in I2C v.2.0 • Maximum inter-IC distance of about 3 meters • (for moderate speeds, less for high-speed) I2C: Inter-Integrated Circuit Bus - 2
• Three supported speed modes: • slow (under 100 Kbps) • fast (400 Kbps) • high-speed (3.4 Mbps) – in I2C v.2.0 • Maximum inter-IC distance of about 3 meters • (for moderate speeds, less for high-speed) • Can support multi-master mode • For complex applications • Communication is always started by a master, both in single-master and multi-master mode I2C: Inter-Integrated Circuit Bus - 2
• Three supported speed modes: • slow (under 100 Kbps) • fast (400 Kbps) • high-speed (3.4 Mbps) – in I2C v.2.0 • Maximum inter-IC distance of about 3 meters • (for moderate speeds, less for high-speed) • Can support multi-master mode • For complex applications • Communication is always started by a master, both in single-master and multi-master mode • Half-duplex synchronous communication scheme • the master of the communication generates the clock (SCL) on which data (SDA) is synchronized I2C: Inter-Integrated Circuit Bus - 3
• Based on two lines: • SCL (serial clock) • SDA (serial data)
• Pull-Up resistors, Pull-Down by open-drain drivers • Wired-AND: if any driver pulls down, the line is low (avoids short circuits) • Any module on the bus can act as master, slave or both • typical case: MCU is the master, peripherals/sensors are slaves I2C: Interface Protocol
address (7 or 10 bits) ack bit ack bit
SCL
SDA
start bit direction bit data payload stop bit
• In idle, both SCL and SDA are pulled-up to 1 I2C: Interface Protocol
address (7 or 10 bits) ack bit ack bit
SCL
SDA
start bit direction bit data payload stop bit
1. To start the communication, the master: • asserts the start bit (SDA 1→0 transition while SCL is still 1) • then, it starts generating the SCL clock • except for the start and stop bits, SDA transitions only when SCL is 0 I2C: Interface Protocol
address (7 or 10 bits) ack bit ack bit
SCL
SDA
start bit direction bit data payload stop bit
2. The master transmits the slave address: • broadcasted to all devices on the I2C bus • used to select the target slave • either 7 bits or 10 bits (newer devices – 7 bits address space is small!) • in the example, the address is 7’b1000001 I2C: Interface Protocol
address (7 or 10 bits) ack bit ack bit
SCL
SDA
start bit direction bit data payload stop bit
3. The master transmits a direction bit: • a 0 for master → slave (write) transfer • a 1 for slave → master (read) transfer • in the example, suppose a write transfer I2C: Interface Protocol
address (7 or 10 bits) ack bit ack bit
SCL
SDA
start bit direction bit data payload stop bit
4. The slave then acknowledges reception: • by driving SDA to 0 • if not acknowledged, the transaction must be repeated by the master I2C: Interface Protocol
address (7 or 10 bits) ack bit ack bit
SCL
SDA
start bit direction bit data payload stop bit
5. The master transmits its data payload: • each payload packet is 8 bits • there might be more than one packet, depending on application • in the example, data payload is 8’b00110100 I2C: Interface Protocol
address (7 or 10 bits) ack bit ack bit
SCL
SDA
start bit direction bit data payload stop bit
6. The slave acknowledges reception of the data packet: • 1 ack bit every 8 payload bits • slave must acknowledge each packet I2C: Interface Protocol
address (7 or 10 bits) ack bit ack bit
SCL
SDA
start bit direction bit data payload stop bit
7. At the end of the transfer, the master transmits a stop bit: • first, it sets SDA to 0 • then it releases SCL (i.e. it lets it go to 1) • finally, it releases SDA which also goes to 1 I2C: Interface Protocol
address (7 or 10 bits) ack bit ack bit
SCL
SDA
start bit direction bit data payload stop bit
Reads work similarly, but data transfer – ack roles are reversed: • the slave drives SDA when transmitting the data byte • the master acknowledges the transfer I2C: Clock Stretching
SCL
SDA
Slave can ask for more time to process a bit by clock stretching: • drive SCL to 0 if in need of more processing time I2C: MCU-Sensor Communication Example Example of MCU – sensor communication (data acquisition) via I2C bus I2C: Blackboard Exercise Consider a sensor: • the address of the sensor on the I2C bus is 7’b1010101 • the peripheral works at fast speed • the peripheral expects a command to be written (which is then stored in its control register) and will then stream out a packet of data • we need two I2C transactions: • activate it by writing a 1 into into its control register • extract 256 byte of data I2C: Blackboard Exercise Consider a sensor: • the address of the sensor on the I2C bus is 7’b1010101 • the peripheral works at fast speed • the peripheral expects a command to be written (which is then stored in its control register) and will then stream out a packet of data • we need two I2C transactions: • activate it by writing a 1 into into its control register • extract 256 byte of data 1. Draw a timing diagram covering the transfer up to the first data bit extracted from the sensor I2C: Blackboard Exercise Consider a sensor: • the address of the sensor on the I2C bus is 7’b1010101 • the peripheral works at fast speed • the peripheral expects a command to be written (which is then stored in its control register) and will then stream out a packet of data • we need two I2C transactions: • activate it by writing a 1 into into its control register • extract 256 byte of data 1. Draw a timing diagram covering the transfer up to the first data bit extracted from the sensor 2. How much time is needed, assuming there is no clock stretching and all packets are acknowledged? SPI: Serial Peripheral Interface - 1
• Introduced by Motorola (now Freescale Semiconductors) for the MC68HCxx line of microcontrollers • Use cases are generally similar to I2C • Generally faster than I2C (up to several Mbit/s) • Short-distance (i.e. on printed circuit boards) SPI: Serial Peripheral Interface - 1
• Introduced by Motorola (now Freescale Semiconductors) for the MC68HCxx line of microcontrollers • Use cases are generally similar to I2C • Generally faster than I2C (up to several Mbit/s) • Short-distance (i.e. on printed circuit boards) • Single-master, multiple slave • needs one chip select per slave device (no broadcast addressing) • Full-duplex synchronous communication scheme • master drives the clock (SCLK or SCK) • clock polarity (i.e. write/read edges) and phase depend on specific application! SPI: Serial Peripheral Interface - 2
MOSI MISO MCU CLK device CSN
• Based on two data and two control lines: • MISO (master-in, slave-out data) • MOSI (master-out, slave-in data) • SCK (clock) • CSN (chip select, one per slave – usually active low) • Names are not standard, beware! Some possible alternatives: • SDI (SPI data in) instead of MISO • SDO (SPI data out) instead of MOSI • SCLK, CLK, SPC, … instead of SCK • CS, SS (slave select), SSN (slave select, active low) ... instead of CSN SPI: Serial Peripheral Interface - 2
MOSI MISO MCU CLK device CSN
• Based on two data and two control lines: • MISO (master-in, slave-out data) • MOSI (master-out, slave-in data) • SCK (clock) • CSN (chip select, one per slave – usually active low) • Names are not standard, beware! Some possible alternatives: • SDI (SPI data in) instead of MISO • SDO (SPI data out) instead of MOSI • SCLK, CLK, SPC, … instead of SCK • CS, SS (slave select), SSN (slave select, active low) ... instead of CSN SPI: Serial Peripheral Interface - 3 • Full-duplex transfer: data is streamed between master and slave shift-registers / FIFO buffers: • the master pushes the content of its buffer to the slave via MOSI • the slave pushes the content of its buffer to the master via MISO • Processing / sensing / … happens in between (dashed line)
MOSI
FIFO out FIFO in
FIFO in FIFO out MISO MCU device SPI: Interface Protocol - 1 • Four operating modes, varying by clock polarity (CPOL) and phase (CPHA): • polarity sets the initial value of the SPI clock signal • phase defines the edge at which MOSI is switched and the one at which MISO is sampled
CSN
SCK
MOSI
MISO
slave samples master samples CPOL = 0 @posedge SCK @negedge SCK CPHA = 0 SPI: Interface Protocol - 1 • Four operating modes, varying by clock polarity (CPOL) and phase (CPHA): • polarity sets the initial value of the SPI clock signal • phase defines the edge at which MOSI is switched and the one at which MISO is sampled
CSN
SCK
MOSI
MISO
slave samples master samples CPOL = 01 @negedge SCK @posedge SCK CPHA = 1 SPI: Interface Protocol -1 • Four operating modes, varying by clock polarity (CPOL) and phase (CPHA): • polarity sets the initial value of the SPI clock signal • phase defines the edge at which MOSI is switched and the one at which MISO is sampled
CSN
SCK
MOSI
MISO
slave samples master samples CPOL = 1 @negedge SCK @posedge SCK CPHA = 0 SPI: Interface Protocol -1 • Four operating modes, varying by clock polarity (CPOL) and phase (CPHA): • polarity sets the initial value of the SPI clock signal • phase defines the edge at which MOSI is switched and the one at which MISO is sampled
CSN
SCK
MOSI
MISO
slave samples master samples CPOL = 1 @posedge SCK @negedge SCK CPHA = 1 SPI: Interface Protocol - 2 • Master completely in charge of transfer • no ack, no clock stretching contrarily to I2C SPI: Interface Protocol - 2 • Master completely in charge of transfer • no ack, no clock stretching contrarily to I2C • More complex behavior than simple data streaming can be mapped on top of SPI protocol • e.g. command + address + data streaming SPI vs I2C • For point-to-point, SPI is simple and efficient • Less overhead than I2C due to lack of addressing, plus SPI is full-duplex.
• For multiple slaves, each slave needs separate slave select signal SPI • SPI requires more effort and more hardware than I2C • Quad-SPI also exists • 4x the bandwidth, often used by Flash drives I2C SPI: Blackboard Exercise Consider again the same sensor of the previous exercise: • SPI works at 400 kb/s • the sensor begins streaming data out as soon as the command word is written to its control register • again, we need to • activate it by writing a 8’b1 into into its control register • extract 256 byte of data SPI: Blackboard Exercise Consider again the same sensor of the previous exercise: • SPI works at 400 kb/s • the sensor begins streaming data out as soon as the command word is written to its control register • again, we need to • activate it by writing a 8’b1 into into its control register • extract 256 byte of data 1. How much time is needed for the transfer? SPI: Blackboard Exercise Consider again the same sensor of the previous exercise: • SPI works at 400 kb/s • the sensor begins streaming data out as soon as the command word is written to its control register • again, we need to • activate it by writing a 8’b1 into into its control register • extract 256 byte of data 1. How much time is needed for the transfer? 2. How much time would be needed if the transfer speed was 1.2 Mb/s? SPI: Blackboard Exercise Consider again the same sensor of the previous exercise: • SPI works at 400 kb/s • the sensor begins streaming data out as soon as the command word is written to its control register • again, we need to • activate it by writing a 8’b1 into into its control register • extract 256 byte of data 1. How much time is needed for the transfer? 2. How much time would be needed if the transfer speed was 1.2 Mb/s? 3. What if the transfer involves 1) writing a 8 bit control register 2) writing 256 byte of data, 3) reading 256 byte of data? • Assume that to begin producing its output, the peripheral needs only the first 2 bytes of the input UART - 1
• Stands for Universal Asynchronous Receiver-Transmitter • sometimes also found as USART (Universal Synchronous- Asynchronous Receiver Transmitter) UART - 1
• Stands for Universal Asynchronous Receiver-Transmitter • sometimes also found as USART (Universal Synchronous- Asynchronous Receiver Transmitter) • Used to interface MCUs with other computing devices: • Communication with other processors, a PC (e.g. a serial terminal) • Used to interface the microcontroller with others transmission bus as: RS232, RS485, USB, CAN BUS, KNX, LonWorks ecc. • Used to connect MCUs with modems and transceivers as telephone modems, Bluetooth, Wi-Fi, GSM/GPRS/HDPSA UART - 1
• Stands for Universal Asynchronous Receiver-Transmitter • sometimes also found as USART (Universal Synchronous- Asynchronous Receiver Transmitter) • Used to interface MCUs with other computing devices: • Communication with other processors, a PC (e.g. a serial terminal) • Used to interface the microcontroller with others transmission bus as: RS232, RS485, USB, CAN BUS, KNX, LonWorks ecc. • Used to connect MCUs with modems and transceivers as telephone modems, Bluetooth, Wi-Fi, GSM/GPRS/HDPSA UART - 2 • Essentially a parallel2serial (TX), serial2parallel (RX) converter couple • e.g. using shift registers for P2S conversion UART - 2 • Essentially a parallel2serial (TX), serial2parallel (RX) converter couple • e.g. using shift registers for P2S conversion • Asynchronous: no common clock shared • Each device has its own local clock, typically running faster than the bit rate (e.g. 8x faster) • The phase of the receiver clock is locked onto the edge of the transmitted data
TX RX
MCU RX TX device UART - 2 • Essentially a parallel2serial (TX), serial2parallel (RX) converter couple • e.g. using shift registers for P2S conversion • Asynchronous: no common clock shared • Each device has its own local clock, typically running faster than the bit rate (e.g. 8x faster) • The phase of the receiver clock is locked onto the edge of the transmitted data
TX RX
MCU RX TX device
• Highly configurable • parity / no parity • data framing (e.g number of stop bits, number of payload bits) • simplex, full-duplex or half-duplex UART: “baud rate” vs “bit rate” • UART communication speed is defined by its symbol rate measured in baud: • 1 baud = 1 symbol per second • in UART, a symbol has two values (0/1) -> 1 bit • this number includes both data payload and protocol bits (e.g. parity, framing) – this number is also called “physical” or “gross” bit rate Ref. Wikipedia “Bit rate” page • This can cause some confusion • Some people use “bit rate” for UART when referring only to payload bits • In some devices (e.g. modems) one symbol might correspond to more bits -> baud rate is not the same as gross bit rate • Bottom line: to be 100% clear, always talk of baud rate when referring to UART, and remember that in UART 1 symbol = 1 bit UART: Interface Protocol
1. In idle, the transmission line is driven to 1 UART: Interface Protocol
1 start bit
2. The transfer begins with a start bit: • the transmission line is driven to 0 UART: Interface Protocol
1 start bit 5-9 data bits
2. Then, a symbol of 5 to 9 bits is transmitted: • most often, 8 bits (1 ASCII character) • the symbol size is defined by the application and known a-priori with respect to the communication UART: Interface Protocol
1 start bit 4-8 data bits 1 parity bit
3. One of the data bits can be used for parity:
N N • odd parity p odd = XOR b i even parity peven = XNOR bi i=1 i=1
• in this case, 4-8 bits can be used for data UART: Interface Protocol
1 start bit 4-8 data bits 1 parity bit 1-2 stop bits
4. Finally, 1-2 stop bits: • Transmission line brought back to 1 • 1 or 2 stop bits depending on application UART: Handshake The UART protocol can also include a handshake: • request-to-send (RTS) signal from the MCU to the device means that the MCU can accept new data • clear-to-send (CTS) signal from the device to the MCU means that the device can send new data • signals have dual meaning if seen from the other point of view • exchange happens when CTS and RTS are both asserted
TX RX RX TX MCU device CTS RTS RTS CTS UART: blackboard exercise Consider an MCU connected to a PC via UART (e.g. over USB) • assume a baud rate of 9600 baud • the MCU uses parity, 1 start bit and 1 stop bit and transmits a payload of 8 bits per frame • assume the MCU needs to print 1024 ASCII characters via the UART serial terminal to the PC 1. How much time is needed for the transfer? 2. How much time with a baud rate of 115200 baud? The next-generation: I3C
• An evolution of I2C proposed by the MIPI alliance (2016/7) • Designed to fit applications currently using I2C, SPI, UART • Many operating modes, I2C backward-compatibility also supported • without some of the most «exotic» features such as SCL stretching • supporting also (mainly) push-pull drivers • Targets high data rate and energy efficiency The next generation: I3C – 2 The next generation: I3C – 3 The next generation: I3C – 3
I2C backward compatible The next generation: I3C – 3
I2C backward compatible
Similar to I2C, but dynamic address The next generation: I3C – 3
I2C backward compatible
Broadcast message
Similar to I2C, but dynamic address The next generation: I3C – 3
I2C backward compatible
High-Data Rate (SPI-like)
Broadcast message
Similar to I2C, but dynamic address Yes, but how to actually use these interfaces?
• Now, we make a practical example • We’ll see a set of specific steps related to a specific STM32 microcontroller, but the concepts are general and adaptable to a wide range of MCUs Yes, but how to actually use these interfaces?
• Now, we make a practical example • We’ll see a set of specific steps related to a specific STM32 microcontroller, but the concepts are general and adaptable to a wide range of MCUs
• The purpose of this example is to: 1. Illustrate the procedure to use a peripheral interface in a real microcontroller 2. Show how to read technical documentation so that you can replicate this feat in a practical situation Yes, but how to actually use these interfaces?
• Now, we make a practical example • We’ll see a set of specific steps related to a specific STM32 microcontroller, but the concepts are general and adaptable to a wide range of MCUs
• The purpose of this example is to: 1. Illustrate the procedure to use a peripheral interface in a real microcontroller 2. Show how to read technical documentation so that you can replicate this feat in a practical situation
• The purpose of this example is not to teach the specific register names / numbers, etc. • So it’s not particularly useful to learn them by heart Yes, but how to actually use these interfaces?- 2
• Our task is to use the third I2C interface (I2C3) on a STM32-F401 microcontroller device Yes, but how to actually use these interfaces?- 2
• Our task is to use the third I2C interface (I2C3) on a STM32-F401 microcontroller device
• The steps shown here correspond to what you would do in C code using the STM32 Standard Peripheral Library (SPL) Yes, but how to actually use these interfaces?- 2
• Our task is to use the third I2C interface (I2C3) on a STM32-F401 microcontroller device
• The steps shown here correspond to what you would do in C code using the STM32 Standard Peripheral Library (SPL) • In practice, the SPL is actually easier to use than what we show here, as it abstracts low level details (e.g. registers) using C data structures, functions. • Next week, a taste of how the Standard Peripheral Library works on a simple case (blinking a LED). Practical case: Documentation
The information to use I2C (and in general the MCU) is typically contained in a datasheet: Practical case: Documentation
The information to use I2C (and in general the MCU) is typically contained in a datasheet:
And/or a reference manual: 2 1. The timers connected to APB2 clocked are to from TIMxCLK up connected timers The 1. STM32F401xBSTM32F401xC
Practical case: I C on STM32-F401 rmTMCKu o4 MHz. 42 TIMxCLK up to from 0. Understand the complexity! Figure STM32F401xB/STM3.
DocID024738 Rev 5 Rev DocID024738
to 84 MHz, while the timers connected to APB1 are clocked the timers connected to APB1 are clocked MHz, while 84 to 241Cbokdarm diagram block 32F401xC
Description 14/134 53 2 1. The timers connected to APB2 clocked are to from TIMxCLK up connected timers The 1. STM32F401xBSTM32F401xC
Practical case: I C on STM32-F401 rmTMCKu o4 MHz. 42 TIMxCLK up to from 0. Understand the complexity! core Figure STM32F401xB/STM3.
DocID024738 Rev 5 Rev DocID024738
to 84 MHz, while the timers connected to APB1 are clocked the timers connected to APB1 are clocked MHz, while 84 to 241Cbokdarm diagram block 32F401xC
Description 14/134 53 2 1. The timers connected to APB2 clocked are to from TIMxCLK up connected timers The 1. STM32F401xBSTM32F401xC
Practical case: I C on STM32-F401 rmTMCKu o4 MHz. 42 TIMxCLK up to from 0. Understand the complexity! core Figure STM32F401xB/STM3.
DocID024738 Rev 5 Rev DocID024738
to 84 MHz, while the timers connected to APB1 are clocked the timers connected to APB1 are clocked MHz, while 84 to 241Cbokdarm diagram block 32F401xC
I2C3 Description 14/134 53 2 1. The timers connected to APB2 clocked are to from TIMxCLK up connected timers The 1. STM32F401xBSTM32F401xC
Practical case: I C on STM32-F401 rmTMCKu o4 MHz. 42 TIMxCLK up to from 0. Understand the complexity! core Figure STM32F401xB/STM3.
DocID024738 Rev 5 Rev DocID024738
to 84 MHz, while the timers connected to APB1 are clocked the timers connected to APB1 are clocked MHz, while 84 to 241Cbokdarm diagram block 32F401xC
I2C3 Description 14/134 53 Practical case: I2C on STM32-F401
1. Enable the clock. Practical case: I2C on STM32-F401
1. Enable the clock.
1a. The first step is to scan the Reference Manual to find what bus in the system architecture the peripheral is attached to. Practical case: I2C on STM32-F401
1. Enable the clock.
1a. The first step is to scan the Reference Manual to find what bus in the system architecture the peripheral is attached to. Practical case: I2C on STM32-F401
1. Enable the clock.
1a. The first step is to scan the Reference Manual to find what bus in the system architecture the peripheral is attached to. • In the example, the bus is APB1. 2 1. The timers connected to APB2 clocked are to from TIMxCLK up connected timers The 1. STM32F401xBSTM32F401xC
Practical case: I C on STM32-F401 rmTMCKu o4 MHz. 42 TIMxCLK up to from 1. Enable the clock . core Figure STM32F401xB/STM3.
DocID024738 Rev 5 Rev DocID024738
to 84 MHz, while the timers connected to APB1 are clocked the timers connected to APB1 are clocked MHz, while 84 to 241Cbokdarm diagram block 32F401xC APB1
I2C3 Description 14/134 53 Practical case: I2C on STM32-F401
1. Enable the clock.
1b. Then, you look at the clock tree diagram to understand what clocks should be active. The prescalers define the frequency of the peripheral clock. Practical case: I2C on STM32-F401
1. Enable the clock.
1b. Then, you look at the clock tree diagram to understand what clocks should be active. The prescalers define the frequency of the peripheral clock. Practical case: I2C on STM32-F401
1. Enable the clock.
1b. Then, you look at the clock tree diagram to understand what clocks should be active. The prescalers define the frequency of the peripheral clock.
APB1 clk enable Practical case: I2C on STM32-F401
1. Enable the clock.
1c. You enable the relevant clock(s) by setting a value in the right bit a memory-mapped reset/clock control (RCC) registers. Practical case: I2C on STM32-F401
1. Enable the clock.
1c. You enable the relevant clock(s) by setting a value in the right bit a memory-mapped reset/clock control (RCC) registers. Practical case: I2C on STM32-F401
1. Enable the clock.
1c. You enable the relevant clock(s) by setting a value in the right bit a memory-mapped reset/clock control (RCC) registers. • In the example, you set bit 23 of register RCC_APB1ENR to 1. 2 1. The timers connected to APB2 clocked are to from TIMxCLK up connected timers The 1. STM32F401xBSTM32F401xC
Practical case: I C on STM32-F401 rmTMCKu o4 MHz. 42 TIMxCLK up to from 1. Enable the clock . core Figure STM32F401xB/STM3.
DocID024738 Rev 5 Rev DocID024738
RCC
to 84 MHz, while the timers connected to APB1 are clocked the timers connected to APB1 are clocked MHz, while 84 to 241Cbokdarm diagram block 32F401xC
I2C3 Description 14/134 53 Practical case: I2C on STM32-F401
2. Connect the pins to the correct function. Practical case: I2C on STM32-F401
2. Connect the pins to the correct function.
2a. You check which pins are associated to the interface you want to use. Practical case: I2C on STM32-F401
2. Connect the pins to the correct function.
2a. You check which pins are associated to the interface you want to use. Practical case: I2C on STM32-F401
2. Connect the pins to the correct function.
2a. You check which pins are associated to the interface you want to use. • In the example, the I2C3 interface uses pins C9 (for SDA) and A8 (for SCL). Practical case: I2C on STM32-F401
2. Connect the pins to the correct function.
2b. You activate the correct alternate function of the pins by setting some bits in the appropriate memory-mapped register. Practical case: I2C on STM32-F401
2. Connect the pins to the correct function.
2b. You activate the correct alternate function of the pins by setting some bits in the appropriate memory-mapped register. Practical case: I2C on STM32-F401
2. Connect the pins to the correct function.
2b. You activate the correct alternate function of the pins by setting some bits in the appropriate memory-mapped register. • In the example, you set both the AFHR9 bit field of register GPIOC_AFRH and the AFHR8 bit field of register GPIOA_AFRH to function 4 (4’b1000) 2 1. The timers connected to APB2 clocked are to from TIMxCLK up connected timers The 1. STM32F401xBSTM32F401xC
Practical case: I C on STM32-F401 rmTMCKu o4 MHz. 42 TIMxCLK up to from 2. Connect the pins to the correct function. core Figure STM32F401xB/STM3.
DocID024738 Rev 5 Rev DocID024738
GPIO ports
to 84 MHz, while the timers connected to APB1 are clocked the timers connected to APB1 are clocked MHz, while 84 to 241Cbokdarm diagram block 32F401xC
I2C3 Description 14/134 53 Practical case: I2C on STM32-F401
3. Configure the peripheral interface. Practical case: I2C on STM32-F401
3. Configure the peripheral interface.
3a. You write the peripheral memory-mapped control registers. Practical case: I2C on STM32-F401
3. Configure the peripheral interface.
3a. You write the peripheral memory-mapped control registers. Practical case: I2C on STM32-F401
3. Configure the peripheral interface.
3a. You write the peripheral memory-mapped control registers. • In the example, you can allow or disallow clock stretching (plus other options). The I2C3 peripheral must also know the APB1 clock frequency, therefore you must set it in the FREQ bit field. Practical case: I2C on STM32-F401
3. Configure the peripheral interface.
3b. You configure the SCL clock. Practical case: I2C on STM32-F401
3. Configure the peripheral interface.
3b. You configure the SCL clock. Practical case: I2C on STM32-F401
3. Configure the peripheral interface.
3b. You configure the SCL clock. • In the example, you can set the SCL clock to a submultiple frequency of the APB1 clock in the I2C_CCR register. Practical case: I2C on STM32-F401
4. Start the transfer. Practical case: I2C on STM32-F401
4. Start the transfer.
4a. You start the transfer by setting a start bit. Practical case: I2C on STM32-F401
4. Start the transfer.
4a. You start the transfer by setting a start bit. Practical case: I2C on STM32-F401
4. Start the transfer.
4a. You start the transfer by setting a start bit. • In the example, you set the START bit of the I2C_CR1 register to 1. Practical case: I2C on STM32-F401
4. Start the transfer.
4b. You check the status. Practical case: I2C on STM32-F401
4. Start the transfer.
4b. You check the status. Practical case: I2C on STM32-F401
4. Start the transfer.
4b. You check the status. • In the example, you read the I2C_SR1 register (this is required by the I2C peripheral in the STM32F401). Practical case: I2C on STM32-F401
4. Start the transfer.
4c. You configure I2C address and direction. Practical case: I2C on STM32-F401
4. Start the transfer.
4c. You configure I2C address and direction. Practical case: I2C on STM32-F401
4. Start the transfer.
4c. You configure I2C address and direction. • In the example, you write a 7 address bits and 1 direction bit into the I2C_DR register. Practical case: I2C on STM32-F401
5. Perform the transfer. Practical case: I2C on STM32-F401
5. Perform the transfer.
You read or write data packets in the I2C interface. Practical case: I2C on STM32-F401
5. Perform the transfer.
You read or write data packets in the I2C interface. Practical case: I2C on STM32-F401
5. Perform the transfer.
You read or write data packets in the I2C interface. • In the example, you read/write one byte at a time from/into the I2C_DR register. Practical case: I2C on STM32-F401
6. End the transfer. Practical case: I2C on STM32-F401
6. End the transfer.
You end the transfer by setting an appropriate value in the control register. Practical case: I2C on STM32-F401
6. End the transfer.
You end the transfer by setting an appropriate value in the control register. Practical case: I2C on STM32-F401
6. End the transfer.
You end the transfer by setting an appropriate value in the control register. • In the example, in case of a read you have to clear the ACK bit to 0. In case of a write, you have to set the STOP bit to 1. 2 1. The timers connected to APB2 clocked are to from TIMxCLK up connected timers The 1. STM32F401xBSTM32F401xC
Practical case: I C on STM32-F401 rmTMCKu o4 MHz. 42 TIMxCLK up to from 7. What you’d do for real…
DMA engine core Figure STM32F401xB/STM3. int
DocID024738 Rev 5 Rev DocID024738
to 84 MHz, while the timers connected to APB1 are clocked the timers connected to APB1 are clocked MHz, while 84 to 241Cbokdarm diagram block 32F401xC
SRAM I2C3 Description 14/134 53