DOCSLIB.ORG

ECE 4750 Computer Architecture, Fall 2020 T02 Fundamental Processor

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
ECE 4750 Computer Architecture, Fall 2020 T02 Fundamental Processor ECE 4750 Computer Architecture, Fall 2021 T02 Fundamental Processor Microarchitecture School of Electrical and Computer Engineering Cornell University revision: 2021-09-12-02-56 1 Processor Microarchitectural Design Patterns 4 1.1. Transactions and Steps . .4 1.2. Microarchitecture: Control/Datapath Split . .5 2 TinyRV1 Single-Cycle Processor 6 2.1. High-Level Idea for Single-Cycle Processors . .7 2.2. Single-Cycle Processor Datapath . .8 2.3. Single-Cycle Processor Control Unit . 14 2.4. Analyzing Performance . 14 3 TinyRV1 FSM Processor 17 3.1. High-Level Idea for FSM Processors . 18 3.2. FSM Processor Datapath . 18 3.3. FSM Processor Control Unit . 25 3.4. Analyzing Performance . 29 4 TinyRV1 Pipelined Processor 31 4.1. High-Level Idea for Pipelined Processors . 32 4.2. Pipelined Processor Datapath and Control Unit . 34 1 5 Pipeline Hazards: RAW Data Hazards 39 5.1. Expose in Instruction Set Architecture . 41 5.2. Hardware Stalling . 42 5.3. Hardware Bypassing/Forwarding . 43 5.4. RAW Data Hazards Through Memory . 47 6 Pipeline Hazards: Control Hazards 48 6.1. Expose in Instruction Set Architecture . 50 6.2. Hardware Speculation . 51 6.3. Interrupts and Exceptions . 54 7 Pipeline Hazards: Structural Hazards 59 7.1. Expose in Instruction Set Architecture . 60 7.2. Hardware Stalling . 61 7.3. Hardware Duplication . 62 8 Pipeline Hazards: WAW and WAR Name Hazards 62 8.1. Software Renaming . 64 8.2. Hardware Stalling . 65 9 Summary of Processor Performance 65 10 Case Study: Transition from CISC to RISC 69 10.1. Example CISC: IBM 360/M30 . 70 10.2. Example RISC: MIPS R2K . 73 Copyright © 2016 Christopher Batten. All rights reserved. This handout was originally prepared by Prof. Christopher Batten at Cornell University for ECE 4750 / CS 4420. It has 2 been updated in 2017-2021 by Prof. Christina Delimitrou. Download and use of this hand- out is permitted for individual educational non-commercial purposes only. Redistribution either in part or in whole via both commercial or non-commercial means requires written permission. 3 1. Processor Microarchitectural Design Patterns 2.0. Transactions and Steps 1. Processor Microarchitectural Design Patterns Time Instructions Avg Cycles Time = × × Program Program Instruction Cycle • Instructions / program depends on source code, compiler, ISA • Avg cycles / instruction (CPI) depends on ISA, microarchitecture • Time / cycle depends upon microarchitecture and implementation Microarchitecture CPI Cycle Time Single-Cycle Processor 1 long FSM Processor >1 short Pipelined Processor ≈1 short 1.1. Transactions and Steps • We can think of each instruction as a transaction • Executing a transaction involves a sequence of steps add addi mul lw sw jal jr bne Fetch Instruction 3 3 3 3 3 3 3 3 Decode Instruction 3 3 3 3 3 3 3 3 Read Registers 3 3 3 3 3 3 3 Register Arithmetic 3 3 3 3 3 3 Read Memory 3 Write Memory 3 Write Registers 3 3 3 3 3 Update PC 3 3 3 3 3 3 3 3 3 1. Processor Microarchitectural Design Patterns1.2.Microarchitecture: Control/Datapath Split 1.2. Microarchitecture: Control/Datapath Split Control Unit Control Signals Status Signals Datapath imem imem imem dmem dmem dmem req_val req resp req_val req resp Memory 4 2. TinyRV1 Single-Cycle Processor 2.1. High-Level Idea for Single-Cycle Processors 2. TinyRV1 Single-Cycle Processor Time Instructions Avg Cycles Time = × × Program Program Instruction Cycle • Instructions / program depends on source code, compiler, ISA • Avg cycles / instruction (CPI) depends on ISA, microarchitecture • Time / cycle depends upon microarchitecture and implementation Microarchitecture CPI Cycle Time Single-Cycle Processor1 long FSM Processor >1 short Pipelined Processor ≈1 short Technology Constraints • Assume technology where Control Unit logic is not too expensive, so Control Status we do not need to overly Datapath minimize the number of registers and combinational logic regfile • Assume multi-ported register file with a reasonable number of ports is feasible imem imem dmem dmem req resp req resp • Assume a dual-ported Memory combinational memory <1 cycle combinational 5 2. TinyRV1 Single-Cycle Processor 2.1. High-Level Idea for Single-Cycle Processors 2.1. High-Level Idea for Single-Cycle Processors add addi mul lw sw jal jr bne Fetch Instruction 3 3 3 3 3 3 3 3 Decode Instruction 3 3 3 3 3 3 3 3 Read Registers 3 3 3 3 3 3 3 Register Arithmetic 3 3 3 3 3 3 Read Memory 3 Write Memory 3 Write Registers 3 3 3 3 3 Update PC 3 3 3 3 3 3 3 3 Fetch Decode Reg Read Write Fetch Decode Reg Write Fetch Decode Write Inst Inst Arith Mem Reg Inst Inst Arith Reg Inst Inst Reg lw Read Update add Read Update jal Update Reg PC Reg PC PC Single-Cycle 6 2. TinyRV1 Single-Cycle Processor 2.2. Single-Cycle Processor Datapath 2.2. Single-Cycle Processor Datapath ADD 31 25 24 20 19 15 14 12 11 7 6 0 add rd, rs1, rs2 0000000rs2rs1 000 rd 0110011 R[rd] ← R[rs1] + R[rs2] PC ← PC + 4 regfile regfile (read) (write) pc ADDI 31 20 19 15 14 12 11 7 6 0 addi rd, rs1, imm imm rs1000 rd 0010011 R[rd] ← R[rs1] + sext(imm) PC ← PC + 4 regfile regfile (read) (write) pc 7 2. TinyRV1 Single-Cycle Processor 2.2. Single-Cycle Processor Datapath Implementing ADD and ADDI Instructions To control unit ir[11:7] pc_plus4 ir[19:15] regfile regfile (read) alu (write) ir[24:20] +4 ir[31:7] imm pc gen op2_sel imemreq. imemresp. addr data MUL 31 19202425 11121415 067 mul rd, rs1, rs2 0000001rs2 000rs1 rd 0110011 R[rd] ← R[rs1] × R[rs2] PC ← PC + 4 To control unit ir[11:7] mul wb_sel pc_plus4 ir[19:15] regfile regfile (read) alu (write) ir[24:20] +4 ir[31:7] imm pc gen op2_sel imemreq. imemresp. addr data 8 2. TinyRV1 Single-Cycle Processor 2.2. Single-Cycle Processor Datapath LW 31 20 19 15 14 12 11 7 6 0 lw rd, imm(rs1) imm rs1010 rd 0000011 R[rd] ← M[ R[rs1] + sext(imm) ] PC ← PC + 4 To control unit ir[11:7] mul wb_sel pc_plus4 ir[19:15] regfile regfile (read) alu (write) ir[24:20] +4 ir[31:7] imm pc gen op2_sel imemreq. imemresp. dmemreq. dmemresp. addr data addr data SW 31 25 24 20 19 15 14 12 11 7 6 0 sw rs2, imm(rs1) imm rs2 rs1010 imm 0100011 M[ R[rs1] + sext(imm) ] ← R[rs2] imm = { inst[31:25], inst[11:7] } PC ← PC + 4 To control unit ir[11:7] rf_wen mul wb_sel pc_plus4 ir[19:15] regfile regfile (read) alu (write) ir[24:20] +4 ir[31:7] imm pc gen imm_type op2_sel imemreq. imemresp. dmemreq. dmemreq. dmemresp. addr data data addr data 9 2. TinyRV1 Single-Cycle Processor 2.2. Single-Cycle Processor Datapath JAL 31 1112 067 jal rd, imm imm rd 1101111 R[rd] ← PC + 4 imm = { inst[31], inst[19:12], inst[20], inst[30:21], 0 } PC ← PC + sext(imm) To control unit ir[11:7] rf_wen jalbr_targ mul wb_sel pc_plus4 ir[19:15] regfile regfile (read) alu (write) ir[24:20] +4 imm alu_func ir[31:7] gen pc_sel pc imm_type + op2_sel imemreq. imemresp. dmemreq. dmemreq. dmemresp. addr data data addr data JR 31 1920 11121415 067 jr rs1 000000000000 000rs100000 1100111 PC ← R[rs1] To control unit jr_targ ir[11:7] rf_wen jalbr_targ mul wb_sel pc_plus4 ir[19:15] regfile regfile (read) alu (write) ir[24:20] +4 imm alu_func ir[31:7] gen pc_sel pc imm_type + op2_sel imemreq. imemresp. dmemreq. dmemreq. dmemresp. addr data data addr data 10 2. TinyRV1 Single-Cycle Processor 2.2. Single-Cycle Processor Datapath BNE 31 2425 1920 11121415 067 bne rs1, rs2, imm imm rs2 001rs1imm 1100011 if ( R[rs1] != R[rs2] ) PC ← PC + sext(imm) imm = { inst[31], inst[7], inst[30:25], inst[11:8], 0 } else PC ← PC + 4 To control unit jr_targ ir[11:7] rf_wen jalbr_targ mul eq wb_sel pc_plus4 ir[19:15] regfile regfile (read) alu (write) ir[24:20] +4 imm alu_func ir[31:7] gen pc_sel pc imm_type + op2_sel imemreq. imemresp. dmemreq. dmemreq. dmemresp. addr data data addr data 11 2. TinyRV1 Single-Cycle Processor 2.2. Single-Cycle Processor Datapath Adding a New Auto-Incrementing Load Instruction Draw on the datapath diagram what paths we need to use as well as any new paths we will need to add in order to implement the following auto-incrementing load instruction. LW.AI 31 1920 11121415 067 lw.ai rd, imm(rs1) imm 000rs1rd 0001011 R[rd] ← M[ R[rs1] + sext(imm) ] R[rs1] ← R[rs1] + 4 PC ← PC + 4 To control unit jr_targ ir[11:7] rf_wen jalbr_targ mul eq wb_sel pc_plus4 ir[19:15] regfile regfile (read) alu (write) ir[24:20] +4 imm alu_func ir[31:7] gen pc_sel pc imm_type + op2_sel imemreq. imemresp. dmemreq. dmemreq. dmemresp. addr data data addr data 12 2. TinyRV1 Single-Cycle Processor 2.3. Single-Cycle Processor Control Unit 2.3. Single-Cycle Processor Control Unit imem dmem pc imm op1 alu wb rf req req inst sel type sel func sel wen val val add pc+4 – rf + alu 1 10 addi mul pc+4 – – – mul 1 10 lw pc+4 i imm + mem 1 1 1 sw jal jr jr i – – –010 bne Need to factor eq status signal into pc_sel signal for BNE! 2.4. Analyzing Performance Time Instructions Cycles Time = × × Program Program Instruction Cycles • Instructions / program depends on source code, compiler, ISA • Cycles / instruction (CPI) depends on ISA, microarchitecture • Time / cycle depends upon microarchitecture and implementation 13 2.
Load more

Recommended publications
  • Inside Intel® Core™ Microarchitecture Setting New Standards for Energy-Efficient Performance
    White Paper Inside Intel® Core™ Microarchitecture Setting New Standards for Energy-Efficient Performance Ofri Wechsler Intel Fellow, Mobility Group Director, Mobility Microprocessor Architecture Intel Corporation White Paper Inside Intel®Core™ Microarchitecture Introduction Introduction 2 The Intel® Core™ microarchitecture is a new foundation for Intel®Core™ Microarchitecture Design Goals 3 Intel® architecture-based desktop, mobile, and mainstream server multi-core processors. This state-of-the-art multi-core optimized Delivering Energy-Efficient Performance 4 and power-efficient microarchitecture is designed to deliver Intel®Core™ Microarchitecture Innovations 5 increased performance and performance-per-watt—thus increasing Intel® Wide Dynamic Execution 6 overall energy efficiency. This new microarchitecture extends the energy efficient philosophy first delivered in Intel's mobile Intel® Intelligent Power Capability 8 microarchitecture found in the Intel® Pentium® M processor, and Intel® Advanced Smart Cache 8 greatly enhances it with many new and leading edge microar- Intel® Smart Memory Access 9 chitectural innovations as well as existing Intel NetBurst® microarchitecture features. What’s more, it incorporates many Intel® Advanced Digital Media Boost 10 new and significant innovations designed to optimize the Intel®Core™ Microarchitecture and Software 11 power, performance, and scalability of multi-core processors. Summary 12 The Intel Core microarchitecture shows Intel’s continued Learn More 12 innovation by delivering both greater energy efficiency Author Biographies 12 and compute capability required for the new workloads and usage models now making their way across computing. With its higher performance and low power, the new Intel Core microarchitecture will be the basis for many new solutions and form factors. In the home, these include higher performing, ultra-quiet, sleek and low-power computer designs, and new advances in more sophisticated, user-friendly entertainment systems.
    [Show full text]
  • POWER-AWARE MICROARCHITECTURE: Design and Modeling Challenges for Next-Generation Microprocessors
    POWER-AWARE MICROARCHITECTURE: Design and Modeling Challenges for Next-Generation Microprocessors THE ABILITY TO ESTIMATE POWER CONSUMPTION DURING EARLY-STAGE DEFINITION AND TRADE-OFF STUDIES IS A KEY NEW METHODOLOGY ENHANCEMENT. OPPORTUNITIES FOR SAVING POWER CAN BE EXPOSED VIA MICROARCHITECTURE-LEVEL MODELING, PARTICULARLY THROUGH CLOCK- GATING AND DYNAMIC ADAPTATION. Power dissipation limits have Thus far, most of the work done in the area David M. Brooks emerged as a major constraint in the design of high-level power estimation has been focused of microprocessors. At the low end of the per- at the register-transfer-level (RTL) description Pradip Bose formance spectrum, namely in the world of in the processor design flow. Only recently have handheld and portable devices or systems, we seen a surge of interest in estimating power Stanley E. Schuster power has always dominated over perfor- at the microarchitecture definition stage, and mance (execution time) as the primary design specific work on power-efficient microarchi- Hans Jacobson issue. Battery life and system cost constraints tecture design has been reported.2-8 drive the design team to consider power over Here, we describe the approach of using Prabhakar N. Kudva performance in such a scenario. energy-enabled performance simulators in Increasingly, however, power is also a key early design. We examine some of the emerg- Alper Buyuktosunoglu design issue in the workstation and server mar- ing paradigms in processor design and com- kets (see Gowan et al.)1 In this high-end arena ment on their inherent power-performance John-David Wellman the increasing microarchitectural complexities, characteristics. clock frequencies, and die sizes push the chip- Victor Zyuban level—and hence the system-level—power Power-performance efficiency consumption to such levels that traditionally See the “Power-performance fundamentals” Manish Gupta air-cooled multiprocessor server boxes may box.
    [Show full text]
  • Hardware Architecture
    Hardware Architecture Components Computing Infrastructure Components Servers Clients LAN & WLAN Internet Connectivity Computation Software Storage Backup Integration is the Key ! Security Data Network Management Computer Today’s Computer Computer Model: Von Neumann Architecture Computer Model Input: keyboard, mouse, scanner, punch cards Processing: CPU executes the computer program Output: monitor, printer, fax machine Storage: hard drive, optical media, diskettes, magnetic tape Von Neumann architecture - Wiki Article (15 min YouTube Video) Components Computer Components Components Computer Components CPU Memory Hard Disk Mother Board CD/DVD Drives Adaptors Power Supply Display Keyboard Mouse Network Interface I/O ports CPU CPU CPU – Central Processing Unit (Microprocessor) consists of three parts: Control Unit • Execute programs/instructions: the machine language • Move data from one memory location to another • Communicate between other parts of a PC Arithmetic Logic Unit • Arithmetic operations: add, subtract, multiply, divide • Logic operations: and, or, xor • Floating point operations: real number manipulation Registers CPU Processor Architecture See How the CPU Works In One Lesson (20 min YouTube Video) CPU CPU CPU speed is influenced by several factors: Chip Manufacturing Technology: nm (2002: 130 nm, 2004: 90nm, 2006: 65 nm, 2008: 45nm, 2010:32nm, Latest is 22nm) Clock speed: Gigahertz (Typical : 2 – 3 GHz, Maximum 5.5 GHz) Front Side Bus: MHz (Typical: 1333MHz , 1666MHz) Word size : 32-bit or 64-bit word sizes Cache: Level 1 (64 KB per core), Level 2 (256 KB per core) caches on die. Now Level 3 (2 MB to 8 MB shared) cache also on die Instruction set size: X86 (CISC), RISC Microarchitecture: CPU Internal Architecture (Ivy Bridge, Haswell) Single Core/Multi Core Multi Threading Hyper Threading vs.
    [Show full text]
  • Microcontroller Serial Interfaces
    Microcontroller Serial Interfaces Dr. Francesco Conti [email protected] Microcontroller System Architecture Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU Example: STM32F101 MCU Microcontroller System Architecture Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU • Memory • RAM (from 512B to 256kB) • FLASH (from 512B to 1MB) Example: STM32F101 MCU Microcontroller System Architecture Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU • Memory • RAM (from 512B to 256kB) • FLASH (from 512B to 1MB) • Peripherals • DMA • Timer • Interfaces • Digital Interfaces • Analog Timer DMAs Example: STM32F101 MCU Microcontroller System Architecture Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU • Memory • RAM (from 512B to 256kB) • FLASH (from 512B to 1MB) • Peripherals • DMA • Timer • Interfaces • Digital • Analog • Interconnect Example: STM32F101 MCU • AHB system bus (ARM-based MCUs) • APB peripheral bus (ARM-based MCUs) Microcontroller System Architecture Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU • Memory • RAM (from 512B to 256kB) • FLASH
    [Show full text]
  • Reverse Engineering X86 Processor Microcode
    Reverse Engineering x86 Processor Microcode Philipp Koppe, Benjamin Kollenda, Marc Fyrbiak, Christian Kison, Robert Gawlik, Christof Paar, and Thorsten Holz, Ruhr-University Bochum https://www.usenix.org/conference/usenixsecurity17/technical-sessions/presentation/koppe This paper is included in the Proceedings of the 26th USENIX Security Symposium August 16–18, 2017 • Vancouver, BC, Canada ISBN 978-1-931971-40-9 Open access to the Proceedings of the 26th USENIX Security Symposium is sponsored by USENIX Reverse Engineering x86 Processor Microcode Philipp Koppe, Benjamin Kollenda, Marc Fyrbiak, Christian Kison, Robert Gawlik, Christof Paar, and Thorsten Holz Ruhr-Universitat¨ Bochum Abstract hardware modifications [48]. Dedicated hardware units to counter bugs are imperfect [36, 49] and involve non- Microcode is an abstraction layer on top of the phys- negligible hardware costs [8]. The infamous Pentium fdiv ical components of a CPU and present in most general- bug [62] illustrated a clear economic need for field up- purpose CPUs today. In addition to facilitate complex and dates after deployment in order to turn off defective parts vast instruction sets, it also provides an update mechanism and patch erroneous behavior. Note that the implementa- that allows CPUs to be patched in-place without requiring tion of a modern processor involves millions of lines of any special hardware. While it is well-known that CPUs HDL code [55] and verification of functional correctness are regularly updated with this mechanism, very little is for such processors is still an unsolved problem [4, 29]. known about its inner workings given that microcode and the update mechanism are proprietary and have not been Since the 1970s, x86 processor manufacturers have throughly analyzed yet.
    [Show full text]
  • Intel(R) Software Guard Extensions Developer Guide
    Intel® Software Guard Extensions (Intel® SGX) Developer Guide Intel(R) Software Guard Extensions Developer Guide Legal Information No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest forecast, sched- ule, specifications and roadmaps. The products and services described may contain defects or errors known as errata which may cause deviations from published specifications. Current char- acterized errata are available on request. Intel technologies features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at Intel.com, or from the OEM or retailer. Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548-4725 or by visiting www.in- tel.com/design/literature.htm. Intel, the Intel logo, Xeon, and Xeon Phi are trademarks of Intel Corporation in the U.S. and/or other countries. Optimization Notice Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel micro- processors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations.
    [Show full text]
  • Itanium® 2 Processor Microarchitecture Overview
    Itanium® 2 Processor Microarchitecture Overview Don Soltis, Mark Gibson Cameron McNairy Hot Chips 14, August 2002 Itanium® 2 Processor Overview 16KB16KB L1L1 I-cacheI-cache BranchBranch PredictPredict 2 bundles (128 bits each) InstrInstr 22 InstrInstr 11 InstrInstr 00 TemplateTemplate Issue up to 6 instructions to the 11 pipes FF FF M/AM/A M/AM/A M/AM/A M/AM/A I/AI/A I/AI/A BB BB BB 22 FMACsFMACs 66 ALUsALUs BranchBranch UnitUnit 6 Opnds 2 Preds 16KB16KB L1L1 D-cacheD-cache 12 Opnds 2 Results 4 Preds 6 Results 2 Loads, 2 Stores 6 Predicates 128 FP GPRs 128 Int GPRs Consumed 1 Predicate 3 Predicates 128 FP GPRs 4 Predicates 128 Int GPRs 12 Predicates Produced Block Diagram 64 Predicate Registers 4 Loads 64 Predicate Registers 2 Stores 256KB256KB L2L2 CacheCache 3MB3MB L3L3 CacheCache BusBus InterfaceInterface Hot Chips 14 Itanium® 2 Processor Overview EXEEXE DETDET WRBWRB IPGIPG ROTROT EXPEXP RENREN REGREG FP1FP1 FP2FP2 FP3FP3 FP4FP4 WRBWRB IPG: Instruction Pointer Generate, Instruction address to L1 I-cache ROT: Present 2 Instruction Bundles from L1 I-cache to dispersal hardware EXP: Disperse up to 6 instruction syllables from the 2 instruction bundles REN: Rename (or convert) virtual register IDs to physical register IDs REG: Register file read, or bypass results in flight as operands EXE: Execute integer instructions; generate results and predicates DET: Detect exceptions, traps, etc. FP1-4: Execute floating point instructions; generate results and predicates Main Execution Unit Pipeline WRB: Write back results to the register file
    [Show full text]
  • Microarchitecture-Level Soc Design 27 Young-Hwan Park, Amin Khajeh, Jun Yong Shin, Fadi Kurdahi, Ahmed Eltawil, and Nikil Dutt
    Microarchitecture-Level SoC Design 27 Young-Hwan Park, Amin Khajeh, Jun Yong Shin, Fadi Kurdahi, Ahmed Eltawil, and Nikil Dutt Abstract In this chapter we consider the issues related to integrating microarchitectural IP blocks into complex SoCs while satisfying performance, power, thermal, and reliability constraints. We first review different abstraction levels for SoC design that promote IP reuse, and which enable fast simulation for early functional validation of the SoC platform. Since SoCs must satisfy a multitude of interrelated constraints, we then present high-level power, thermal, and reliability models for predicting these constraints. These constraints are not unrelated and their interactions must be considered, modeled and evaluated. Once constraints are modeled, we must explore the design space trading off performance, power and reliability. Several case studies are presented illustrating how the design space can be explored across layers, and what modifications could be applied at design time and/or runtime to deal with reliability issues that may arise. Acronyms AHB Advanced High-performance Bus APB Advanced Peripheral Bus ASIC Application-Specific Integrated Circuit BER Bit Error Rate BLB Bit Lock Block Y.-H. Park Digital Media and Communications R&D Center, Samsung Electronics, Seoul, Korea e-mail: [email protected] A. Khajeh Broadcom Corp., San Jose, CA, USA e-mail: [email protected] J. Yong Shin • F. Kurdahi () • A. Eltawil • N. Dutt Center for Embedded and Cyber-Physical Systems, University of California Irvine, Irvine, CA, USA e-mail: [email protected]; [email protected]; [email protected]; [email protected] © Springer Science+Business Media Dordrecht 2017 867 S.
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • Digital and System Design
    Digital System Design — Use of Microcontroller RIVER PUBLISHERS SERIES IN SIGNAL, IMAGE & SPEECH PROCESSING Volume 2 Consulting Series Editors Prof. Shinsuke Hara Osaka City University Japan The Field of Interest are the theory and application of filtering, coding, trans- mitting, estimating, detecting, analyzing, recognizing, synthesizing, record- ing, and reproducing signals by digital or analog devices or techniques. The term “signal” includes audio, video, speech, image, communication, geophys- ical, sonar, radar, medical, musical, and other signals. • Signal Processing • Image Processing • Speech Processing For a list of other books in this series, see final page. Digital System Design — Use of Microcontroller Dawoud Shenouda Dawoud R. Peplow University of Kwa-Zulu Natal Aalborg Published, sold and distributed by: River Publishers PO box 1657 Algade 42 9000 Aalborg Denmark Tel.: +4536953197 EISBN: 978-87-93102-29-3 ISBN:978-87-92329-40-0 © 2010 River Publishers All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, mechanical, photocopying, recording or otherwise, without prior written permission of the publishers. Dedication To Nadia, Dalia, Dina and Peter D.S.D To Eleanor and Caitlin R.P. v This page intentionally left blank Preface Electronic circuit design is not a new activity; there have always been good designers who create good electronic circuits. For a long time, designers used discrete components to build first analogue and then digital systems. The main components for many years were: resistors, capacitors, inductors, transistors and so on. The primary concern of the designer was functionality however, once functionality has been met, the designer’s goal is then to enhance per- formance.
    [Show full text]
  • Itanium Processor
    IA-64 Microarchitecture --- Itanium Processor By Subin kizhakkeveettil CS B-S5….no:83 INDEX • INTRODUCTION • ARCHITECTURE • MEMORY ARCH: • INSTRUCTION FORMAT • INSTRUCTION EXECUTION • PIPELINE STAGES: • FLOATING POINT PERFORMANCE • INTEGER PERFORMANCE • CONCLUSION • REFERENCES Itanium Processor • First implementation of IA-64 • Compiler based exploitation of ILP • Also has many features of superscalar INTRODUCTION • Itanium is the brand name for 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64). • Itanium's architecture differs dramatically from the x86 architectures (and the x86-64 extensions) used in other Intel processors. • The architecture is based on explicit instruction-level parallelism, in which the compiler makes the decisions about which instructions to execute in parallel Memory architecture • From 2002 to 2006, Itanium 2 processors shared a common cache hierarchy. They had 16 KB of Level 1 instruction cache and 16 KB of Level 1 data cache. The L2 cache was unified (both instruction and data) and is 256 KB. The Level 3 cache was also unified and varied in size from 1.5 MB to 24 MB. The 256 KB L2 cache contains sufficient logic to handle semaphore operations without disturbing the main arithmetic logic unit (ALU). • Main memory is accessed through a bus to an off-chip chipset. The Itanium 2 bus was initially called the McKinley bus, but is now usually referred to as the Itanium bus. The speed of the bus has increased steadily with new processor releases. The bus transfers 2x128 bits per clock cycle, so the 200 MHz McKinley bus transferred 6.4 GB/sand the 533 MHz Montecito bus transfers 17.056 GB/s.
    [Show full text]
  • Intel's Haswell CPU Microarchitecture
    Intel’s Haswell CPU Microarchitecture www.realworldtech.com/haswell-cpu/ David Kanter Over the last 5 years, high performance microprocessors have changed dramatically. One of the most significant influences is the increasing level of integration that is enabled by Moore’s Law. In the context of semiconductors, integration is an ever-present fact of life, reducing system power consumption and cost and increasing performance. The latest incarnation of this trend is the System-on-a-Chip (SoC) philosophy and design approach. SoCs have been the preferred solution for extremely low power systems, such as 1W mobile phone chips. However, high performance microprocessors span a much wider design space, from 15W notebook chips to 150W server sockets and the adoption of SoCs has been slower because of the more diverse market. Sandy Bridge was a dawn of a new era for Intel, and the first high-end x86 microprocessor that could truly be described as an SoC, integrating the CPU, GPU, Last Level Cache and system I/O. However, Sandy Bridge largely targets conventional PC markets, such as notebooks, desktops, workstations and servers, with a smattering of embedded applications. The competition for Sandy Bridge is largely AMD’s Bulldozer family, which has suffered from poor performance in the first few iterations. The 32nm Sandy Bridge CPU introduced AVX, a new instruction extension for floating point (FP) workloads and fundamentally changed almost every aspect of the pipeline, from instruction fetching to memory accesses. The system architecture was radically revamped, with a coherent ring interconnect for on-chip communication, a higher bandwidth Last Level Cache (LLC), integrated graphics and I/O, and comprehensive power management.
    [Show full text]