DOCSLIB.ORG

A Collaborative Approach to Advancing In-Vehicle Connectivity

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
A Collaborative Approach to Advancing In-Vehicle Connectivity A Collaborative Approach to Advancing In-Vehicle Connectivity Rick Wietfeldt, Ph.D. Director, MIPI Alliance Board of Directors Sr. Director Technology, Qualcomm 19 November 2020 1 | © 2019 MIPI Alliance, Inc. Presentation Outline • About MIPI Alliance • Automotive Industry Need • MIPI Automotive SerDes Solutions (MASSSM) and MIPI A-PHYSM • Summary 2 | © 2020 MIPI Alliance, Inc. About MIPI Alliance TODAY'S MIPI MEMBER ECOSYSTEM 3 | © 2020 MIPI Alliance, Inc. MIPI Specifications Leveraged Beyond Mobile 4 | © 2020 MIPI Alliance, Inc. Board and Contributor Members Contributor Members Board Members 5 | © 2020 MIPI Alliance, Inc. MIPI Liaisons: Extending The Mobile Ecosystem Security Automotive SIM, Secure Element Memory, Storage Displays Telecommunications Storage Connectivity Automotive 6 | © 2020 MIPI Alliance, Inc. Cross-Industry Convergence, Protocol Persistence • Semiconductor & ecosystem companies reuse assets (IP) to lower NRE/costs, including reuse of interface protocols – Making any interface change is difficult and costly. MIPI CSI, DSI, Backward compatibility is key. I3C, RFFE ... • Leading examples of evolution… reuse/extend: – USB: 1996+: USB 1, … USB 4 (adds DP, PCIe) … – SD: 1999+: SD, … SD v7 (adds PCIe) … – PCIe 2003+: PCIe Gen 1, … Gen 5, Gen 6 WIP – CSI-2 2005+: CSI-2 v1, … CSI-2 v3, … CSI-2 v4 WIP • Leverage includes cross-SDO cooperation: – USB4 adds DP & PCIe support; SD7 adds PCIe support • Evolution focuses on improving USB PCIe, DP UART Ethernet performance & reliability I2C I2CMIPI I3C – Encoding, equalization, error control, modulation DP … … – Functional safety and security CANbus Ethernet … 7 | © 2020 MIPI Alliance, Inc. MIPI in Automotive SPECIFICATIONS IN AUTOMOTIVE TODAY Most MIPI interfaces are implemented as "short reach" (15~30cm+) CSI-2SM I3C® Camera Serial Interface protocol Control and data bus protocol and Protocol for cameras, lidar, radar interface sensors Sensor and general-purpose data and control interface within a module DSI-2SM Display Serial Interface protocol RFFESM Protocol for smartphone, IOT and RF control protocol automotive displays Front-end control within a wireless module C-PHYSM SoundWire® & SWI3SSM 3-phase physical layer for CSI-2 Digital audio and control interface & DSI-2 Audio interface within a module Short-reach physical layer for cameras and displays UniPro® for JEDEC UFS Data transport protocol for UFS over M- Cameras, displays, audio, sensors, storage, RFFE for 5G, D-PHYSM PHY Transport protocol for UFS storage Wi-Fi, Bluetooth, NFC Differential physical layer for CSI-2 & DSI-2 M-PHY® for JEDEC UFS Reuse & extend well-proven protocols == reduced NRE/cost Short-reach physical layer for cameras and displays Differential physical layer for UFS storage Intra-box usage has been limited due to lack of native long- Short-reach physical transport for UFS storage reach PHY 8 | © 2020 MIPI Alliance, Inc. MIPI and the Mobile Gs . Including Automotive 9 | © 2020 MIPI Alliance, Inc. Automotive Industry Need MIPI 2017 Forecast for Display/Camera Payload … that Informed the A-PHY v1.0 Speed Target of 16 Gbps 11 | © 2020 MIPI Alliance, Inc. MIPI in High-Speed In-Vehicle Connectivity Coexistence of Edge and Networking Connectivity • High-speed Edge and Networking connectivity will coexist in automotive architectures • Networking: • Symmetric comms between ECUs • Edge: • Asymmetric comms from cameras-to-ECU and ECU-to- displays • MIPI is focused on asymmetric communications, leveraging its long history of protocol and SerDes PHY specification developments 12 | © 2020 MIPI Alliance, Inc. MIPI Automotive SerDes Solutions (MASS) and MIPI A-PHY MASS: A Conceptual View Certified cameras (displays) connect to the ECU over an enhanced CSI-2 (DSI-2) protocol, which includes functional safety and security protection. HDCP for premium content over DP/eDP and DSI-2 is also supported. By “certified” it is meant those camera/display peripherals that have been provisioned by a key authority(s) to support the MIPI security standards of authentication, encryption and integrity protection. 14 | © 2020 MIPI Alliance, Inc. MASS: Data Protection 15 | © 2020 MIPI Alliance, Inc. MASS: Bridge-to-Bridge Data Protection 16 | © 2020 MIPI Alliance, Inc. MASS: End-to-End Data Protection 17 | © 2020 MIPI Alliance, Inc. MASS: A More Detailed Look 3 1 2 3 2 1 4 6 4 5 Legend: 1 CSI-2 Protocol 2 CSI-2 SerDes Tx,Rx 3 CSI-2 FuSa & Security 4 DSI-2/DP Protocols 5 DSI-2/DP SerDes Tx,Rx 6 DSI-2/DP FuSa, Security, HDCP 5 4 6 18 | © 2020 MIPI Alliance, Inc. MIPI Automotive Stack 19 | © 2020 MIPI Alliance, Inc. A-PHY v1.0 Released – 15 September 2020 Members named in press release: • Beijing ASL Technology • Qualcomm • BitifEye Digital Test • Robert Bosch Solutions • Sony • Intel • STMicroelectronics • Luxshare-ICT • Synopsys • MediaTek • Tektronix • Mixel • Teledyne LeCroy • ON Semiconductor • Toshiba Electronics • Parade Technologies • Valens • Primesoc Technologies Semiconductor • Prodigy Technovations 20 | © 2020 MIPI Alliance, Inc. MIPI A-PHY Overview Asymmetric SerDes physical layer specification targeted for ADAS/ADS surround sensor applications and infotainment display applications A-PHY v1.0 offers: • Direct coupling to CSI- 2/DSI-2/DP-eDP protocols, supporting bridge-based & endpoint integration • High performance of 2- 16 Gbps over 10-15m, with roadmap to 24- 48+ Gbps • High noise immunity, ultra-low PER (< 10-19) Lower cost through standardization and economies of scale Lower cost/eBOM through integration • Support for automotive coax and SDP channels 21 | © 2020 MIPI Alliance, Inc. A-PHY Performance and Immunity-Based Profiles Performance requirements vary: • 8MP camera sensors might require “8 Gbps” per camera • 4K displays might require “16 Gbps” per display (uncompressed) • These interface speeds increase with aggregation and daisy- chain use cases Noise immunity (EMC RF Ingress) requirements vary: • Different OEMs have different requirements • MIPI-conducted tests in independent labs evaluated noise levels and shielding effect degradation after mechanical stress and aging A-PHY supports two performance & immunity profiles: • P1 (NRZ): Lower noise immunity, similar to other SerDes Performance- and Immunity-based profiles: solutions, and applicable to the lower speed gears (G1 and • P1 offers the lowest cost at the lower performance needs G2, optional at G3) • P2 offers the highest performance and immunity • P2 (PAM-X): Very high noise immunity to meet the expected noise levels over 10-15m and the car lifetime period 22 | © 2020 MIPI Alliance, Inc. MIPI Automotive Guiding Principles 23 | © 2020 MIPI Alliance, Inc. Concluding Thoughts • Asymmetric interfaces are key to surround sensor applications for ADAS/autonomous driving • MIPI A-PHY is the first long-reach asymmetric SerDes PHY standard, offering performance- and immunity-based profiles to meet a broad spectrum of requirements • With A-PHY as its foundation, MASS leverages existing protocols (MIPI CSI-2 and DSI-2, VESA DP and eDP, and more) to simplify integration while adding functional safety and security • This approach enables end-to-end data protection, from data source to data sink • Standardization drives economies of scale, increases choice and interoperability, and reduces cost and eBOM • The majority of MASS specifications will be completed by early 2021 24 | © 2020 MIPI Alliance, Inc. Thanks for listening MIPI Automotive Resources More information can be found at: • Press Release: MIPI Alliance Releases A-PHY SerDes Interface for Automotive • MIPI Automotive Homepage • MIPI A-PHY Specification Homepage • MIPI in Automotive White Paper 26 | © 2020 MIPI Alliance, Inc. .
Load more

Recommended publications
  • Powering AI and Automotive Applications with the MIPI Camera Interface Agenda
    Hyoung-Bae Choi Synopsys Powering AI and Automotive Applications with the MIPI Camera Interface Agenda Adoption of MIPI CSI-2℠ Image sensors beyond mobile AI and automotive examples CSI-2 interface overview Meeting reliability requirements of automotive applications Supporting artificial intelligence (AI) applications Summary © 2018 MIPI Alliance, Inc. 2 MIPI Specifications in New Applications Automotive, IoT / Wearables, Virtual / Augmented Reality © 2018 MIPI Alliance, Inc. 3 Industrial & Surveillance Applications Using MIPI CSI-2 Image Sensors © 2018 MIPI Alliance, Inc. 4 Example of MIPI in an Automotive Application MIPI CSI-2 Image Sensors & DSI Display MIPI CSI-2 Image Sensors Front Camera Module Vbat Power Supply Front Camera Left Camera MIPI DSI Right Display Module Camera Display Proprietary, LVDS or Right Camera MPU Left Ethernet Switch Module Camera CAN Interface Rear Camera Module Flash LVDS or Rear Camera DRAM Memory Ethernet Link Other Camera Module Other Camera Module © 2018 MIPI Alliance, Inc. 5 Safety-Critical ADAS Applications Require ISO 26262 Functional Safety Compliance and ASIL Certification Electronics failure can have hazardous impact Emergency braking Pedestrian detection Collision avoidance ≠ © 2018 MIPI Alliance, Inc. 6 MIPI Specs for Automotive Applications Infotainment Vehicle Networks & V2X • Real time video & data network • Gateways • Navigation • Telematics • Audio/Video • V2V • Entertainment • V2I • Security Driver Information Driver Assistance • Parking assist • Instrument clusters • Lane departure warning
    [Show full text]
  • OCP DC-SCM Specification
    Datacenter Secure Control Module Specification Authors: Priya Raghu, Senior Hardware Engineer, Microsoft Mark A. Shaw, Principal Hardware Engineering Manager, Microsoft Prakash Chauhan, Server Architect, Google Siamak Tavallaei, Chief Systems Architect, Google Mike Branch, Server Architect, Google Mason Possing, Hardware Engineer, Microsoft Open Compute Project • DC-SCM Specification Revision History Version Date Notes 0.8 Nov 9th 2020 Initial public review. 0.95 Dec 2nd 2020 Feedback Implemented Removed ESPI_CS1_N and replaced with RSVD3, Table 22:SPARE[0:1] desc, 1.0 March 11th Fig 22: Updated to initiator/Responder, Table 27: I3C pull-up updated to 2021 STBY/MAIN, Sec 6: Platform interop wording edit, Sec 2.2.3- Typo( FFF> HFF), Fig 3,4,5,6 updated, Table 3 updated http://opencompute.org ii Open Compute Project • DC-SCM Specification Contributions to this Specification are made under the terms and conditions set forth in Open Web Foundation Contributor License Agreement (“OWF CLA 1.0”) (“Contribution License”) by: Microsoft Corporation, Google LLC Usage of this Specification is governed by the terms and conditions set forth in the Open Web Foundation Final Specification Agreement (“OWFa 1.0”). Note: The following clarifications, which distinguish technology licensed in the Contribution License and/or Specification License from those technologies merely referenced (but not licensed), were accepted by the Incubation Committee of the OCP: INTELLIGENT PLATFORM MANAGEMENT INTERFACE (IPMI) I2C TRADEMARK OF PHILLIPS SEMICONDUCTOR I3C TRADEMARK OF MIPI ALLIANCE, INC USB TRADEMARK OF USB IMPLEMENTORS FORUM, INC PCIE TRADEMARK OF PCI-SIG ESPI TRADEMARK OF INTEL CORP NOTWITHSTANDING THE FOREGOING LICENSES, THIS SPECIFICATION IS PROVIDED BY OCP "AS IS" AND OCP EXPRESSLY DISCLAIMS ANY WARRANTIES (EXPRESS, IMPLIED, OR OTHERWISE), INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, OR TITLE, RELATED TO THE SPECIFICATION.
    [Show full text]
  • Microcontroller Serial Interfaces
    Microcontroller Serial Interfaces Dr. Francesco Conti [email protected] Microcontroller System Architecture Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU Example: STM32F101 MCU Microcontroller System Architecture Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU • Memory • RAM (from 512B to 256kB) • FLASH (from 512B to 1MB) Example: STM32F101 MCU Microcontroller System Architecture Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU • Memory • RAM (from 512B to 256kB) • FLASH (from 512B to 1MB) • Peripherals • DMA • Timer • Interfaces • Digital Interfaces • Analog Timer DMAs Example: STM32F101 MCU Microcontroller System Architecture Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU • Memory • RAM (from 512B to 256kB) • FLASH (from 512B to 1MB) • Peripherals • DMA • Timer • Interfaces • Digital • Analog • Interconnect Example: STM32F101 MCU • AHB system bus (ARM-based MCUs) • APB peripheral bus (ARM-based MCUs) Microcontroller System Architecture Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU • Memory • RAM (from 512B to 256kB) • FLASH
    [Show full text]
  • Server Base Manageability Requirements 1.0 Platform Design Document Non-Confidential
    Arm® Server Base Manageability Requirements 1.0 Platform Design Document Non-confidential Copyright © 2020 Arm Limited or its affiliates. All rights reserved. Document number: DEN0069B Server Base Manageability Requirements Server Base Manageability Requirements Copyright © 2020 Arm Limited or its affiliates. All rights reserved. Release inormation The Change History table lists the changes made to this document. Table 1-1 Change history Date Issue Confidentiality Change 30 January 2020 A Non-Confidential Initial release, SBMR 1.0 15 June 2020 B Non-Confidential License LES-PRE-21585 Page 2 of 45 Copyright © 2020 Arm Limited or its affiliates. All rights reserved. DEN0069B 1.0 Server Base Manageability Requirements Arm Non-Confidential Document Licence (“Licence”) This Licence is a legal agreement between you and Arm Limited (“Arm”) for the use of the document accompanying this Licence (“Document”). Arm is only willing to license the Document to you on condition that you agree to the terms of this Licence. By using or copying the Document you indicate that you agree to be bound by the terms of this Licence. If you do not agree to the terms of this Licence, Arm is unwilling to license this Document to you and you may not use or copy the Document. “Subsidiary” means any company the majority of whose voting shares is now or hereafter owner or controlled, directly or indirectly, by you. A company shall be a Subsidiary only for the period during which such control exists. This Document is NON-CONFIDENTIAL and any use by you and your Subsidiaries (“Licensee”) is subject to the terms of this Licence between you and Arm.
    [Show full text]
  • I3C Master IP Core - Lattice Radiant Software
    I3C Master IP Core - Lattice Radiant Software User Guide FPGA-IPUG-02082-1.0 December 2019 I3C Master IP Core - Lattice Radiant Software User Guide Disclaimers Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice. © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-IPUG-02082-1.0 I3C Master IP Core - Lattice Radiant Software User Guide Contents Acronyms in This Document ................................................................................................................................................
    [Show full text]
  • For MIPI I3C Version 1.0, FAQ Version
    Frequently Asked Questions (FAQ) for MIPI I3CSM Version 1.0 FAQ Version 1.0 08 December 2017 MIPI Board Approved 08 December 2017 Public Release Edition Further technical changes to this document are expected as work continues in the Sensor Working Group. Copyright © 2017 MIPI Alliance, Inc. FAQ for MIPI I3C v1.0 FAQ Version 1.0 08-Dec-2017 NOTICE OF DISCLAIMER The material contained herein is provided on an “AS IS” basis. To the maximum extent permitted by applicable law, this material is provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIPI Alliance Inc. (“MIPI”) hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of negligence. ALSO, THERE IS NO WARRANTY OR CONDITION OF TITLE, QUIET ENJOYMENT, QUIET POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD TO THIS MATERIAL. IN NO EVENT WILL ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL, CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR ANY OTHER AGREEMENT RELATING TO THIS MATERIAL, WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.
    [Show full text]
  • I3C Slave IP Core - Lattice Radiant Software
    I3C Slave IP Core - Lattice Radiant Software User Guide FPGA-IPUG-02083-1.2 June 2020 I3C Slave IP Core - Lattice Radiant Software User Guide Disclaimers Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice. © 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-IPUG-02083-1.2 I3C Slave IP Core - Lattice Radiant Software User Guide Contents Acronyms in This Document ................................................................................................................................................
    [Show full text]
  • 2-Wire Sideband Translator
    2-Wire Sideband Translator Component Specification for I3C/SMBUS Forwards/Backwards Compatibility February 2020 Revision 0.2 1 ©2020-2021 Intel Corporation – All rights reserved Intellectual Property Disclaimer THIS SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION, OR SAMPLE. A COPYRIGHT LICENSE IS HEREBY GRANTED TO REPRODUCE AND DISTRIBUTE THIS SPECIFICATION FOR INTERNAL USE ONLY. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY OTHER INTELLECTUAL PROPERTY RIGHTS IS GRANTED OR INTENDED HEREBY. INTEL CORPORATION AND THE AUTHORS OF THIS SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF PROPRIETARY RIGHTS, RELATING TO IMPLEMENTATION OF INFORMATION IN THIS DOCUMENT AND THE SPECIFICATION. INTEL CORPORATION AND THE AUTHORS OF THIS SPECIFICATION ALSO DO NOT WARRANT OR REPRESENT THAT SUCH IMPLEMENTATION(S) WILL NOT INFRINGE SUCH RIGHTS. ALL SUGGESTIONS OR FEEDBACK RELATED TO THIS SPECIFICATION BECOME THE PROPERTY OF INTEL CORPORATION UPON SUBMISSION. INTEL CORPORATION MAY MAKE CHANGES TO SPECIFICATIONS, PRODUCT DESCRIPTIONS, AND PLANS AT ANY TIME, WITHOUT NOTICE. Intel Corporation and its subsidiaries (collectively, “Intel”) would like to receive input, comments, suggestions and other feedback (collectively, “Feedback”) on this specification. To be considered for incorporation into the specification, Feedback must be submitted by e-mail to: [email protected]. To the extent that You provide Intel with Feedback, You grant to Intel a worldwide, non-exclusive, perpetual, irrevocable, royalty-free, fully paid, transferable license, with the right to sublicense, under Your Intellectual Property Rights, to make, use, sell, offer for sale, import, disclose, reproduce, make derivative works, distribute, or otherwise exploit Your Feedback without any accounting.
    [Show full text]
  • I + I²C = I3C, What’S Hiding in This Additional
    ELC 2018 I + I²C = I3C, what’s hiding in this additional ’I’ Boris Brezillon [email protected] © Copyright 2004-2018, Bootlin. Creative Commons BY-SA 3.0 license. Formerly Free Electrons Corrections, suggestions, contributions and translations are welcome! - Kernel, drivers and embedded Linux - Development, consulting, training and support - https://bootlin.com 1/46 Boris Brezillon I Embedded Linux engineer and trainer at Bootlin I Embedded Linux development: kernel and driver development, system integration, boot time and power consumption optimization, consulting, etc. I Embedded Linux, Linux driver development, Yocto Project / OpenEmbedded and Buildroot training courses, with materials freely available under a Creative Commons license. I https://bootlin.com I Contributions I Maintainer of the MTD subsystem I Kernel support for various ARM SoCs I Submitted RFCs for an I3C subsystem I Living in Toulouse, south west of France - Kernel, drivers and embedded Linux - Development, consulting, training and support - https://bootlin.com 2/46 ’I’ like in ... I I²C == Inter Integrated Circuit I I3C == Improved Inter Integrated Circuit I If it’s improved, it’s obviously better - Kernel, drivers and embedded Linux - Development, consulting, training and support - https://bootlin.com 3/46 Questions? Suggestions? Comments? Boris Brezillon [email protected] Slides under CC-BY-SA 3.0 https://bootlin.com/pub/conferences/2018/elc/bbrezillon-i3c/ - Kernel, drivers and embedded Linux - Development, consulting, training and support - https://bootlin.com
    [Show full text]
  • 100BASE-T1 Automotive Ethernet I3C 프로토콜 어날라이저/엑서사이저
    100BASE-T1 Automotive Ethernet I3C 프로토콜 어날라이저/엑서사이저 (주)탐시스텍 1 Agenda About Prodigy Technovations Trends & Overview of Automotive In-vehicle Bus Network Automotive Ethernet Industry Needs Introduction to PGY-100BASET1-PA Demo of PGY-100BASET1-PA Overview of I3C interface Introduction to PGY-I3C-EX-PD Demo of PGY-I3C-EX-PD 2 www.tamsystech.com Prodigy Technovations Founded in 2009 with software application for Tektronix Oscilloscope Hardware based Protocol Analyzer launched in 2015 Protocol Analyzer – eMMC, SD, SDIO – UFS3.1 – 100BaseT1 Automotive Ethernet – I3C, RFFE, SPMI Exerciser and Protocol Analyser – 10 Channel Logic Analyser with 1GS/Sec, I2C, SPI and UART Trigger and decode – I2C, SM Bus, SPI Exerciser and Protocol Analyzer Tektronix Oscilloscope based Electrical Validation and Protocol decode Software – I2C, SPI, UART, eMMC, SD, SDIO, QSPI, I3C, SPMI, RFFE, UFS, UniPRO, HDMI, MHL, USB2.0/3.0, 3.1Gen2, I2S, SVID, JTAG, 3 www.tamsystech.com Mainstream Automotive In-Vehicle Networking Electronic Control Units (ECUs) are Embedded System devices which control and monitor cars ECUs are interconnected using LIN, CAN, CAN FD, FlexRay and MOST Interface Modern Car has 75+ ECU. 4 www.tamsystech.com Current In-Vehicle Network Bus Local Interconnect Network (LIN) Bus – Low cost , Low speed 19.2 Kbps ,Single Copper Cable , Easy to implement Controller Area Network (CAN) Bus – The most dominant ,most common and popular vehicle network – Many variants for different speed, Max Speed 15 Mbps – Single Twisted Pair cable , Its plug
    [Show full text]
  • National Science Foundation Cri Workshop
    NATIONAL SCIENCE FOUNDATION Division of Computer and Network Systems CISE Computing Research Infrastructure CRI WORKSHOP SNOWBIRD UTAH JUNE 23-25, 2006 NATIONAL SCIENCE FOUNDATION Division of Computer and Network Systems CISE Computing Research Infrastructure CRI-WORKSHOP PROGRAM ORGANIZATION LOGISTICS Rita Rodriguez, CISE, NSF Dana Neill Steve Mahaney, CISE, NSF Computing Research Association Malek Adjouadi, FIU INVITED SPEAKERS Peter Freeman, Assistant Director CISE, NSF Deborah Crawford, Deputy Assistant Director, CISE, NSF PANELS CISE and the Global Implications: Larry Peterson, Princeton; David Novick, UTEP; Patrick Crowley, Washington U. St. Louis; Ram Dantu, U. of North Texas; Debby Cheng, Michigan State U.; and Bryant York, Portland State U. The GENI Program Guru Parulkar, GENI Program Director, CISE, NSF The Industry/University Cooperative Research Centers (I/UCRCs) Alex Schwarzkopf, Program Director, NSF, Division of Eng Education & Centers Sayfe Kiaei, Arizona State University, Director of Connection One and WINTech. ORGANIZATION OF PROCEEDINGS PHOTOS ON THE COVER PAGE Malek Adjouadi with thanks to the FIU-CATE Courtesy of the Cliff Lodge students Magno Guillen and Javier Delgado. Snowbird Ski & Summer Resort WITH THANKS To all of the investigators, presenters and participants of this NSF Workshop. SNOWBIRD UTAH JUNE 23-25, 2006 . NATIONAL SCIENCE FOUNDATION Division of Computer and Network Systems CISE Computing Research Infrastructure WORKSHOP - AGENDA Friday: June 23 Registration: 4:00 PM – 6:00PM Reception: 6:00 PM Dinner: 7:00 PM Saturday: June 24 7:30 - 8:00 Breakfast 8:00 - 8:20 Welcome Steve Mahaney, CISE/CNS Program Director, NSF Rita Rodriguez, CISE/CNS Program Director, NSF Malek Adjouadi, Florida International University 8:20 – 10:20 Session I: First-Year Awards Sabharwal, Ashutosh Rice University Shieber, Stuart Harvard University Callan, Jamie Carnegie Mellon University Manikopoulos, Constantine Foundation @ NJIT Chandra, Namas Florida A&M University Raju, G.V.S.
    [Show full text]
  • UC Berkeley UC Berkeley Electronic Theses and Dissertations
    UC Berkeley UC Berkeley Electronic Theses and Dissertations Title The Design &amp; Implementation of Modular Smart Dust Permalink https://escholarship.org/uc/item/51p6s7zb Author Pannuto, Patrick Publication Date 2020 Peer reviewed|Thesis/dissertation eScholarship.org Powered by the California Digital Library University of California The Design & Implementation of Modular Smart Dust by Patrick William Pannuto A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering { Electrical Engineering and Computer Science in the Graduate Division of the University of California, Berkeley Committee in charge: Associate Professor Prabal K. Dutta, Chair Professor Kristofer S. J. Pister Professor David E. Culler Taisei Professor Khalid M. Mosalam Fall 2020 The Design & Implementation of Modular Smart Dust Copyright 2020 by Patrick William Pannuto 1 Abstract The Design & Implementation of Modular Smart Dust by Patrick William Pannuto Doctor of Philosophy in Engineering { Electrical Engineering and Computer Science University of California, Berkeley Associate Professor Prabal K. Dutta, Chair Advancements across the computing stack now allow the realization of self-contained, sensing, computing, and communication devices in less than a cubic millimeter of volume|Smart Dust. Today's millimeter-scale systems are often one-offs, however. They are built to prove they can be built or for one particular application, but they are not yet so numerous and diverse to satisfy the vision of ubiquitous, ambient intelligence. This work aims to identify and address challenges in the move from tens to tens of millions of Smart Dust computing systems. The core contribution of this dissertation is bringing modularity to the millimeter-scale computing class.
    [Show full text]