Introduction
►Purpose • This course describes Freescale’s new 32-bit microcontroller: the Version 1 ColdFire core. ►Objectives • Explain the ColdFire family • Describe the features of the V1 ColdFire core • Explain the architecture, debug architecture, and microarchitecture of the V1 ColdFire core. ►Content • 36 pages • 3 questions ►Learning Time •60 minutes
1
Welcome to the “V1 ColdFire core” course, one of an exciting series of courses offered by Freescale. This course describes the details on Freescale’s new, ground breaking, 32-bit microcontroller, the Version 1 ColdFire core. The V1 ColdFire core was developed as part of the controller continuum. It introduces several exciting new features that place it at the forefront of a new era of compatibility between 8- and 32-bit processors.
1 Freescale Controller Continuum The Freescale Controller Continuum is our roadmap for ColdFire V4 8-bit and 32-bit compatibility ColdFire V3
ColdFire V2 32-bit ColdFire V1 FlexisFlexisTMTM TheThe ControllerController HCS08 core ContinuumContinuum “Connection“Connection Point”Point” RS08 core 8-bit
2
Freescale is redefining compatibility for the industry with our Controller Continuum. The Freescale Controller Continuum provides stepwise compatibility for an easy migration path up or down the performance spectrum From the ultra-low-end RS08 to our highest-performance ColdFire® V4 devices.
The connection point on the Freescale Controller Continuum is the Flexis series of microcontrollers. This connection point is where complimentary families of S08 and V1 ColdFire cores share a common set of peripherals and development tools to deliver the ultimate in migration flexibility. Pin-for-pin compatibility between many Flexis devices allows controller exchanges without board redesign.
2 What is the Flexis™ Series?
► Hardware platform offers multiple configurations and performance levels
► Software platform allows software reinvestment and reduced design cycle
► Single development tool • 8-bit (S08) and 32-bit (CFV1)
► Common peripheral set • Allows software reuse between 8-bit and 32- bits
► Pin to Pin compatibility • Maximize hardware reuse when moving between 8- bit and 32-bit
► QE Family • High performing devices • ULP features and peripherals ADC Analog comparator Multiple communications options Timers On-chip, in-circuit emulation
3
Why does 8 to 32 bit compatibility matter? For the hardware platform, designers can now offer multiple configurations and performance levels of their products with a single hardware and board design. For the software platform, software re-investment and design cycle time are drastically reduced. Peripheral and tools compatibility makes the transition between 8-bit and 32-bit fast and simple.
Later in this course we will discuss in detail our first Flexis family, the QE128 duo. However, because they are general-purpose devices with all the key attributes of a Flexis family solution, we will begin with a review of the high-level features:
One feature is that the single development tool eases migration between 8-bit (S08) and 32-bit (CFV1). Another benefit is that the common peripheral set preserves allows software reuse between 8-bit and 32-bit. Also, pin compatibility - wherever practical - maximizes hardware reuse when moving between 8-bit and 32-bit.
The QE family features high performing devices, including our very first offering which uses the V1 ColdFire core. It also includes ultra low power features and peripherals, such as an Analog-to-Digital Converter, analog comparator, multiple communications options, timers, and on-chip in-circuit emulation.
3 Flexis Series Compatible Roadmap
ColdFire® ® ColdFire General Purpose Ultra-low power ColdFire® S08 ColdFire® LCD Controller USB Enabled Colors Indicate ColdFire® Pin/Peripheral Industrial Application Compatibility S08 Controller General Purpose Ultra-low power S08 LCD Controller
S08 S08 Industrial Application USB Enabled Controller
2007 2008 2009
4
Next, let's consider the initial product offerings planned for the Flexis Roadmap. Freescale currently has plans for 4 sets of duo devices based on the S08 and V1 ColdFire cores.
First, we have the QE128 family, which provides general-purpose, ultra-low power devices. Later, we will be introducing devices that are enabled for USB and LCD applications and a pair of products targeted as an industrial application controller. We will also be developing additional duo devices targeted for other application spaces over time.
Before we dive into any more details on the V1 core, let's step back and briefly review the ColdFire Family of embedded processors.
4 ColdFire Family Summary
► Compatible family of processor cores architected for SoC and reuse • 100% synthesizable and technology-independent designs since inception in 1995 • DFT emphasis for easy SoC test • Strong embedded debug architecture Common developer tool set used for standard products + customer SoC designs ► Family of cores, software compatible with M68000 family legacy • Five generations available today covering a wide price/performance range • Generations of microarchitectures are named “versions” (Vx = CFx) – V1,V2,V3,… • Five generations have provided a 36.6x performance increase in 11 years ► CF1Core developed as the “connection point” in FSL’s Controller Continuum • Absolute minimal implementation for low-end MCU configurations ► Configurable designs: Options in cost / performance / function • MCU & MPU implementations, options on cache, local memory + {E}MAC, FPU, MMU ► Compatible family of platforms combining core + integrated peripherals • CFxCore, AXBS, DMA2, INTC, FlexBus, FEC, SDRAMC, ColdFire legacy peripherals • CoProcessor interface supports acceleration at instruction- or function-level, e.g., CAU
5
This slide provides a concise 1-page summary of the ColdFire family. Let's consider each of the major attributes of this processor family.
From its inception, ColdFire has been designed to provide a compatible family of processor cores that are architected for system-on-a-chip design flows and reuse. The entire family has been 100% synthesizable since its inception in 1995. The cores use a standard rising-edge D flip-flop implementation which is design-for-test friendly and easily adaptable to a wide range of process technologies. ColdFire has always had a strong embedded debug architecture which allows common development tools to be used for Freescale products as well as customer-specific designs.
The ColdFire family of cores is compatible with the 68K legacy. Today, we have five generations of microarchitectures covering a wide range of price/performance options. We call these different generations "versions", so we have V1, V2, etc. Over the past 11 years, the five generations of microarchitectures, coupled with process technology improvements, have provided a performance increase of almost 37 times its predecessor.
As we saw earlier, the V1 core was developed as the "connection point" for Flexis and targeted at an absolute minimal implementation for low-end 32-bit microcontroller configurations.
Another hallmark of the ColdFire family is configurable core designs, supporting options in cost, performance, and functionality. Today we have a variety of microcontroller and microprocessor devices with numerous cache and local memory sizes, and optional execution units like Multiply-Accumulate units (MAC and EMAC), floating-point units, virtual memory management, and so on.
All of these are available as required by different applications. In all cases, the intent of this configurability is to provide the system designer with access to the key hardware variables for optimizing device cost, performance and functionality.
Finally, the family has made use of a platform-based SoC design approach for many years, combining a ColdFire core with a platform containing a standard set of integrated peripherals. These include modules like crossbar switches, DMA units, interrupt controllers, external bus interfaces, Fast Ethernet Controllers, external SDRAM controllers and simple slave peripherals. The result is a consistent "look-and-feel" across all Freescale ColdFire products which minimizes software development time and maximizes hardware and software reuse.
Additionally, the core architecture includes support for a coprocessor interface to accelerate operations at the instruction- or function-level. An example is our Cryptographic Acceleration Unit, the CAU, which has been included on a number of devices. The CAU provides a significant performance boost to a number of security algorithms popular today.
5 V1 ColdFire Core
►V1 ColdFire Core Architecture • Supports ISA Revision C (ISA_C) • Same addressing modes, instruction definitions ty ili tib V4 Core • Provides upward compatibility to other ColdFire cores a p m ►V1 ColdFire microarchitecture Advantages o C e V3 Core • 2-stage instruction fetch and execution pipelines d • 32-bit local bus for tightly-coupled memories Co rd a V2 Core Large linear memory address space w p On-chip RAM and flash reduce memory U costs and complexity V1 Core • Standardized bus to S08 peripherals • Up to 12x performance improvement over S08 products ►Updated Debug Interface • S08 single-pin BDM interface for pin compatibility • Implements a buffer for BDM-readable trace
6
Now, let's turn our attention to the V1 ColdFire core. So what makes up the new V1 core? It is essentially a simplified version of the V2 ColdFire core, but with several very important enhancements that are targeted squarely at its role as the Flexis connection point.
First, the V1 core supports instruction set architecture revision C, the most current definition. This means that it retains the same addressing modes and instruction definitions shared by other ColdFire core architectures. The same programming model and compiler conventions are used, ensuring designs have a compatible roadmap to higher performance.
Since the V1 core takes advantage of its ColdFire legacy, it offers many advantages over 8-bit products. It leverages the V2 pipeline structure, but does so with a minimum implementation cost for the smallest size and power dissipation. The pipelined instruction fetch and execution provide higher performance, while the tightly coupled 32-bit local memories allow for faster data access in a larger memory map. And by being able to use on-chip RAM and flash, there is no need for external memory, thus reducing development costs as well as memory complexity.
The design includes a standardized slave bus which connects to the S08 peripheral modules to allow pin-compatible devices, providing both hardware and software compatibility with the 8-bit devices. Relative performance varies widely based on the application, but we have measured up to 12x performance improvement with the V1 ColdFire core.
Finally, the "classic" ColdFire debug architecture has been updated to be compatible with the 1-pin S08 Background Debug Mode (or BDM) interface. We'll be reviewing the details of the V1 debug architecture later, but for now, let's just note that the new debug definition includes an on-chip buffer to support program trace. The buffer is written by the processor as it executes, and can be read out via the 1-pin BDM interface. In conjunction with emulator software, it can provide instruction- by-instruction program trace information for debugging.
The end result? Faster processing on a simplified memory scheme with the flexibility for operating systems and advanced applications, all supported by powerful development tools.
6 Question
► Which of these statements about the V1 ColdFire core are true? Select all that apply and then click Done.
A. It supports instruction set architecture revision C.
B. It includes a standardized slave bus which connects to the S08 peripheral modules to allow pin-compatible devices.
C. The pipelined instruction fetch and execution provide higher performance over 8-bit products.
D. It includes updated programming model and compiler conventions.
Done
7
Take a moment now to answer this question the V1 ColdFire core.
Correct.
The V1 core supports instruction set architecture revision C, the most current definition. The design includes a standardized slave bus which connects to the S08 peripheral modules to allow pin-compatible devices, providing both hardware and software compatibility with the 8-bit devices. The pipelined instruction fetch and execution provide higher performance over 8-bit products. The programming model and compiler conventions are identical to the ColdFire V2.
7 V1 ColdFire Core Features
Next, let's consider the key features of the V1 ColdFire core and 3 other related functions and how they come together in the QE128 Family.
8 V1 ColdFire Core Features
►Architecture • Variable-length RISC architecture and implementation • Supports Revision C of the ColdFire Instruction Set Architecture • Implementation contains 24-bit address and 32-bit data paths • Support for optional execute engines including integer divider, multiply- accumulate units (MAC, EMAC) and cryptography acceleration unit (CAU) ►Programming Model • Supports the standard ColdFire user programming model with 16 general- purpose, 32-bit data and address registers, PC and Condition Code Register • Simplified supervisor programming model adds status register, supervisor stack pointer, vector base register, and CPU configuration register ►Performance and Power • Up to 50 MHz core frequency in a low-voltage, low-power 0.25-micron process technology • 0.85 Dhrystone 2.1 MIPS per MHz performance when executing from flash, 1.05 DMIPS per MHz when executing from RAM • Aggressive clock gating reduces power dissipation
9
The V1 core is a variable-length RISC architecture and implementation, supporting Revision C of the ColdFire Instruction Set Architecture. The implementation includes 24-bit address and 32-bit data paths, and the core design optionally supports inclusion of various execute engines like the integer divider, multiply-accumulate engines (both the MAC or EMAC) and the cryptographic acceleration coprocessor.
The V1 programming model supports the standard ColdFire definition, which includes a user-mode model containing 16 general-purpose 32-bit data and address registers, a 32-bit program counter and an 8-bit Condition Code Register containing indicator flags reflecting the results of instruction execution. The supervisor-mode model adds the Status Register, another stack pointer, a vector base register used during exception processing and a CPU configuration register, which provides software control over a number of key hardware configuration variables.
In a low-voltage, low-power 0.25 micron process technology implementation, the result is a V1 ColdFire core that operates up to 50 MHz, and provides 0.85 to 1.05 Dhrystone 2.1 MIPS per MHz of performance with ultra-low power dissipation.
9 V1 ColdFire Core Debug Features
►Architecture • Supports Debug Revision B+ definition mapped into S08’s 1-pin BDM • Real-time debug capabilities Multiple hardware breakpoints (4 PC, address-pair with optional data) – Configurable into 1-, 2-level triggers – Programmable response: processor halt or debug interrupt • Program (and optional slave data) trace capabilities On-chip trace buffer captures 6-bit compressed processor status (PST), debug data (DDATA) packets Trace buffer readable via 1-pin BDM Hardware breakpoint registers can be used to start/stop recording Provides a snapshot of dynamic execution path when combined with application memory image ►Multiple ways to access debug programming model resources • 1-pin BDM interface • Privileged WDEBUG processor instruction
10
Next, let's consider the debug features included in the core in more detail.
The V1 core supports Revision B+ of the ColdFire debug architecture mapped into the S08's single-pin BDM interface. To support real-time debug, the core has multiple hardware breakpoint registers, including 4 program counter breakpoints, and a pair of address register breakpoints with an optional data breakpoint and mask. The breakpoint registers can be configured into either 1- or 2-level triggers, with the trigger response programmed to either halt the core or generate a special debug interrupt.
The V1 core supports program trace and optional slave bus data trace capabilities. An on-chip trace buffer captures 6-bit packets of compressed Processor Status information which details the instruction execution state and captured debug data information. The contents of the trace buffer is controlled by the processor and the breakpoint registers can be used to define when the buffer starts and stops recording.
The trace buffer can be retrieved using BDM commands and the 1-pin interface. In conjunction with an application memory image, the trace buffer contents provides a snapshot of the dynamic execution path of the processor. This is a necessary component of a highly-capable debug architecture.
Finally, all the debug programming model resources, including the breakpoint registers and trigger definition registers, are accessible via the 1-pin BDM interface or through a privileged WDEBUG core instruction. There is also a WDDATA core instruction that effectively provides a hardware "printf" mechanism where the application can write directly into the trace buffer to signal information useful for debugging and/or performance analysis.
10 “Rapid GPIO” Features
►Architecture • 16 bits of high-speed GPIO connected to the CPU’s local bus • Memory-mapped device • Data bits can be accessed directly or via alternate addresses Alternate addresses allow set, clear, toggle functions using simple writes without the need for read-modify-writes Bit-level control for data direction and enable registers • All references complete in a single data phase core cycle for zero wait- state response ►Performance • Toggle rates typically 1.5x – 3.5x faster than normal GPIO pins
11
Next up is a new function, which is targeted at improved performance of general-purpose input/output (GPIO) pins. These are often very important in these types of embedded applications.
V1 ColdFire core includes a "rapid GPIO" module which provides 16 bits of high-speed GPIO connected to the processor's high-speed local bus. This is a memory-mapped device. The data register bits can be accessed directly or via alternate addresses which support set, clear and toggle functions using simple store instructions. These do not need a read-modify- write sequence. The Rapid GPIO logic includes bit-level control for defining data direction and pin enables. All processor references complete in zero wait-states for maximum performance.
Performance studies have shown that the toggle rates for the Rapid GPIO signals are typically 1.5x - 3.5x faster than the "normal" GPIO pins.
11 Interrupt Controller Features
►Architecture • Peripheral-mapped slave module Programming model accessed via peripheral space Encoded 3-bit request level and vector continuously sent directly to CPU • Initial support for 30 I/O interrupt requests Plus 7 software interrupt requests (1 per level) • Interrupt request priorities exactly match the S08 • Fixed association between request and vector CF1_Vector_Number = 62 + S08_Vector_Number 2 requests may be remapped to the highest maskable level + priority • Support for software interrupt acknowledge cycles Can improve system performance ►Implementation • Follows standard CF_INTC programming model, but greatly simplified • Sparsely-populated implementation of 7 levels x 9 priorities IRQ matrix
12
Finally, let's consider the functionality provided by the V1 interrupt controller, known as the INTC.
This is a memory-mapped slave peripheral module that is accessed in the same way as all the other peripheral devices. The INTC continuously evaluates the state of all the interrupt request signals, prioritizes them, and sends an encoded 3-bit request level and vector number to the V1 processor. ColdFire supports 7 levels of interrupt requests and this controller evaluates, prioritizes and encodes the highest-priority request for the processor.
For the QE128 family, there is support for 30 device interrupt requests plus 7 software-settable requests, one per level.
The interrupt request priorities exactly match the definition of the corresponding S08 device within a given Flexis family.
The ColdFire vector number is always 62 larger than the equivalent S08 vector number. Additionally, up to 2 requests can be remapped under software control to become the highest-priority maskable interrupt sources.
The controller supports software interrupt acknowledge cycles, which can be used to improve system performance when there is a pending - but masked - interrupt request asserted near the end of a service routine.
The interrupt controller implementation generally follows the standard ColdFire module programming model definition, but it is greatly simplified. Effectively, it is an implementation of a sparsely-populated hardware matrix of interrupt requests, mapped into 7 levels x 9 priorities per level organization.
12 Introducing the QE128 Family 50MHz S08 or V1 ColdFire core 2x 2 2xSCI 25MHz bus frequency KBI 2xSPI 2xI C ACMP 1.8-3.6V operating range COP ColdFire® V1 Core 24 ch. ► Memory Selection S08 Peripherals 12-bit 3 16-bit • Up to 8K bytes RAM ADC timers • Up to 128K bytes flash S08
► Features Flash Memory 8KB • 2x SCI, 2x I2C, 2x SPI 128 KB SRAM • 2x KBI – 8 channels each • 16-bit timers: 1 x 6-ch, 2 x 3-ch • 12-bit 24 channel A-to-D converter Power ICE + Mgmt 70 ICS+ULP • 2 analog comparators BDM Control GPI/O OSC • Up to 70 general purpose I/O (PMC) • System integration (PLL, SW Watchdog) • Integrated 1-pin BDM interface S08QE Packages • Rapid I/O 80LQFP, 64LQFP, 48QFN, 44QFP, 32LQFP ► Ultra-Low Power ColdFire QE Packages • Internal Clock Source (ICS) • Vreg with fast start up and low regulation voltage 80LQFP, 64LQFP • Low power 32 kHz oscillator Temperature Range • Optimize clock tree and clock gating techniques -40C to 85C r1
13
So, let's examine how all the key features of the V1 ColdFire core and related functions are integrated into the initial Flexis devices. This is a high-level view of the Flexis QE family. Both devices offer up to 50 MHz of performance and an operating range of 1.8 to 3.6 volts, with either the S08 or V1 ColdFire core with memory capacities up to 8 Kbytes of RAM and up to 128 Kbytes of flash.
The 128K flash is great because it provides additional headroom for 8-bit devices. Other flash offerings from 64K all the way down to 8K will be offered for the 8-bit device.
There are common peripherals on chip such as the 2 Serial Communications Interface modules, 2 Serial Peripheral Interfaces and 2 I squared C modules, all of which are ideal for supporting flexible serial communication protocols. A 12-bit 24 channel Analog to Digital converter is a major differentiator of the devices, along with the 2 analog comparators and 3 timer modules. As we've been discussing, the 32-bit device also offers the same 1-pin BDM interface for access to the powerful system debug features.
The QE showcases new ultra low power technology. We will be addressing this topic in more detail shortly.
13 Slide 13 r1 remove pricing from slide r62259, 07/12/2007 V1 ColdFire Core Architecture
We will now continue our review of the V1 ColdFire core by focusing on architecture.
14 ColdFire Programming Model
►User Programming Model • 16 x 32-bit General Purpose Registers 8 Data Registers, D0-D7 8 Address Registers, A0-A7 • 32-bit Program Counter (PC) • 8-bit Conditional Code Register (CCR)
►Supervisor Programming Model • User programming model plus… Status Register (SR) Supervisor Stack Pointer (Other_A7) Vector Base Register (VBR) CPU Configuration Register (CPUCR)
15
Let's begin with a description of the core's programming model.
The ColdFire user programming model includes sixteen 32-bit general-purpose registers, split equally into 8 data registers and 8 address registers. There is a 32-bit program counter which defines the current instruction being executed and an 8-bit Condition Code Register, which contains indicator flags to record the results of a previous instruction’s execution. This includes flags to signal a negative result, zero, overflow and a carry out. These flags are used by conditional branch instructions to determine whether the branch should be taken or not.
The supervisor programming model includes all the user registers plus a status register, another stack pointer, a vector base register used during exception processing and a CPU configuration register, which provides software control of hardware configuration settings.
15 Instruction Set Architecture
►ColdFire ISA • Dyadic structure:
16
The ColdFire instruction set architecture, the ISA, defines a dyadic structure. This means that most instructions specify two source operands and a destination where one of the source identifiers is the same as the destination. Thus, instructions follow an "x = f(x,y)" type of expression where x is the destination and x and y are the source operands.
The instruction syntax is op dot size followed by effective address specifiers for the y and x source operands. Here, op defines the operation to be performed, size is the operand size,
ColdFire supports 4 sizes of integer operands: 1-bit data, 8-bit bytes, 16-bit words and 32-bit longwords.
Recall ColdFire is a variable-length instruction set, where the instruction length is either 16-, 32- or 48-bits. All instructions begin with a 16-bit operand word, which can then be optionally followed by one or two 16-bit extension words. The extension words are typically used to define signed displacements from base address pointers for memory accesses, immediate operands or absolute addresses.
16 ISA Addressing Modes
Addressing Mode Example Uses Register Direct Simplest register operations
Register Indirect Simplest data memory access Register Indirect with Postincrement, Popping or pushing data from stack, sequential Predecrement data accesses Register Indirect with Displacement Preferred “generic” data addressing mode Register Indirect with Scaled Index and Indexed data array accesses Displacement Program Counter (PC) Indirect with PC-relative data accesses for constants, strings, Displacement etc. PC Indirect with Scaled Index and PC-relative indexed data tables, e.g., C “switch()” Displacement statements Arbitrary code and all peripheral data accesses Absolute (direct-page, high-page addresses) Immediate Operations with constants
17
This table provides a summary of the effective addressing modes supported by ColdFire. These modes would typically define the effective address for operand y from the instruction syntax shown previously.
The addressing modes vary from simple specifiers of the general-purpose registers - "register direct" and immediate operands where the data value is included in the instruction itself - to modes which define a memory operand.
The simplest memory-referencing mode is "register indirect" where one of the address register defines the location of the memory operand.
Next, there are memory addressing modes which adjust the address register value based on the operand size. These are the postincrement and predecrement modes. They are useful for pushing or popping data from the stack or accessing sequential data.
“Register indirect with displacement" is a very heavily-used mode because it adds a base address register with a sign-extended 16-bit displacement contained in the extension word 1 to define the memory location being referenced. For the V1 ColdFire core, most data references to the on-chip RAM will typically use this addressing mode, where the base address register points into the RAM and then the displacements can provide positive or negative offsets from this pointer.
Next, there are indexed addressing modes that combine a base address register plus an index register (which may be scaled by a times 1, times 2, or times 4 factor) plus a sign-extended 8-bit displacement. This mode is often used for references of memory array variables.
There are two addressing modes that use the program counter instead of an address register to define a base memory location. The"PC indirect with displacement" is most often used on branch instructions or instructions that reference PC-relative constants, strings, etc.
There are two forms of absolute addressing modes. Here, the actual memory address is included in the extension words as part of the instruction. In one form, a 16-bit address is first sign-extended before being used (this is the absolute short form) and another mode defines the 32-bit address directly (this is the absolute long form). For the V1 core, the absolute short form is the preferred mode for referencing all the slave peripheral registers.
Finally, there is an immediate mode, where the actual operand itself is contained within the extension words as part of the instruction.
So, the addressing modes supported by ColdFire and inherited from its 68K legacy provide a powerful set of operators that facilitate the generation of efficient, small code, whether it is compiled or hand assembled.
17 ColdFire Exception Processing
Attribute S08 V1 ColdFire Core Architecture
32, 2-byte entries, fixed @ 100+ 4-byte entries, located at lower end of memory @ Vector Table upper end of memory reset, relocatable with VBR
2 for CPU + 30 for IRQs, reset More on Vectors 64 for CPU, 40-48 for IRQs, reset @ lowest address @ upper address
8-byte frame: F/V, SR, PC; General-purpose registers Exception 5-byte frame: CCR, A, X, PC (An, Dn) must be saved/restored by the exception Stack Frame handler Interrupt Levels 1 = f(CCR[I]) 7 = f(SR[I]) with automatic hardware support for nesting
Non-Maskable No Yes with Level 7 interrupts IRQ Support
Core-enforced No Level 7 is edge-sensitive, else level sensitive IRQ Sensitivity
Fixed priorities and vector assignments, plus assignments INTC Vectoring Fixed priorities & vector 2 IRQs can be remapped as the highest level 6 (non- maskable) requests Software IACK No Yes Exit Instruction RTI RTE
18
Here is a high-level comparison of the exception processing between an S08 and ColdFire. Recall exception processing represents an instruction stream discontinuity caused either by some type of program or system error, or an asynchronous event like an interrupt. Here are the attributes that make up exception processing.
First, we have the exception vector table containing pointers to the first instruction of the service routine. For the S08, there are 32 entries, each 2 bytes in size, fixed at the upper end of memory. For ColdFire, there is a 256-entry table with each entry being 4 bytes. For V1 implementations, only the first 100 or so vectors are actually used. The ColdFire table is based at address zero after reset, but can be relocated using the Vector Base Register.
Of the 32-entry S08 table, two are reserved for reset and the software call instruction, while the remaining 30 are available for interrupt requests. The reset vector is located at the highest memory address. For ColdFire, the first 64 vectors are reserved for reset and internal processor conditions, while the next 40-48 vectors are used by the interrupt requests. Here, the reset vector is located at the lowest address.
When the processor takes an exception, both the S08 and ColdFire create an "exception stack frame" in memory to record the context of the machine (at least partially) at the time of the event. For the S08, this is a 5-byte frame containing the 2-byte PC, and 1-byte versions of the CCR, A and X registers. For ColdFire, an 8-byte frame is created, storing the status register and program counter, along with format and exception vector information.
Note the general-purpose 32-bit registers are not included in this exception stack frame and must be saved and restored as required by the exception handler.
The S08 supports a single level of interrupts as a function of the I bit in the CCR: either interrupts are enabled or disabled. On the other hand, ColdFire supports 7 levels of interrupt requests with automatic hardware support of level nesting. The current level is defined by the 3-bit I field in the Status Register.
Next, the S08 does not support the notion of non-maskable interrupts, while ColdFire treats the highest priority, level 7, as non- maskable. In fact, the S08 core does not enforce any type of sensitivity on the interrupt requests, while ColdFire treats the non-maskable level 7s as edge-sensitive and the remaining ones are level-sensitive. Both the S08 and V1 ColdFire core support fixed interrupt request priorities and vector assignments. V1 ColdFire core also supports the ability to remap (through software) up to 2 interrupt requests to be the highest priority, maskable requests.
While the S08 did not support the notion of a software interrupt acknowledge (IACK), this system feature is supported by ColdFire and can improve overall system performance in environments with high interrupt rates.
Finally, each architecture has a specific instruction for exiting from an exception service routine and returning to the application: "return from interrupt" for the S08, "return from exception" for ColdFire.
18 ISA History
►In the beginning (of the 32-bit world) was the M68000…
• Each ISA revision fully FPU encompasses the previous one(s) to ISA_C preserve backward ISA_B compatibility
ISA_A • Non-overlapping areas MAC are meant to show the M68000 incremental ISA additions EMAC • Revision “sizes” are not to scale M68020
http://www.freescale.com/files/dsp/doc/ref_manual/CFPRM.pdf
19
Here is a pictorial history of the evolution of the ColdFire instruction set architecture.
In the beginning there was the 68000. One of the hallmarks of both the 68K and ColdFire families has been support for binary code compatibility across the various revisions of the ISAs. The original 68000 ISA was supplemented by extensions provided by the 68020 as shown by their respective concentric circles. In this figure, the non-overlapping areas show the incremental ISA additions. Note that the relative sizes are *not* to scale.
There have been 3 revisions of the ColdFire ISA: ISA Revision A, or simply ISA_A, _B and _C. In addition, there have been instruction set architectures associated with specific execution engines including the MAC, EMAC, and floating-point unit, the FPU.
The original ColdFire ISA_A was a proper subset of the 68000 plus selected features from the ‘020 extensions. It was targeted for compiled code with 32-bit integers as the dominant data type. As the first ColdFire devices reached the market, we received feedback for tool developers and users about ISA enhancements which could improve both performance and code density associated with applications which made extensive use of 8- and 16-bit data types.
As a result, when we defined ISA_B, these concerns where addressed and this revision included a number of operations from the original 68000 plus more '020 features and new instructions never part of the 68K definition.
ColdFire ISA_C added a small number of new instructions to better support certain types of bit handling . These were never included in the 68K.
The 68020 added floating-point operations. ColdFire implements a subset of this functionality as shown by the "FPU" circle. Finally, the MAC and EMAC instruction sets are unique to ColdFire and do not have any 68K heritage.
Recall the V1 ColdFire core supports ISA_C, the most current revision, as we wanted to include all the enhancements to better support 1-, 8- and 16-bit data types most efficiently.
The complete instruction set architecture definition is available in the ColdFire Programmer's Reference Manual, or PRM, which is available on the Freescale web site.
19 System Memory Map
►Fixed address memory map • Restricted to 24-bit address = 16 Mbyte space Shown as 32-bit value: 0x(ss)nn_nnnn where ss = {00,ff} ►Standardized map
Base Address Memory Allocated Size 0x(00)00_0000 Flash 8 Mbytes 0x(00)80_0000 RAM 4 Mbytes 0x(00)C0_0000 Rapid GPIO 16 bytes 0x(FF)FF_8000 Slave Peripherals 32 Kbytes
0x(FF)FF_8000 – 0x(FF)FF_807F Direct-page peripheral regs 0x(FF)FF_9800 – 0x(FF)FF_98FF High-page peripheral regs 0x(FF)FF_FFC0 – 0x(FF)FF_FFFF Interrupt controller regs
► Efficiently supports use of short-a5-relative addressing mode (d16,A5) for all data memory accesses and the use of xxx.w for all peripheral accesses to produce better code density and higher performance
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V1 ColdFire cores implement a fixed address map with a 24-bit address space. This provides a 16 MByte definition, which is sufficient for the devices targeted for this application space. Even though the address space is restricted to 24 bits, we still represent addresses as 32-bit values because there are still certain hardware structures that retain the full vector width. For all addresses, we show the upper byte in parentheses, where this byte is either 00 or all ones - FF.
The system address map is partitioned into 4 regions: flash, based at zero; RAM, based at hex 800,000; the rapid GPIO module, based at hex c00,000; and a 32 Kbyte region for all the slave peripherals. This is located at the upper end of the available memory space. Within the slave peripheral region, there are 3 sub-sections: the direct-page registers, the high-page registers, and the interrupt controller registers. The first two groups retain their naming convention from the S08, although for ColdFire, there are no differences in the access speeds, unlike the 8-bit devices.
As mentioned in the earlier discussion on addressing modes, the "register with displacement" form provides efficient support for all data RAM accesses. In many compilers, this uses address register 5, that is, A5, in a "small data area" implementation. Additionally, the use of the signed-extended 16-bit absolute short mode is preferred for peripheral references.
20 Question
True or false? The ColdFire user programming model includes sixteen 32- bit general-purpose registers, split equally into 8 data registers and 8 address registers. Click the correct answer and then click Done.
A)True
B)False
Done
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Please answer this question about the registers used by the V1 ColdFire core.
Correct!
The ColdFire user programming model includes sixteen 32-bit general-purpose registers, split equally into 8 data registers and 8 address registers. There is a 32-bit program counter which defines the current instruction being executed and an 8-bit Condition Code Register, which contains indicator flags to record the results of a previous instruction’s execution.
21 V1 ColdFire Core Debug Architecture
Now we will explore some of the details of the V1 ColdFire core debug architecture.
22 V1 ColdFire Core Debug Architecture
►The definition of the V1 debug is driven by the S08’s single-pin BDM interface ►It effects two areas of the classic ColdFire debug architecture: • The emulator interface into the V1 core is mapped into the S08’s BDM command structure using 8-bit packets • The processor’s real-time trace capabilities (PST/DDATA) are redefined to implement PST compression with the resulting data stream of 6-bit packets loaded into a BDM-mapped on-chip core trace buffer Classic ColdFire PST/DDATA information is output from the processor using dedicated pins (9 outputs: 4 for PST, 4 for DDATA, PSTCLK) For V1, there are no pins dedicated for this capability; rather the PST/DDATA stream is compressed and loaded into a 64-entry trace buffer that is mapped into the BDM-accessible debug registers ►Supports a V1 implementation of DEBUG_B+ functionality
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The definition of the V1 debug functionality was driven by pin compatibility with the S08's single-pin BDM interface. It impacted two areas of the "classic" ColdFire debug architecture.
First, the emulator interface into the V1 core has been remapped into the S08's BDM command structure, which uses 8-bit packets.
Second, the core's real-time trace capabilities, using Processor Status (known as PST) and Debug Data (known as DDATA), have been redefined to implement compression on the PST values. The resulting stream of 6-bit packets can be loaded into an on-chip trace buffer that is readable from BDM.
The classic ColdFire debug definition uses dedicated package pins to output the trace information. There are a minimum of 9 pins: 4 for PST, 4 for DDATA, and 1 for PST clock. For V1, there are no pins dedicated for this functionality. Instead, the stream of PST and DDATA values is compressed and loaded into a 64-entry trace buffer that is mapped into BDM-readable debug registers.
As mentioned earlier, the V1 implementation supports revision B+ of the debug architecture. This is primarily related to the number of available breakpoint registers.
23 Debug Architecture Comparison
Function Classic ColdFire V1 ColdFire Core BDM Pins 3 for BDM + 1 for BKPT_b 1 (BKGD) Command Structure 17-bit packets, full-duplex 8-bit packets, half-duplex
Speed 1 bit per < 1/5 fCPU 1 bit per 1/16 fBDC (fBDC < ½fCPU) R/W (Mem + CPU Regs + Same + cmds to retrieve Functionality Dbg Regs), Run/Halt control trace buffer Trace Pins 4 PST, 4 DDATA, 1 CLK None 4-bit packets from core, 6-bit packets from core Data Structure separate PST, DDATA Type included in packet Program trace + optional partial Same but loaded into on-chip Functionality data trace trace buffer, retrieved via BDM Real-time Debug 4 PC (+1 mask), 2 addr, Same + bkpt regs can be used to Breakpoint Registers 1 data (+ mask) start/stop trace buffer recording
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Here is a summary contrasting the capabilities of the "classic" ColdFire and V1 debug definitions. This table presents a matrix of information about the 3 basic areas of debug functionality: background debug mode, trace and real-time debug. It also describes the support provided by the classic definition and the V1 definition.
First, let's consider BDM. The classic definition requires 4 pins total for this function: 3 for the BDM serial interface and 1 for a breakpoint input. As you know, the V1 implementation is mapped into a single pin.
The classic BDM command structure uses 17 bit packets in a full-duplex mode of communication, while the V1 implementation uses the 8-bit packet size defined by the S08, operating in a half-duplex scheme.
Classic BDM can operate at speeds up to 1/5 of the CPU's frequency, while the single-pin interface is considerably slower. Each bit requires 16 clocks in the Background Debug Controller, which is typically operating at speeds less than or equal to half the CPU frequency.
The supported functionality is effectively the same: there are commands to read and write memory, CPU registers, debug registers, and commands for run and halt control of the MCU. Additionally, the V1 implementation includes commands to retrieve the contents of the trace buffer.
Next is trace. The classic implementation required a minimum of 9 pins for real-time trace, while the V1 implementation uses no pins.
The classic implementation uses separate 4-bit packets for processor status and debug data. In the V1 implementation, the PST compression requires the field width be expanded by 1 bit. And, because the PST and DDATA packets are intermixed, there is another bit defined as a "prefix" which identifies the packet type. The result is the trace buffer packet size is 6 bits.
The classic definition provides real-time program trace with optional partial data trace of peripheral references. The V1 implementation provides the same type of program with optional partial data trace, but because it's loaded into the buffer, it is no longer real-time information. The information must be retrieved "after the fact" using the single-pin BDM interface.
Finally, the available breakpoint register resources are the same for both implementations. In addition, the V1 definition allows the breakpoint registers to be used to specify the start and stop conditions associated with trace buffer recording.
24 V1 ColdFire Core microarchitecture
Let's now turn our attention of the V1 ColdFire core microarchitecture, which is the underlying hardware implementation.
25 V1 ColdFire Core Block Diagram
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Here is a high-level view of the hardware structure of the device, the core and the CPU. We will zoom in on each section on the following pages. This is a core-centric block diagram of a generic V1 ColdFire core. This figure shows the V1 core on the left, the attached local memory devices in the upper right and middle and the various slave peripherals in the lower right. The diagram clearly identifies the two major clock domains of the Flexis devices, with the high-speed CPU clock domain shaded and the lower-speed bus clock domain not shaded.
The CPU clock domain operates at a frequency that is 2x the speed of the bus clock domain. Notice the V1 core interfaces with a local bus controller that connects to all the high-speed local devices including the RAM, Rapid GPIO and flash memory. Although the core's interface to the flash array resides in the CPU domain, each flash read requires 2 CPU cycles to complete.
The core-to-flash interface includes speculation logic to minimize the effective access time exposed to the core for accesses from this non-volatile memory. The bus controller also includes a connection to the standardized slave peripheral bus. This bus controller implements the domain boundary bridging between the CPU and bus clock regions. The interrupt controller and the flash's programming model are accessed through the slave bus, as are the S08 peripherals on a given chip.
Finally, notice that the entire core and attached local memories reside in the CPU's clock domain except for the debug module's Background Debug Controller. The single-pin BDM interface, represented by the "Background Data" signal, can operate at two speeds, depending on a software-settable configuration bit. It can operate at the bus clock, that is, at 1/2 of the CPU frequency, or it can operate with a fixed 10 MHz clock, generated from on-chip clock generation logic.
Now we will zoom in on the V1 ColdFire core.
26 V1 ColdFire Core Block Diagram
V1 Core modules include:
► V1 ColdFire Core • IFP Instruction Fetch Pipeline • OEP Operand Execution Pipeline ► V1 ColdFire Core Debug • BDC Background Debug Controller • ColdFire BDM Background Debug Module • PST/DDATA Processor Status/Debug Data • RTD Real-Time Debug
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This figure shows only the V1 core. Note there are two major functional blocks within the core: the CPU and the debug module.
Within the CPU, the two independent and decoupled pipeline structures are shown: the Instruction Fetch Pipeline, the IFP, and the Operand Execution Pipeline, the OEP. The pipelines generate a single unified bus interface with the address bus and the read and write data buses shown on the right side of the figure. Notice the encoded interrupt level is input to the Operand Execution Pipeline and sourced from the interrupt controller. We'll dig deeper into the CPU on the next page.
The debug module consists of 4 sub-blocks. We've already mentioned the Background Debug Controller as the hardware which connects to the single-pin BDM interface. The BDC packages the serial commands and then passes them along to the ColdFire BDM module, which then controls the distribution and execution of the commands to the rest of the debug module and/or the processor.
The PST/DDATA module includes the PST compression logic and the actual trace buffer. It receives PST packets from the CPU and monitors the processor bus addresses and data values, capturing debug data packets as appropriate. Finally, the real-time debug (RTD) module includes the hardware breakpoint registers. It too monitors the processor's address and data buses so it can evaluate possible breakpoint triggers.
Now we will zoom in one more level to view the details of the V1 ColdFire core.
27 V1 ColdFire Core CPU Block Diagram
► Two independent, decoupled pipeline structures with a unified 32- bit bus interface • 2-stage Instruction Fetch Pipeline (IFP) • 2-stage Operand Execution Pipeline (OEP) • Decoupled by an instruction buffer, which serves as FIFO queue ► IFP stages • IAG Instruction address generation • IC Instruction fetch cycle • IB Instruction buffer (optional) ► OEP stages • Each stage has two functions depending on the instruction type • DSOC Decode & select/operand • AGEX Address generation/execute
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In this last hardware block diagram, we explore "under the hood" of the V1 Central Processor Unit. The two independent and decoupled pipelined structures are clearly shown: the 2-stage Instruction Fetch Pipeline and the 2-stage Operand Execution Pipeline, with the FIFO instruction buffer providing the decoupling between these structures. The two independent and decoupled pipelines are a feature of all ColdFire microarchitectures because they provide an excellent hardware structure for handling the variable-length instruction set architecture of the family.
The two stages of the IFP include an instruction address generation stage where the prefetch address is generated and sent onto the processor's local bus. This is followed by the instruction fetch cycle, when the instruction read data is typically returned to the CPU. As the read data is routed from the local bus back into this pipeline stage, it is loaded into the instruction buffer and can optionally be bypassed directly into the Operand Execution Pipeline.
The IFP prefetches instructions and attempts to keep the buffer full so that the OEP does not waste time waiting for operation or extension words for each instruction.
The Operand Execution Pipeline includes 2 stages, where each stage has two functions depending on the instruction type. It is based on a familiar 3- terminal compute engine model with a 2-ported register file feeding an ALU with the result written back into the register file. The first stage performs instruction decode and operand selection at certain times and serves as the operand fetch cycle at other times. The second stage of the OEP performs operand address generation with instruction execution as the other function of this stage.
For simple register-to-register instructions, their execution time is 1 CPU cycle. The first stage performs instruction decode and selects the operands from the register file which implements the sixteen 32-bit general-purpose registers. The second stage of the pipeline uses the two registered source operands and sends them to the arithmetic/logic unit (or a barrel shifter) to perform the actual execution of the instruction. At the end of this second stage, the new result is written back into the register file.
For embedded load instructions, which read an operand from memory and then operate on the data, the instruction passes through the OEP twice. During the first pass, the operands for the effective address calculation are accessed. In the second cycle, the ALU calculates the effective memory address. The operand address is driven onto the processor's local bus near the end of the pipeline stage. In the next cycle, the operand read data is typically returned to the processor as the OEP begins its second pass for the instruction's actual execution.
As the read data is returned in the operand cycle, the second source operand is accessed from the register file. In the final execution cycle in the second pipeline stage, the two registered source operands are fed to the ALU to perform the required operation with the result written back into the register file at the end of the cycle. Thus, the two passes through the 2-stage pipeline results in a basic execution time of 3 cycles for this class of instructions, where the 4th cycle occurs at the same time as the first cycle of the next instruction.
Load instructions are optimized to require only two cycles since there is no real "execute" function to be performed on this class of assignment operations. Store instructions require only a single pipelined cycle of execution time, while read-modify-writes generally require 3 cycles to complete.
The diagram shows OEP-to-IFP coupling on the left side of the figure - these connections are used by change-of-flow and branch instructions, where the OEP calculates a new instruction fetch address and then passes it back to the Instruction Fetch Pipeline.
This finishes our tour of the V1 ColdFire core microarchitecture details.
28 QE128 Power “Data Sheet”
Ultra-low-power run and wait modes MCF51QE128 MC9S08QE128 ► CPU and peripherals run with voltage regulator in low power mode ► Allows full functionality at reduced frequency Run Mode @ 2 MHz CPU / 2 mA 1 mA for lower power operation 1 MHz bus Clock gating ► Turn clocks off to unused peripherals Run Mode @ 50 MHz CPU 27 mA 11 mA ► Reduces overall run and wait mode current / 25 MHz bus Ultra-low-power internal regulator & oscillator ► Fast start up from stop modes, typically 6-7 Lower Power Run Mode 50 uA 22 uA usec @ 32 kHz CPU/16 kHz bus ► New low power external oscillator consumes less than 1 uA Stop 2 – Lowest power mode; partial power 370 nA 370 nA Ultra-low-power internal clock source & oscillator down of circuits ► Eliminates need for external clock source ► Supports low frequency operations which Stop 3 - Int. circuits lowers power in system loosely regulated; clocks 520nA 450 nA at low frequency Ultra-low-power real-time counter ► Use in run, wait and stop modes ► Use with low power oscillator, internal or Stop 3 - Wake Up Time 6 us 6 us external clock sources
Preliminary typical measurements, Vdd = 3V, Temp = 25C
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Here is a sampling of power metrics for S08 and the V1 ColdFire cores. The rich set of low-power modes from earlier S08 devices has been brought forward to the Flexis family with a number of additional enhancements. This table shows descriptions and metrics for the V1 ColdFire QE128 and the S08 QE128 cores.
The data table presents the current draw in a number of operating modes including run mode with CPU operation at 2 MHz and full-speed 50 MHz and low-power run mode with CPU operation at 32 kHz. It also shows Stop2 - the lowest power mode - with dissipation of 370 nanoamps for both devices, Stop3 - another low power mode - and finally, the wakeup time from exiting Stop3 as 6 microseconds for both devices.
As you can see, the QE128 Flexis family was designed for ultra-low power dissipation.
29 Performance + Ultra-Low Power
►Measured V1 Dhrystone 2.1 Performance Text Location CpuCycles/Inst DMIPS/MHz Flash 2.53 0.85 RAM 2.05 1.05
►The Ultra-Low Power 32-bit Solution • World-class mA/MIP rating for 32-bit devices • Faster wakeup time to respond to events more quickly • More low power modes • Run at lower power without going to sleep
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Next, let's consider the combination of 32-bit performance plus the ultra-low power dissipation we just discussed. Here is the measured V1 ColdFire Dhrystone 2.1 performance. This benchmark is often used to quote integer performance across a wide range of processors. Despite all its shortcomings, it remains a performance metric used by customers.
The V1 Dhrystone performance is quoted in the typical DMIPS per MHz for two configurations: one with the benchmark code in flash and another with the code mapped into the RAM. The 2-cycle flash access time reduces performance slightly versus the single-cycle RAM speed, but both configurations provide a sizable improvement - approximately an order of magnitude - over typical 8-bit devices.
The combination of the improved performance levels coupled with the advanced ultra-low power implementation provides a world-class milliamp per MIPS rating for 32-bit microcontrollers. When coupled with the faster wakeup times from the collection of low-power modes or the option of running in the new low-power run modes opens exciting opportunities on possible products and application spaces with the Flexis family.
30 Question
► Which of these statements about the ColdFire core microarchitecture are true? Select all that apply and then click Done. A. The two stages of the IFP include an instruction address generation stage where the prefetch address is generated and sent onto the processor's local bus. B. Instructions for embedded load instructions pass through the OEP three times. C. The 2-stage Instruction Fetch Pipeline and the 2-stage Operand Execution Pipeline are a feature of all ColdFire microarchitectures.
Done 31
Now, answer this last question about the ColdFire microarchitecture.
Correct.
The two stages of the IFP include an instruction address generation stage where the prefetch address is generated and sent onto the processor's local bus. For embedded load instructions the instruction passes through the OEP twice. The 2-stage Instruction Fetch Pipeline and the 2-stage Operand Execution Pipeline are a feature of all ColdFire microarchitectures because they provide an excellent hardware structure for handling the variable-length instruction set architecture of the family.
31 Applications
Let's now briefly turn our attention to applications that can be serviced by the Flexis family.
32 Enabling New Generation Products
Security Systems Home Health Monitoring Home Appliances
HVAC Control Home Automation
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The V1 ColdFire core was designed to be used by applications that have reached their performance limit on 8-bit processors but want to reduce the time to market for higher performance implementations. Some of these possible applications include security systems, health monitoring systems, home appliances, and many, many more. The V1 ColdFire core is also perfect for designers interested in achieving a low-cost and low-overhead link to future 32-bit designs.
33 Applications Medical Instrumentation Factory Automation Consumer • Portable health monitors • Motion controllers • Invisible pet fences • Home health monitoring • Machine vision • Electronic toys • Patient monitoring • Operator panels • Electronic keys and locks • Dialysis machines • Embedded computer boards • Thermostats • Cardiac rhythm management • I/O modules • Remote controls • Hearing analysis equipment • Industrial networking products • Cordless telephones • Powered beds • Process controllers • Digital cameras/camcorders • Infusion pumps • Measurement equipment • Personal care products (electric • Electric wheelchairs shavers, toothbrushes, etc.) • Laboratory equipment Fire/Security • Smoke/heat detectors HVAC and Building Control • Fire alarm sounders and control panels • Utility meters • CCTV cameras and control panels Point of Sale • Environmental & building automation • Security cameras • Card payment terminals • Gas boiler controls • Intruder alarm control panels • Handheld bar code scanners • Thermostats • Intruder alarm motion detectors • Stationary bar code scanners • Lamp ballast • Access control • Bar code printers • Air conditioners • Biometrics security systems • Automatic Teller Machines (ATMs) • Carbon dioxide detectors • Portable data collection terminals
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This is a more detailed enumeration of possible applications covering just a sampling of areas including medical instrumentation, factory automation, consumer, point-of-sale devices, fire and security, and building control.
34 Additional Learning Learn more at freescale.com/flexis ► Get Started—freescale.com/flexis • Documentation • CodeWarrior Development Studio for Microcontrollers 6.0 • EVBQE128 Evaluation Board $325 • DEMOQE128 Demo Board $99 • S08QE samples • V1 ColdFire Core QE samples ► Training and Support—freescale.com/flexis • Global Seminars and Workshop on Demand • Reference Designs • Low Power and Migration Application Notes • See a demonstration ► Freescale Controller Continuum— freescale.com/continuum • Learn about stepwise compatibility from RS08 to S08 to V1 ColdFire Core
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The Freescale Flexis QE series provides unprecedented compatibility between 8-bit and 32-bit with common pin-outs, peripherals and tools. More information is located at freescale.com/flexis which includes how to get started with samples, documentation and training. Our full ecosystem of hardware and software development tools makes migration between 8-bit and 32-bit quick and easy. All this is available at Freescale.com/flexis.
For those who would like personalized exposure to the Flexis QE family, a Global seminar series consisting of hands on training with the QE Flexis family is available. Workshop on Demand is also available for those who would like an in-depth overview on the QE family. In addition to these live sessions, we are hosting examples of reference designs and application notes that showcase our optimized ultra-low-power architecture that helps extend battery life in industrial applications.
Also, Freescale has the only Controller Continuum with stepwise compatibility from RS08 to S08 to ColdFire V5 controllers. You can learn more about our Controller Continuum at www.freescale.com/continuum.
Thank you for your interest in Freescale products!
35 Course Summary
►Review the ColdFire family ►Describe the features of the V1 ColdFire core, including: • Architecture • Debug architecture • microarchitecture
For more information, please visit our Web site: www.freescale.com/flexis
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This concludes the “V1 ColdFire core” course. In this course you learned about Freescale’s new, ground breaking, 32-bit microcontroller, the Version 1 ColdFire core. For more information about this device, including seminars, workshops, reference designs and application notes, please visit the Freescale web site.
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