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Introduction Introduction ►Purpose • This course describes Freescale’s new 32-bit microcontroller: the Version 1 ColdFire core. ►Objectives • Explain the ColdFire family • Describe the features of the V1 ColdFire core • Explain the architecture, debug architecture, and microarchitecture of the V1 ColdFire core. ►Content • 36 pages • 3 questions ►Learning Time •60 minutes 1 Welcome to the “V1 ColdFire core” course, one of an exciting series of courses offered by Freescale. This course describes the details on Freescale’s new, ground breaking, 32-bit microcontroller, the Version 1 ColdFire core. The V1 ColdFire core was developed as part of the controller continuum. It introduces several exciting new features that place it at the forefront of a new era of compatibility between 8- and 32-bit processors. 1 Freescale Controller Continuum The Freescale Controller Continuum is our roadmap for ColdFire V4 8-bit and 32-bit compatibility ColdFire V3 ColdFire V2 32-bit ColdFire V1 FlexisFlexisTMTM TheThe ControllerController HCS08 core ContinuumContinuum “Connection“Connection Point”Point” RS08 core 8-bit 2 Freescale is redefining compatibility for the industry with our Controller Continuum. The Freescale Controller Continuum provides stepwise compatibility for an easy migration path up or down the performance spectrum From the ultra-low-end RS08 to our highest-performance ColdFire® V4 devices. The connection point on the Freescale Controller Continuum is the Flexis series of microcontrollers. This connection point is where complimentary families of S08 and V1 ColdFire cores share a common set of peripherals and development tools to deliver the ultimate in migration flexibility. Pin-for-pin compatibility between many Flexis devices allows controller exchanges without board redesign. 2 What is the Flexis™ Series? ► Hardware platform offers multiple configurations and performance levels ► Software platform allows software reinvestment and reduced design cycle ► Single development tool • 8-bit (S08) and 32-bit (CFV1) ► Common peripheral set • Allows software reuse between 8-bit and 32- bits ► Pin to Pin compatibility • Maximize hardware reuse when moving between 8- bit and 32-bit ► QE Family • High performing devices • ULP features and peripherals ADC Analog comparator Multiple communications options Timers On-chip, in-circuit emulation 3 Why does 8 to 32 bit compatibility matter? For the hardware platform, designers can now offer multiple configurations and performance levels of their products with a single hardware and board design. For the software platform, software re-investment and design cycle time are drastically reduced. Peripheral and tools compatibility makes the transition between 8-bit and 32-bit fast and simple. Later in this course we will discuss in detail our first Flexis family, the QE128 duo. However, because they are general-purpose devices with all the key attributes of a Flexis family solution, we will begin with a review of the high-level features: One feature is that the single development tool eases migration between 8-bit (S08) and 32-bit (CFV1). Another benefit is that the common peripheral set preserves allows software reuse between 8-bit and 32-bit. Also, pin compatibility - wherever practical - maximizes hardware reuse when moving between 8-bit and 32-bit. The QE family features high performing devices, including our very first offering which uses the V1 ColdFire core. It also includes ultra low power features and peripherals, such as an Analog-to-Digital Converter, analog comparator, multiple communications options, timers, and on-chip in-circuit emulation. 3 Flexis Series Compatible Roadmap ColdFire® ® ColdFire General Purpose Ultra-low power ColdFire® S08 ColdFire® LCD Controller USB Enabled Colors Indicate ColdFire® Pin/Peripheral Industrial Application Compatibility S08 Controller General Purpose Ultra-low power S08 LCD Controller S08 S08 Industrial Application USB Enabled Controller 2007 2008 2009 4 Next, let's consider the initial product offerings planned for the Flexis Roadmap. Freescale currently has plans for 4 sets of duo devices based on the S08 and V1 ColdFire cores. First, we have the QE128 family, which provides general-purpose, ultra-low power devices. Later, we will be introducing devices that are enabled for USB and LCD applications and a pair of products targeted as an industrial application controller. We will also be developing additional duo devices targeted for other application spaces over time. Before we dive into any more details on the V1 core, let's step back and briefly review the ColdFire Family of embedded processors. 4 ColdFire Family Summary ► Compatible family of processor cores architected for SoC and reuse • 100% synthesizable and technology-independent designs since inception in 1995 • DFT emphasis for easy SoC test • Strong embedded debug architecture Common developer tool set used for standard products + customer SoC designs ► Family of cores, software compatible with M68000 family legacy • Five generations available today covering a wide price/performance range • Generations of microarchitectures are named “versions” (Vx = CFx) – V1,V2,V3,… • Five generations have provided a 36.6x performance increase in 11 years ► CF1Core developed as the “connection point” in FSL’s Controller Continuum • Absolute minimal implementation for low-end MCU configurations ► Configurable designs: Options in cost / performance / function • MCU & MPU implementations, options on cache, local memory + {E}MAC, FPU, MMU ► Compatible family of platforms combining core + integrated peripherals • CFxCore, AXBS, DMA2, INTC, FlexBus, FEC, SDRAMC, ColdFire legacy peripherals • CoProcessor interface supports acceleration at instruction- or function-level, e.g., CAU 5 This slide provides a concise 1-page summary of the ColdFire family. Let's consider each of the major attributes of this processor family. From its inception, ColdFire has been designed to provide a compatible family of processor cores that are architected for system-on-a-chip design flows and reuse. The entire family has been 100% synthesizable since its inception in 1995. The cores use a standard rising-edge D flip-flop implementation which is design-for-test friendly and easily adaptable to a wide range of process technologies. ColdFire has always had a strong embedded debug architecture which allows common development tools to be used for Freescale products as well as customer-specific designs. The ColdFire family of cores is compatible with the 68K legacy. Today, we have five generations of microarchitectures covering a wide range of price/performance options. We call these different generations "versions", so we have V1, V2, etc. Over the past 11 years, the five generations of microarchitectures, coupled with process technology improvements, have provided a performance increase of almost 37 times its predecessor. As we saw earlier, the V1 core was developed as the "connection point" for Flexis and targeted at an absolute minimal implementation for low-end 32-bit microcontroller configurations. Another hallmark of the ColdFire family is configurable core designs, supporting options in cost, performance, and functionality. Today we have a variety of microcontroller and microprocessor devices with numerous cache and local memory sizes, and optional execution units like Multiply-Accumulate units (MAC and EMAC), floating-point units, virtual memory management, and so on. All of these are available as required by different applications. In all cases, the intent of this configurability is to provide the system designer with access to the key hardware variables for optimizing device cost, performance and functionality. Finally, the family has made use of a platform-based SoC design approach for many years, combining a ColdFire core with a platform containing a standard set of integrated peripherals. These include modules like crossbar switches, DMA units, interrupt controllers, external bus interfaces, Fast Ethernet Controllers, external SDRAM controllers and simple slave peripherals. The result is a consistent "look-and-feel" across all Freescale ColdFire products which minimizes software development time and maximizes hardware and software reuse. Additionally, the core architecture includes support for a coprocessor interface to accelerate operations at the instruction- or function-level. An example is our Cryptographic Acceleration Unit, the CAU, which has been included on a number of devices. The CAU provides a significant performance boost to a number of security algorithms popular today. 5 V1 ColdFire Core ►V1 ColdFire Core Architecture • Supports ISA Revision C (ISA_C) • Same addressing modes, instruction definitions ty ili tib V4 Core • Provides upward compatibility to other ColdFire cores a p m ►V1 ColdFire microarchitecture Advantages o C e V3 Core • 2-stage instruction fetch and execution pipelines d • 32-bit local bus for tightly-coupled memories Co rd a V2 Core Large linear memory address space w p On-chip RAM and flash reduce memory U costs and complexity V1 Core • Standardized bus to S08 peripherals • Up to 12x performance improvement over S08 products ►Updated Debug Interface • S08 single-pin BDM interface for pin compatibility • Implements a buffer for BDM-readable trace 6 Now, let's turn our attention to the V1 ColdFire core. So what makes up the new V1 core? It is essentially a simplified version of the V2 ColdFire core, but with several very important enhancements that are targeted squarely at its role as the Flexis connection
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