ASIC = “Application Specific Integrated Circuit”

Total Page:16

File Type:pdf, Size:1020Kb

ASIC = “Application Specific Integrated Circuit” ASIC = “Application specific integrated circuit” CS 2630 Computer Organization Meeting 19: Building a MIPS processor Brandon Myers University of Iowa The goal: implement most of MIPS So far Implementing the addu instruction register file still need to: • support more than 1 Kind of arithmetic operation • feed the CPU with a program • support branches and load/store Next: we’ve discussed what is in this box, but we need to learn about the rest of what is needed for a MIPS processor Project 2-1: the stuff in this box Project 2-2: everything else Implementing the addu instruction register file How do we program the “addu machine”? Peer instruction Give the sequence of addu machine inputs to perform $t0 = $t1 + $t2 + $t3 a) 1st clock cycle: rd=8, rs=9, rt=10 2nd clock cycle: rd=8, rs=8, rt=11 b) 1st clock cycle: rd=0, rs=9, rt=10 2nd clock cycle: rd=8, rs=0, rt=0 3rd clock cycle: rd=0, rs=8, rt=11 4th clock cycle: rd=8, rs=0, rt=0 c) 1st clock cycle: rd=0, rs=10, rt=11 2nd clock cycle: rd=8, rs=0, rt=0 3rd clock cycle: rd=0, rs=8, rt=9 4th clock cycle: rd=8, rs=0, rt=0 d) 1st clock cycle: rd=9, rs=10, rt=11 2nd clock cycle: rd=8, rs=0, rt=0 How do we program the addu machine? • Example: 8 8 14 On each clocK cycle, we are allowed to change the inputs rd, rs, and rt to perform another addition. But, where do those inputs come from? mining difficulty year “the difficulty target is adjusted based on the networK's recent performance, with the aim of Keeping the average time between new blocKs at ten minutes. In this way the system automatically adapts to the total amount of mining power on the networK” wiKipedia.org/wiKi/Bitcoin citing Andreas M. Antonopoulos (April 2014). Mastering Bitcoin. Unlocking Digital Crypto-Currencies. O'Reilly Media. ISBN 978-1-4493-7404-4. https://en.wiKipedia.org/wiKi/Bitcoin http://cseweb.ucsd.edu/~mbtaylor/papers/bitcoin_taylor_cases_2013.pdf CS 2630 Computer Organization Meeting 20: Building a MIPS processor Brandon Myers University of Iowa But, where do those inputs come from? • the instruction memory recall the layout of bits in R-type instructions How do we Know which instruction we are on? How do we Know which instruction we are on? • Store the current address in a 32-bit register called the program counter (PC) • Add 4 each cycle to go to the next word (next instruction) The complete addu machine Architecture and microarchitecture Architecture Microarchitecture also Known as ISA, the programmer’s an implementation of the ISA interface we’ll examine at least two Kinds of it includes the things on the MIPS reference microarchitectures for MIPS sheet: 32 registers, PC, instructions and their • right now: a single-cycle design where an behavior (RTL) instruction executes in one clocK period • later: a pipelined design where an instruction taKes multiple clocK periods The complete addu machine But, how do we get data into the addu machine? All registers start with the value 0. Let’s modify the circuit to include addiu Peer instruction • Modify the processor so it also Knows how to execute both addiu and addu Assume you have a component called “control” that taKes a MIPS opcode as input and provides a 1-bit signal isAddiu as output. isAddiu = 0 if the opcode is 0x0 (the opcode for addu) isAddiu = 1 if the opcode is 0x9 (the opcode for addiu) opcode control isAddiu bonus: implement the inside of “control” Addu/addiu machine 1. LooK at RTL of addu and addiu. What are the differences? 2. Where do we get the immediate from? 3. Each difference in the RTL can be handled with a MUX Interesting points: there was a 2- cycle solution, too looKup “microcode” for more information about that Kind of design Project 2: MIPS processor • Project 2-1 is assigned • one submission per team • Project 2-1: ALU and register file and tests • Project 2-2: datapath and control path of pipelined MIPS processor, tests, and test programs ALU stands for Project 2-1: ALU arithmetic logic unit Notice that the output Equal is different from the Zero? signal from the textbooK and lecture examples Project 2-1: ALU Switch plays the same role as the signal ALU control in the textbooK. However, mind the differences! Do not bother building your own adder/shifter/comparator! You can use any built-in Logisim component. Project 2-1: testing the ALU You must use a Linux environment to run the tests. Many options for students using Windows computers: a) connect to instructional machines through ssh (using WinSCP) or through fastx.divms.uiowa.edu b) Use the lab machines directly c) Use a Virtual machine d) Use cygwin e) if Windows 10, then enable Ubuntu console For students using Linux or MacOSX computers: • use the terminal Ask for help early! There is no excuse to not run the tests. Project 2-1: The register file • An addressable memory with 2 read ports and 1 write port! • $0 must always hold 0 Inputs Read Register 1 5 The number of the register whose contents is read out to Read Data 1 Read Register 2 5 The number of the register whose contents is read out to Read Data 2 Write Register 5 The number for the register to be written at the rising edge of ClocK Write Data 32 The data to write to the register specified by Write Register Write Enable 1 If 1, then a register will be written at the rising edge of ClocK. If 0, no register will be written at the rising edge of ClocK. Clock 1 The clocK signal The “Debugging Outputs outputs” provide Name Bit width Description Read Data 1 32 The data read from the register specified by Read Register 1 access to some of Read Data 2 32 The data read from the register specified by Read Register 2 the internal state of $s0 Value 32 (Debugging output) the value stored in register $s0) $s1 Value 32 (Debugging output) the value stored in register $s1) the register file $s2 Value 32 (Debugging output) the value stored in register $s2) $ra Value 32 (Debugging output) the value stored in register $ra) $sp Value 32 (Debugging output) the value stored in register $sp) Project 2-1 If you cannot decide on a split of the worK, you can try • 1 person in charge of ALU • 1 person in charge of register file • 1 person in charge of creating tests This is just a way to organize the worK; every team member is responsible for ensuring the team completes the whole project. SO FAR NEXT Next steps • Add more instructions to our processor: • other R and I types (or, ori, subu) • load and store (lw, sw) • branches (beq/bne) • jumps (j, jr, jal) • How do we implement the control logic? Addu/addiu machine sign extend Using memory for data 32 DataIn DataOut 32 • Load word 32 ReadAddr Data memory • Store word 32 WriteAddr WrEnable 1. Draw the “Data Memory” on the right side of your processor 2. Using the RTL above, add circuitry that is sufficient for executing load word (lw). • Assume that you have a 1-bit control signal isLW (1 when instruction is a lw, 0 otherwise) 3. Using the RTL above, add circuitry that is sufficient for executing load word (sw). If you need a control signal, just picK a descriptive name. • Assume that you have a 1-bit control signal isSW (1 when instruction is a sw, 0 otherwise) Branch instructions PC behavior for non branch/jump instructions • beq PC <- PC + 4 1. Add new circuitry or identify existing circuitry used to implement the comparison R[$rs]=R[$rt] 2. Add circuitry to implement SignExt18b({imm,00}). 3. Notice the difference in what happens to the PC register. • Add circuitry to choose between what the next PC is. • Add a new control signal Branch=1 when instruction is a branch instruction, 0 otherwise. • Did you add a MUX? Add necessary logic to calculate its Select input. RTL from http://www-inst.eecs.berKeley.edu/~cs61c/resources/MIPS_help.html [31:26] Control [25:21] ALUOp WriteEnable Address [20:16] A A ALUResult WriteData ReadData1 result PC Instruction ALU ==Zero? ReadData2 Memory WriteAddress [15:10] zero B B Data ReadAddress1 ReadAddress2 + 4 [5:0] [15:0] How to control the ALU’s operation opcode switch (aKa, ALUControl) ALUOpSwitch ALUControl Unit funct A ALUResult ALU ==Zero? B Note that the textbooK has a slightly different design where the “main decoder” produces a signal, ALUOp, that tells the ALUDecoder some information based on only the Opcode DDCA, 2nd Ed When you just “don’t care” A “don’t care” is where you put an X in the truth table to indicate that it doesn’t matter if the bit is a 0 or a 1. X’s can drastically simplify the truth table and the resulting combinational logic circuit. Why? The person/tool simplifying the circuit can picK whether a 1 or 0 for the X maKes the circuit simpler. Example from your recent experience... “What should happen to the Soda Machine FSM when Dime and NicKel inputs are both 1 in the same clocK period?” • If our circuit’s behavior is unspecified for a certain input case then we can put X’s into the truth table. You can also put X’s in the output column • an X in the output means that you don’t care what the output is for a certain input case • if you use Logisim’s logic analyzer, be aware that it allows for X’s in the output bits but not the input bits Do not confuse “don’t cares” (X’s in the truth table) with Logisim’s RED wires (i.e., wires where the value has X’s in it).
Recommended publications
  • Inside Intel® Core™ Microarchitecture Setting New Standards for Energy-Efficient Performance
    White Paper Inside Intel® Core™ Microarchitecture Setting New Standards for Energy-Efficient Performance Ofri Wechsler Intel Fellow, Mobility Group Director, Mobility Microprocessor Architecture Intel Corporation White Paper Inside Intel®Core™ Microarchitecture Introduction Introduction 2 The Intel® Core™ microarchitecture is a new foundation for Intel®Core™ Microarchitecture Design Goals 3 Intel® architecture-based desktop, mobile, and mainstream server multi-core processors. This state-of-the-art multi-core optimized Delivering Energy-Efficient Performance 4 and power-efficient microarchitecture is designed to deliver Intel®Core™ Microarchitecture Innovations 5 increased performance and performance-per-watt—thus increasing Intel® Wide Dynamic Execution 6 overall energy efficiency. This new microarchitecture extends the energy efficient philosophy first delivered in Intel's mobile Intel® Intelligent Power Capability 8 microarchitecture found in the Intel® Pentium® M processor, and Intel® Advanced Smart Cache 8 greatly enhances it with many new and leading edge microar- Intel® Smart Memory Access 9 chitectural innovations as well as existing Intel NetBurst® microarchitecture features. What’s more, it incorporates many Intel® Advanced Digital Media Boost 10 new and significant innovations designed to optimize the Intel®Core™ Microarchitecture and Software 11 power, performance, and scalability of multi-core processors. Summary 12 The Intel Core microarchitecture shows Intel’s continued Learn More 12 innovation by delivering both greater energy efficiency Author Biographies 12 and compute capability required for the new workloads and usage models now making their way across computing. With its higher performance and low power, the new Intel Core microarchitecture will be the basis for many new solutions and form factors. In the home, these include higher performing, ultra-quiet, sleek and low-power computer designs, and new advances in more sophisticated, user-friendly entertainment systems.
    [Show full text]
  • Design and Evaluation of a Clock Multiplexing Circuit for the SSRL Booster Accelerator Timing System
    SLAC-TN-15-018 Design and Evaluation of a Clock Multiplexing Circuit for the SSRL Booster Accelerator Timing System Million Araya† August 21, 2015 Seattle Central Community College, Seattle, WA CCI Program, SLAC National Accelerator Laboratory SPEAR3 is a 234 m circular storage ring at SLAC’s synchrotron radiation facility (SSRL) in which a 3 GeV electron beam is stored for user access. Typically the electron beam decays with a time constant of approximately 10hr due to electron lose. In order to replenish the lost electrons, a booster synchrotron is used to accelerate fresh electrons up to 3GeV for injection into SPEAR3. In order to maintain a constant electron beam current of 500mA, the injection process occurs at 5 minute intervals. At these times the booster synchrotron accelerates electrons for injection at a 10Hz rate. A 10Hz 'injection ready' clock pulse train is generated when the booster synchrotron is operating. Between injection intervals-where the booster is not running and hence the 10 Hz ‘injection ready’ signal is not present-a 10Hz clock is derived from the power line supplied by Pacific Gas and Electric (PG&E) to keep track of the injection timing. For this project I constructed a multiplexing circuit to 'switch' between the booster synchrotron 'injection ready' clock signal and PG&E based clock signal. The circuit uses digital IC components and is capable of making glitch-free transitions between the two clocks. This report details construction of a prototype multiplexing circuit including test results and suggests improvement opportunities for the final design. I. Introduction The ultimate purpose of a synchrotron radiation facility is to generate stable, high-power beams of light spanning from the Infrared to x-ray portion of the electromagnetic spectrum.
    [Show full text]
  • POWER-AWARE MICROARCHITECTURE: Design and Modeling Challenges for Next-Generation Microprocessors
    POWER-AWARE MICROARCHITECTURE: Design and Modeling Challenges for Next-Generation Microprocessors THE ABILITY TO ESTIMATE POWER CONSUMPTION DURING EARLY-STAGE DEFINITION AND TRADE-OFF STUDIES IS A KEY NEW METHODOLOGY ENHANCEMENT. OPPORTUNITIES FOR SAVING POWER CAN BE EXPOSED VIA MICROARCHITECTURE-LEVEL MODELING, PARTICULARLY THROUGH CLOCK- GATING AND DYNAMIC ADAPTATION. Power dissipation limits have Thus far, most of the work done in the area David M. Brooks emerged as a major constraint in the design of high-level power estimation has been focused of microprocessors. At the low end of the per- at the register-transfer-level (RTL) description Pradip Bose formance spectrum, namely in the world of in the processor design flow. Only recently have handheld and portable devices or systems, we seen a surge of interest in estimating power Stanley E. Schuster power has always dominated over perfor- at the microarchitecture definition stage, and mance (execution time) as the primary design specific work on power-efficient microarchi- Hans Jacobson issue. Battery life and system cost constraints tecture design has been reported.2-8 drive the design team to consider power over Here, we describe the approach of using Prabhakar N. Kudva performance in such a scenario. energy-enabled performance simulators in Increasingly, however, power is also a key early design. We examine some of the emerg- Alper Buyuktosunoglu design issue in the workstation and server mar- ing paradigms in processor design and com- kets (see Gowan et al.)1 In this high-end arena ment on their inherent power-performance John-David Wellman the increasing microarchitectural complexities, characteristics. clock frequencies, and die sizes push the chip- Victor Zyuban level—and hence the system-level—power Power-performance efficiency consumption to such levels that traditionally See the “Power-performance fundamentals” Manish Gupta air-cooled multiprocessor server boxes may box.
    [Show full text]
  • V850 Standby Modes
    Application Note V850 Standby Modes V850ES/SG2 V850ES/SJ2 Document No. U18825EE1V0AN00 Date Published June 2007 © NEC Electronics Corporation June 2007 Printed in Germany NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
    [Show full text]
  • Arithmetic and Logical Unit Design for Area Optimization for Microcontroller Amrut Anilrao Purohit 1,2 , Mohammed Riyaz Ahmed 2 and R
    et International Journal on Emerging Technologies 11 (2): 668-673(2020) ISSN No. (Print): 0975-8364 ISSN No. (Online): 2249-3255 Arithmetic and Logical Unit Design for Area Optimization for Microcontroller Amrut Anilrao Purohit 1,2 , Mohammed Riyaz Ahmed 2 and R. Venkata Siva Reddy 2 1Research Scholar, VTU Belagavi (Karnataka), India. 2School of Electronics and Communication Engineering, REVA University Bengaluru, (Karnataka), India. (Corresponding author: Amrut Anilrao Purohit) (Received 04 January 2020, Revised 02 March 2020, Accepted 03 March 2020) (Published by Research Trend, Website: www.researchtrend.net) ABSTRACT: Arithmetic and Logic Unit (ALU) can be understood with basic knowledge of digital electronics and any engineer will go through the details only once. The advantage of knowing ALU in detail is two- folded: firstly, programming of the processing device can be efficient and secondly, can design a new ALU architecture as per the various constraints of the use cases. The miniaturization of digital circuits can be achieved by either reducing the size of transistor (Moore’s law) or by optimizing the gate count of the circuit. The first has been explored extensively while the latter has been ignored which deals with the application of Boolean rules and requires sound knowledge of logic design. The ultimate outcome is to have an area optimized architecture/approach that optimizes the circuit at gate level. The design of ALU is for various processing devices varies with the device/system requirements. The area optimization places a significant role in the chip design. Here in this work, we have attempted to design an ALU which is area efficient while being loaded with additional functionality necessary for microcontrollers.
    [Show full text]
  • Generate a Clock Signal from a Crystal Oscillator
    www.ti.com Product Overview Generate a Clock Signal from a Crystal Oscillator Clocked Device U CLK Figure 1-1. Using an Unbuffered Inverter and Schmitt-Trigger Inverter to Generate a Clock Signal From a Crystal Oscillator Design Considerations • Drive crystal oscillators directly • Can be disabled with added logic • Allows for selectable system clocks with multiple crystals • Outputs a clean and reliable square wave • See the Use of the CMOS Unbuffered Inverter in Oscillator Circuits Application Report for more information about this use case. • Need additional assistance? Ask our engineers a question on the TI E2E™ logic support forum Recommended Parts Part Number Automotive Qualified VCC Range Features SN74LVC2GU04-Q1 ✓ 1.65 V — 5.5 V Dual unbuffered inverter SN74LVC2GU04 SN74AHC1GU04 2 V — 5.5 V Single unbuffered inverter SN74AUC1GU04 0.8 V — 2.7 V Single unbuffered inverter SN74LVC1G17-Q1 ✓ 1.65 V — 5.5 V Single Schmitt-trigger buffer SN74LVC1G17 For more devices, browse through the online parametric tool where you can sort by desired voltage, channel numbers, and other features. SCEA099 – OCTOBER 2020 Generate a Clock Signal from a Crystal Oscillator 1 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products.
    [Show full text]
  • Unit 8 : Microprocessor Architecture
    Unit 8 : Microprocessor Architecture Lesson 1 : Microcomputer Structure 1.1. Learning Objectives On completion of this lesson you will be able to : ♦ draw the block diagram of a simple computer ♦ understand the function of different units of a microcomputer ♦ learn the basic operation of microcomputer bus system. 1.2. Digital Computer A digital computer is a multipurpose, programmable machine that reads A digital computer is a binary instructions from its memory, accepts binary data as input and multipurpose, programmable processes data according to those instructions, and provides results as machine. output. 1.3. Basic Computer System Organization Every computer contains five essential parts or units. They are Basic computer system organization. i. the arithmetic logic unit (ALU) ii. the control unit iii. the memory unit iv. the input unit v. the output unit. 1.3.1. The Arithmetic and Logic Unit (ALU) The arithmetic and logic unit (ALU) is that part of the computer that The arithmetic and logic actually performs arithmetic and logical operations on data. All other unit (ALU) is that part of elements of the computer system - control unit, register, memory, I/O - the computer that actually are there mainly to bring data into the ALU to process and then to take performs arithmetic and the results back out. logical operations on data. An arithmetic and logic unit and, indeed, all electronic components in the computer are based on the use of simple digital logic devices that can store binary digits and perform simple Boolean logic operations. Data are presented to the ALU in registers. These registers are temporary storage locations within the CPU that are connected by signal paths of the ALU.
    [Show full text]
  • Hardware Architecture
    Hardware Architecture Components Computing Infrastructure Components Servers Clients LAN & WLAN Internet Connectivity Computation Software Storage Backup Integration is the Key ! Security Data Network Management Computer Today’s Computer Computer Model: Von Neumann Architecture Computer Model Input: keyboard, mouse, scanner, punch cards Processing: CPU executes the computer program Output: monitor, printer, fax machine Storage: hard drive, optical media, diskettes, magnetic tape Von Neumann architecture - Wiki Article (15 min YouTube Video) Components Computer Components Components Computer Components CPU Memory Hard Disk Mother Board CD/DVD Drives Adaptors Power Supply Display Keyboard Mouse Network Interface I/O ports CPU CPU CPU – Central Processing Unit (Microprocessor) consists of three parts: Control Unit • Execute programs/instructions: the machine language • Move data from one memory location to another • Communicate between other parts of a PC Arithmetic Logic Unit • Arithmetic operations: add, subtract, multiply, divide • Logic operations: and, or, xor • Floating point operations: real number manipulation Registers CPU Processor Architecture See How the CPU Works In One Lesson (20 min YouTube Video) CPU CPU CPU speed is influenced by several factors: Chip Manufacturing Technology: nm (2002: 130 nm, 2004: 90nm, 2006: 65 nm, 2008: 45nm, 2010:32nm, Latest is 22nm) Clock speed: Gigahertz (Typical : 2 – 3 GHz, Maximum 5.5 GHz) Front Side Bus: MHz (Typical: 1333MHz , 1666MHz) Word size : 32-bit or 64-bit word sizes Cache: Level 1 (64 KB per core), Level 2 (256 KB per core) caches on die. Now Level 3 (2 MB to 8 MB shared) cache also on die Instruction set size: X86 (CISC), RISC Microarchitecture: CPU Internal Architecture (Ivy Bridge, Haswell) Single Core/Multi Core Multi Threading Hyper Threading vs.
    [Show full text]
  • VLSI Digital Signal Processing
    CLOCKS Clocks in Digital Systems • Why are clocks and clocked memory registers needed inside digital systems? • Clocks pace the flow of data inside digital processors • The exact speed of data through circuits is impossible to predict accurately due to factors such as: – Fabrication process variations – Supply voltage variations “PVT variations” – Temperature variations – Countless parasitic effects (e.g., wire-to-wire capacitances) – Data-dependent variations (e.g., calculating 1 OR 1 = 1 requires a different delay than 1 OR 0 = 1) © B. Baas 322 Clocks in Digital Systems • Clocked memory elements slow down the fastest signals, wait until all signals have finished propagating through the combinational logic in the stage*, and then release them into the next stage simultaneously, controlled by the active edge of the clock signal • * This is why we care about clock only the single slowest signal in a block (max propagation delay) when finding the maximum clock frequency © B. Baas 323 Clocks in Digital Systems • All paths within a digital system consist of an input register, (optionally) followed by combinational logic, followed by an output register • Therefore: – If we can make this structure work under all conditions, we can build a robust digital system – We should analyze this structure carefully clock a combinational out b logic c_p1 c_p3 © B. Baas c_p2 324 Robust Clock Design • Edge-triggered memory elements (flip-flops) are generally more robust than level-sensitive memory elements (transparent latches) • Always follow these rules in this class, and for the most robust designs: 1. Only clock signals may connect to flip-flop or latch clock inputs • A simpler circuit may sometimes be possible if a logic signal is connected to a clock input, but do not do it for robustness • always @(posedge key) begin 2.
    [Show full text]
  • Tms320f280x, Tms320c280x, Tms320f2801x Digital Signal Processors
    TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802, TMS320F2809, TMS320F2808, TMS320F2806,TMS320C2801, TMS320F2802, TMS320F28016, TMS320F2801, TMS320F28015TMS320C2802, www.ti.com TMS320C2801,SPRS230P – OCTOBER TMS320F28016, 2003 – REVISED TMS320F28015 FEBRUARY 2021 SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021 TMS320F280x, TMS320C280x, TMS320F2801x digital signal processors 1 Features • Three 32-bit CPU timers • Enhanced control peripherals • High-performance static CMOS technology – Up to 16 PWM outputs – 100 MHz (10-ns cycle time) – Up to 6 HRPWM outputs with 150-ps MEP – 60 MHz (16.67-ns cycle time) resolution – Low-power (1.8-V core, 3.3-V I/O) design – Up to four capture inputs • JTAG boundary scan support – Up to two quadrature encoder interfaces – IEEE Standard 1149.1-1990 Standard Test – Up to six 32-bit/six 16-bit timers Access Port and Boundary Scan Architecture • Serial port peripherals • High-performance 32-bit CPU (TMS320C28x) – Up to 4 SPI modules – 16 × 16 and 32 × 32 MAC operations – Up to 2 SCI (UART) modules – 16 × 16 dual MAC – Up to 2 CAN modules – Harvard bus architecture – One Inter-Integrated-Circuit (I2C) bus – Atomic operations • 12-bit ADC, 16 channels – Fast interrupt response and processing – 2 × 8 channel input multiplexer – Unified memory programming model – Two sample-and-hold – Code-efficient (in C/C++ and Assembly) – Single/simultaneous conversions • On-chip memory – Fast conversion rate: – F2809: 128K × 16 flash, 18K × 16 SARAM 80 ns - 12.5 MSPS (F2809 only) F2808: 64K × 16
    [Show full text]
  • Phase Alignment of Asynchronous External
    PHASEALIGNMENTOFASYNCHRONOUSEXTERNALCLOCK CONTROLLABLEDEVICESTOPERIODICMASTERCONTROLSIGNALUSING THEPERIODICEVENTSYNCHRONIZATIONUNIT by CharlesNicholasOstrander Athesissubmittedinpartialfulfillment oftherequirementsforthedegree of MasterofScience in ElectricalEngineering MONTANASTATEUNIVERSITY Bozeman,Montana May2009 ©COPYRIGHT by CharlesNicholasOstrander 2009 AllRightsReserved ii APPROVAL ofathesissubmittedby CharlesNicholasOstrander Thisthesishasbeenreadbyeachmemberofthethesiscommitteeandhasbeen foundtobesatisfactoryregardingcontent,Englishusage,format,citation,bibliographic style,andconsistency,andisreadyforsubmissiontotheDivisionofGraduateEducation. Dr.BrockJ.LaMeres ApprovedfortheDepartmentElectricalEngineering Dr.RobertC.Maher ApprovedfortheDivisionofGraduateEducation Dr.CarlA.Fox iii STATEMENTOFPERMISSIONTOUSE Inpresentingthisthesisinpartialfulfillmentoftherequirementsfora master’sdegreeatMontanaStateUniversity,IagreethattheLibraryshallmakeit availabletoborrowersunderrulesoftheLibrary. IfIhaveindicatedmyintentiontocopyrightthisthesisbyincludinga copyrightnoticepage,copyingisallowableonlyforscholarlypurposes,consistentwith “fairuse”asprescribedintheU.S.CopyrightLaw.Requestsforpermissionforextended quotationfromorreproductionofthisthesisinwholeorinpartsmaybegranted onlybythecopyrightholder. CharlesNicholasOstrander May2009 iv TABLEOFCONTENTS 1.INTRODUCTION .......................................................................................................... 1
    [Show full text]
  • Microcontroller Serial Interfaces
    Microcontroller Serial Interfaces Dr. Francesco Conti [email protected] Microcontroller System Architecture Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU Example: STM32F101 MCU Microcontroller System Architecture Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU • Memory • RAM (from 512B to 256kB) • FLASH (from 512B to 1MB) Example: STM32F101 MCU Microcontroller System Architecture Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU • Memory • RAM (from 512B to 256kB) • FLASH (from 512B to 1MB) • Peripherals • DMA • Timer • Interfaces • Digital Interfaces • Analog Timer DMAs Example: STM32F101 MCU Microcontroller System Architecture Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU • Memory • RAM (from 512B to 256kB) • FLASH (from 512B to 1MB) • Peripherals • DMA • Timer • Interfaces • Digital • Analog • Interconnect Example: STM32F101 MCU • AHB system bus (ARM-based MCUs) • APB peripheral bus (ARM-based MCUs) Microcontroller System Architecture Each MCU (micro-controller unit) is characterized by: • Microprocessor • 8,16,32 bit architecture • Usually “simple” in-order microarchitecture, no FPU • Memory • RAM (from 512B to 256kB) • FLASH
    [Show full text]