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Intel 64 and IA-32 Architectures Optimization Reference Manual [PDF] Intel® 64 and IA-32 Architectures Optimization Reference Manual Order Number: 248966-033 June 2016 Intel technologies features and benefits depend on system configuration and may require enabled hardware, software, or service ac- tivation. Learn more at intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. Results have been estimated or simulated using internal Intel analysis or architecture simulation or modeling, and provided to you for informational purposes. Any differences in your system hardware, software or configuration may affect your actual performance. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or by visiting http://www.intel.com/design/literature.htm. Intel, the Intel logo, Intel Atom, Intel Core, Intel SpeedStep, MMX, Pentium, VTune, and Xeon are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. Copyright © 1997-2016, Intel Corporation. All Rights Reserved. CONTENTS PAGE CHAPTER 1 INTRODUCTION 1.1 TUNING YOUR APPLICATION. 1-1 1.2 ABOUT THIS MANUAL. 1-1 1.3 RELATED INFORMATION . 1-3 CHAPTER 2 INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES 2.1 THE SKYLAKE MICROARCHITECTURE. 2-2 2.1.1 The Front End . .2-3 2.1.2 The Out-of-Order Execution Engine . .2-3 2.1.3 Cache and Memory Subsystem . .2-5 2.2 THE HASWELL MICROARCHITECTURE . 2-6 2.2.1 The Front End . .2-7 2.2.2 The Out-of-Order Engine . .2-8 2.2.3 Execution Engine . .2-8 2.2.4 Cache and Memory Subsystem . 2-10 2.2.4.1 Load and Store Operation Enhancements . 2-11 2.2.5 The Haswell-E Microarchitecture. 2-11 2.2.6 The Broadwell Microarchitecture . 2-12 2.3 INTEL® MICROARCHITECTURE CODE NAME SANDY BRIDGE . 2-12 2.3.1 Intel® Microarchitecture Code Name Sandy Bridge Pipeline Overview . 2-13 2.3.2 The Front End . 2-14 2.3.2.1 Legacy Decode Pipeline . 2-15 2.3.2.2 Decoded ICache. 2-17 2.3.2.3 Branch Prediction. 2-18 2.3.2.4 Micro-op Queue and the Loop Stream Detector (LSD) . 2-18 2.3.3 The Out-of-Order Engine . 2-19 2.3.3.1 Renamer . 2-19 2.3.3.2 Scheduler . 2-20 2.3.4 The Execution Core . 2-20 2.3.5 Cache Hierarchy . 2-22 2.3.5.1 Load and Store Operation Overview . 2-22 2.3.5.2 L1 DCache. 2-23 2.3.5.3 Ring Interconnect and Last Level Cache . 2-27 2.3.5.4 Data Prefetching . 2-28 2.3.6 System Agent . 2-29 2.3.7 Intel® Microarchitecture Code Name Ivy Bridge . 2-30 2.4 INTEL® CORE™ MICROARCHITECTURE AND ENHANCED INTEL® CORE™ MICROARCHITECTURE . 2-30 2.4.1 Intel® Core™ Microarchitecture Pipeline Overview . 2-31 2.4.2 Front End . 2-32 2.4.2.1 Branch Prediction Unit . 2-33 2.4.2.2 Instruction Fetch Unit . 2-33 2.4.2.3 Instruction Queue (IQ). 2-34 2.4.2.4 Instruction Decode. 2-35 2.4.2.5 Stack Pointer Tracker . 2-35 2.4.2.6 Micro-fusion . ..
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