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Hardware Design I Chap. 10 Design of Microprocessor Outline z What is microprocessor? Hardware Design I Chap. 10 z Microprocessor from sequential machine Design of microprocessor viewpoint {Microprocessor and Neumann computer Computing Architecture Lab. {Memory hierarchy {Instruction set architecture Hajime Shimada z Microarchitecture of the microprocessor E-mail: [email protected] {Microarchitecture with sequential processing {Microarchitecture with pipelined processing 1 Computing Architecture Lab. Hajime Shimada Hardware Design I (Chap. 10) 2 What is microprocessor? Central Processing Unit (CPU) z LSI for processing data at the center of the z A nucleus of Neumann computer computer { Detail will be taught in later slide {Also, called “processor” z Sometimes, the word “microprocessor” denotes this z There are several type of microprocessors z By combining CPU with memories, disks, I/Os, we can create PC or server {Central Processing Unit (CPU) z Examples: Intel core i7, Fujitsu SPARC64 VII, AMD {Microcontroller Opteron, ... {Graphic accelerator {Other several accelerators Computing Architecture Lab. Computing Architecture Lab. Hajime Shimada Hardware Design I (Chap. 10) 3 Hajime Shimada Hardware Design I (Chap. 10) 4 Microcontroller Graphic accelerator z A processor used for control of electric devices z A processor used for processing graphic { Optimized for those use { Also called Graphic Processing Unit (GPU) z e.g. give high current drive ability to output pin to directly drive LED z Implement too many ALU to utilize parallelism z Many of them can organize computer with one chip { In graphic processing, usually, we can process each pixel { Implement memory hierarchy into them independently z Example: Renesus H8, Atmel AT91, Zilog Z80, ... { It also utilized for high parallelism arithmetic { Too many companies provide them z Examples: NVIDIA GeForce, AMD(ATI) Radeon, ... Computing Architecture Lab. Computing Architecture Lab. Hajime Shimada Hardware Design I (Chap. 10) 5 Hajime Shimada Hardware Design I (Chap. 10) 6 1 Other accelerators Outline z There’s several processor to accelerate data processing z What is microprocessor? which is not suitable to process with CPU or GPU z Microprocessor from sequential machine { But recently, GPU intrudes to this area viewpoint z Usually, it implements much ALU to supply high arithmetic performance {Microprocessor and Neumann computer z Example: ClearSpeed CSX, Ageia PhysiX, ... {Memory hierarchy {Instruction set architecture z Microarchitecture of the microprocessor {Microarchitecture with sequential processing {Microarchitecture with pipelined processing Computing Architecture Lab. Computing Architecture Lab. Hajime Shimada Hardware Design I (Chap. 10) 7 Hajime Shimada Hardware Design I (Chap. 10) 8 Microprocessor from sequential circuit Neumann computer viewpoint z We can abstract microprocessor with following z Neumann computer is current major organization sequential machine z Point of Neumann computer z Inputs { Instructions and data are placed in main memory { Programs (= instructions) { Instructions manipulate data of flip-flop and memories { Data for processing { We can apply different manipulation by different instruction z Outputs: Processed data Neumann computer Non-Neman computer z State: Register (and register file) Data before Instructions A hardware processing A hardware which apply Combinational Data before which apply operation Programs Processed processing fixed logic circuit notated in (=instructions) data operation Data after instruction Data after data for processing to data Register (and register file) processing to data processing Main memory Main memory Computing Architecture Lab. Clock Computing Architecture Lab. Hajime Shimada Hardware Design I (Chap. 10) 9 Hajime Shimada Hardware Design I (Chap. 10) 10 Advantages and disadvantages of Neumann computer and microprocessor Neumann computer z Advantages This hardware is Instructions A hardware a microprocessor { We don’t have to modify hardware between different data which apply Combinational processing Data before processing operation logic circuit z EDSAC(1949) is one of the early Neumann computer notated in z ENIAC have to change wire connection if it change processing Data after instruction { We can execute complicated processing with multiple processing to data Register Main memory (and instructions register file) z Disadvantages (Neumann bottleneck) z Microprocessor is a hardware which operate data processing in { Communication between processor and memory increases Neman computer { Slow memory drags down processor performance { Also called “processor” or “Central Processing Unit (CPU)” z How about non-Neumann computer? { It includes a part of main memory (see memory hierarchy) { It remains in some specific use (e.g. movie codec) z Hardware organization of the microprocessor differs between its purpose { It begins to reposition with reconfigurable hardware ->Chap. 9 { For server, for PC, for high performance embedded, for embedded, ... Computing Architecture Lab. Computing Architecture Lab. Hajime Shimada Hardware Design I (Chap. 10) 11 Hajime Shimada Hardware Design I (Chap. 10) 12 2 States in the microprocessor Inputs for the microprocessor z How we define states of sequential machine in the z There are two inputs of sequential machine in the processor? processor { Usually, we call it register { Instruction: must be defined if we design sequential machine z There are many types of registers { Data: don’t have to define them { Special purpose registers (SPR) z What’s instruction? z Program counter (PC): Denotes position of instruction which is executing { Series of bits: e.g. 00000000100001010100000000010000 z Flag register: Denotes carry generation, overflow, ... { Usually, we use assembly language to represent it { Global purpose registers (GPR) z A programming language which has one to one relationship to z Used for hold data before/after processing (work as a part of main instruction memory) z It defines operation relationship between registers and main z Also, used for intermediate data under arithmetic memory (in basic) z The organization of register differs between instruction z e.g. add R8, R4, R5 (GPR #8 = GPR #4 + GPR #5) set architectures Relationship between GPR and <-> 00000000100001010100000000010000 Introduce how to define it memory hierarchy is shown in later efficiency in later slide Computing Architecture Lab. Computing Architecture Lab. Hajime Shimada Hardware Design I (Chap. 10) 13 Hajime Shimada Hardware Design I (Chap. 10) 14 GPR and memory hierarchy (1/2) GPR and memory hierarchy (2/2) z In recent processors, the GPR becomes a part of main z We call “memory hierarchy” for those hierarchical memory { Including disk { Firstly the processor moves data from main memory to register { It also reduces performance degradation from slow device { Processor apply operation to the data in the register z Recently, number of hierarchy increasing because the { After operation, it write back data to main memory speed difference between devices is increasing z This organization effectively reduces workload for main Data Data memory Traditional transmission transmission memory { Assuming that we apply multiple operation to data Disk hierarchy Register Data Data memory Main transmission transmission SRAM SRAM Recent Disk memory Register Internal processor Main memory Main hierarchy Disk L2 cache L2 L1 cache L1 Register FF or SRAM DRAM HDD or SSD memory Main Computing Architecture Lab. Computing Architecture Lab. Hajime Shimada Hardware Design I (Chap. 10) 15 Hajime Shimada Hardware Design I (Chap. 10) 16 Instruction set architecture (ISA) Instruction encoding z To create sequential machine, we have to define format z Instruction is encoded to chunk of binary under ISA of inputs and internal state definition { Internal state: denoted by registers (for internal state) { e.g. add R8, R4, R5 (GPR #8 = GPR #4 + GPR #5) { Inputs: instructions <-> 00000000100001010100000000010000 z We usually call this definition as Instruction Set z In usual encoding, we give meaning into some chunk of Architecture (ISA) bits { Including systematic instruction construction method z By defining ISA carefully you can reduce { States (registers) R type op rs rt rd shift func { Combinational logics 31 26 21 16 11 6 0 I type op rs rt addr 31 26 21 16 0 Computing Architecture Lab. Computing Architecture Lab. Hajime Shimada Hardware Design I (Chap. 10) 17 Hajime Shimada Hardware Design I (Chap. 10) 18 3 Example of instruction encoding (1/3) Example of instruction encoding (2/3) z Example: Instruction encoding of MIPS z add R8, R4, R5 z Total length is 32-bit z It has meaning in several chunk of bits 000000 00100 00101 01000 no use 010000 { op: Type of operation (arithmetic, load, store, branch, ...) 31 26 21 16 11 6 0 { rs: Source operand 1 for arithmetic { Operation: R8 = R4 + R5 (add: addition) This difference { rt: Source operand 2 for arithmetic z sub R8, R4, R5 indicates different { rd: Destination operand for arithmetic (store arithmetic result) arithmetic { shift: Amount of shift { func: Type of arithmetic (supplemental for op) 000000 00100 00101 01000 no use 010010 { addr: Immediate value for arithmetic 31 26 21 16 11 6 0 R type op rs rt rd shift func { Operation: R8 = R4 - R5 (sub: subtract) 31 26 21 16 11 6 0 I type op rs rt addr 31 26 21 16 0 Computing Architecture Lab. Computing Architecture Lab. Hajime Shimada Hardware Design I (Chap. 10) 19 Hajime Shimada Hardware Design I (Chap. 10) 20 Example of instruction encoding (3/3) Short Exercise z lw R8, 8(R4) z
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