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US00941 1925B2

(12) United States Patent (10) Patent No.: US 9.411,925 B2 Meng (45) Date of Patent: Aug. 9, 2016

(54) SIMULTANEOUSLY VIEWING MULTI 7,865,857 B1 * 1/2011 Chopra ...... GO6F 17/5045 PARED SCHEMATIC AND LAYOUT 8,117,586 B2 2/2012 Sheng T16,119 WINDOWS ON 8,181,137 B2 * 52012 Uppiuri. GO6F 17/5022 (PCB) DESIGNSOFTWARE AND TOOLS T16,111 8,261.228 B1* 9/2012 Gopalakrishnan ... G06F 17/5036 (71) Applicant: Lenovo Solutions TO3/14 (Singapore) Pte. Ltd., Singapore (SG) 8,370,790 B2 2/2013 Sheng 8,397,194 B2 * 3/2013 Uppaluri ...... GO6F 17/5022 71.6/107 (72) Inventor: Jian Meng, Kanata (CA) 8,516,399 B2* 8/2013 Paris ...... GO6F 17,5081 T16, 136 (73) Assignee: Lenovo Enterprise Solutions 8,584,072 B1 * 1 1/2013 Gopalakrishnan ... G06F 17/5036 (Singapore) Pte. Ltd., Singapore (SG) T16,111 8,726.207 B2 * 5/2014 Jiang ...... GO6F 17/5068 c - r T16,110 ( ) Notice: Subject tO any disclaimer, the term of this 8,782.577 B2 ck 7/2O 14 Fischer ...... G06F 17,5068 patent is extended or adjusted under 35 T16,100 U.S.C. 154(b) by 87 days. 8,930,877 B1 * 1/2015 Krasnicki ...... GO6F 17/5036 T16, 136 (21) Appl. No.: 14/252,663 9,122,384 B1* 9/2015 Kohli ...... G06F 3/04842 Continued (22) Filed: Apr. 14, 2014 ( ) FOREIGN PATENT DOCUMENTS (65) Prior Publication Data US 2015/0294.060A1 Oct. 15, 2015 EP 193O824 6, 2008 OTHER PUBLICATIONS (51) Int. Cl. Kung et al., “A Finite-Difference Time-Domain (FDTD) Software G06F 17/50 (2006.01) for Simulation of Printed Circuit Board (PCB) Assembly.” Progress (52) U.S. Cl in Electromagnetics Research, Pier 50, 2005, pp. 299-335. CPC ...... G06F 17/5081 (2013.01); G06F 17/5068 Primary Examiner — Stacy Whitmore (2013.01) (74) Attorney, Agent, or Firm — Zilka-Kotab, PC (58) Field of Classification Search CPC ...... G06F 17/5068: G06F 17/5081 (57) ABSTRACT S. licati - - - - - file? - - - - - R 1 O 11 sh t 19, 122 A method according to one embodiment includes receiving a ee appl1cauon Ille Ior complete searcn n1Story. printed circuit board design in a memory; generating, using a (56) References Cited , multiple schematic windows of the printed circuit board design; generating, using the processor, multiple layout U.S. PATENT DOCUMENTS windows of the printed circuit board design; and outputting the multiple schematic windows of the printed circuit board 6,115,546 A * 9/2000 Chevallier ...... GO6F 17,5081 design simultaneously with outputting the multiple layout T16, 112 windows of the printed circuit board design. A first of the 6,757,878 B2 * 6/2004 Srinivasan ...... GO6F 17,5072 T16,122 schematic windows is paired with a first of the layout win 7,418,683 B1* 8/2008 Sonnard ...... GO6F 17,5081 dows, the paired windows depicting representations of a com T16,122 mon Sub-portion of the printed circuit board design. 7,765,508 B1* 7/2010 Roberts ...... GO6F 17,5045 T16,122 19 Claims, 6 Drawing Sheets

&eceive a printed circuit board 32 desig; in a memory

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Generate. using tiples &youtwic 30 inted circuita:

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3. Pair Wixws. US 9.411.925 B2 Page 2

(56) References Cited 2009/0271742 A1* 10/2009 Zhang ...... G06F 9,4443 71.5/854 U.S. PATENT DOCUMENTS 2010.0005438 A1 1/2010 Nakamura 2004/0117750 A1* 6, 2004 Skoll ...... GO6F 17,5081 2011/0276908 A1* 11, 2011 O'Riordan ...... G06F 9,4443 T16,111 715,763 2005/0268269 A1* 12/2005 Coiley ...... GO6F 17,5045 2012fOO23474 A1 1/2012 Geet al. T16,113 2008/0252311 A1 10/2008 Koh et al. * cited by examiner U.S. Patent Aug. 9, 2016 Sheet 1 of 6 US 9.411,925 B2

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F. U.S. Patent Aug. 9, 2016 Sheet 2 of 6 US 9.411,925 B2

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FG. 2 U.S. Patent Aug. 9, 2016 Sheet 3 of 6 US 9.411,925 B2

38 Receive a printed circuit board 3O2 design in a femory

Generate, using a processor, ruitiple schematic windows of the 34. printed circuit board design

Generate, using the processor, ruitipie layout windows of the 308 printed circuit board design

Output the nultiple schematic windows of the printed circuit board design simutaneously with outputting the nutipe layout widows of the printed circuit board design

3 { air widows

FG. 3 U.S. Patent Aug. 9, 2016 Sheet 4 of 6 US 9.411,925 B2

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Scleratic Wiiw layout widow A. 3.

Schematic window layout window A2 32

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548 G. SC US 9,411,925 B2 1. 2 SMULTANEOUSLY VIEWING MULTI neously with outputting the multiple layout windows of the PARED SCHEMATIC AND LAYOUT printed circuit board design. A first of the schematic windows WINDOWS ON PRINTED CIRCUIT BOARD is paired with a first of the layout windows, the paired win (PCB) DESIGNSOFTWARE AND TOOLS dows depicting representations of a first common Sub-portion of the printed circuit board design. A second of the schematic BACKGROUND windows is paired with a second of the layout windows, the paired windows depicting representations of a second com The present invention relates to printed circuitboard (PCB) mon Sub-portion of the printed circuit board design, the sec design Software, and more specifically, this invention relates ond common Sub-portion of the printed circuit board design to the pairing of corresponding layout and Schematic win 10 being different than the first common sub-portion of the dows of a printed circuit board (PCB) design. printed circuit board design. Cross-probing is performed Current printed circuit board (PCB) design software sup between all of the windows showing a representation of a ports opening only a single layout window. This proves to be selected component. One of the layout windows depicts an limiting especially interms of userschematic capture, as well entire layout of the printed circuit board design. Logic is also as the viewing of both driver and receiver portions of the 15 provided for receiving a user selection of the first sub-portion higher density PCB designs of today. In the event that a of the printed circuitboard design from the entire layout of the hardware designer wants to see both the logical and physical printed circuit board design, and generating the first of the connections of a long trace on a PCB, it is not possible for layout windows and the first of the schematic windows upon him/her to Zoom in on both driver and receiver portions in a receiving the user selection. layout window. Instead, the user is limited to traversing the Other aspects and embodiments of the present invention trace of a PCB in the single layout window, Zooming in and will become apparent from the following detailed descrip out multiple times to find the details of a PCB layout. tion, which, when taken in conjunction with the drawings, illustrate by way of example the principles of the invention. BRIEF SUMMARY 25 BRIEF DESCRIPTION OF THE SEVERAL A method according to one embodiment includes receiving VIEWS OF THE DRAWINGS a printed circuit board design in a memory; generating, using a processor, multiple schematic windows of the printed cir FIG. 1 illustrates a , in accordance cuit board design; generating, using the processor, multiple with one embodiment. layout windows of the printed circuit board design; and out 30 FIG. 2 shows a representative hardware environment that putting the multiple schematic windows of the printed circuit may be associated with the servers and/or clients of FIG. 1, in board design simultaneously with outputting the multiple accordance with one embodiment. layout windows of the printed circuit board design. A first of FIG.3 is a flowchart of a method according to one embodi the schematic windows is paired with a first of the layout ment. windows, the paired windows depicting representations of a 35 FIG. 4 is a depiction of schematic and layout window common Sub-portion of the printed circuit board design. pairings. A program product for generating multiple sche FIG. 5A is a depiction of a graphical output of an entire matic and layout windows depicting a printed circuit board printed circuit board. design, according to one embodiment, includes a computer FIG.5B is a depiction of printed circuitboard (PCB) layout readable storage medium having program code embodied 40 windows in multiple windows according to one embodiment. therewith, the program code executable by a processor to FIG.5C is a depiction of schematic and layout sub-portion cause the processor to: generate, by the processor, multiple window pairings. schematic windows of the printed circuit board design; gen erate, by the processor, multiple layout windows of the DETAILED DESCRIPTION printed circuit board design; and output, by the processor, the 45 multiple schematic windows of the printed circuit board The following description is made for the purpose of illus design simultaneously with outputting the multiple layout trating the general principles of the present invention and is windows of the printed circuit board design. A first of the not meant to limit the inventive concepts claimed herein. schematic windows is paired with a first of the layout win Further, particular features described herein can be used in dows, the paired windows depicting representations of a first 50 combination with other described features in each of the common Sub-portion of the printed circuit board design. A various possible combinations and permutations. second of the schematic windows is paired with a second of Unless otherwise specifically defined herein, all terms are the layout windows, the paired windows depicting represen to be given their broadest possible interpretation including tations of a second common Sub-portion of the printed circuit meanings implied from the specification as well as meanings board design, the second common Sub-portion of the printed 55 understood by those skilled in the art and/or as defined in circuit board design being different than the first common dictionaries, treatises, etc. Sub-portion of the printed circuit board design. Computer It must also be noted that, as used in the specification and code is also provided for causing the processor to perform the appended claims, the singular forms “a,” “an and the cross-probing between the paired windows. include plural referents unless otherwise specified. It will be A system according to one embodiment includes a proces 60 further understood that the terms “comprises” and/or “com sor and logic integrated with and/or executable by the pro prising, when used in this specification, specify the presence cessor. The logic is configured to receive a printed circuit of stated features, integers, steps, operations, elements, and/ board design in a memory; generate, using a processor, mul or components, but do not preclude the presence or addition tiple schematic windows of the printed circuit board design; of one or more other features, integers, steps, operations, generate, using the processor, multiple layout windows of the 65 elements, components, and/or groups thereof. printed circuit board design; and output the multiple sche The following description discloses several preferred matic windows of the printed circuit board design simulta embodiments of systems, methods and computer program US 9,411,925 B2 3 4 products for the pairing of corresponding layout and sche 104 and a second remote network 106. A gateway 101 may be matic windows, (and their user-selected Sub-portions), of a coupled between the remote networks 102 and a proximate printed circuit board (PCB) design. network 108. In the context of the present architecture 100, In one general embodiment, a method includes receiving a the networks 104,106 may each take any form including, but printed circuit board design in a memory; generating, using a not limited to a LAN, a WAN such as the Internet, public processor, multiple schematic windows of the printed circuit switched telephone network (PSTN), internal telephone net board design; generating, using the processor, multiple layout work, etc. windows of the printed circuit board design; and outputting In use, the gateway 101 serves as an entrance point from the the multiple schematic windows of the printed circuit board remote networks 102 to the proximate network 108. As such, design simultaneously with outputting the multiple layout 10 windows of the printed circuit board design. A first of the the gateway 101 may function as a router, which is capable of schematic windows is paired with a first of the layout win directing a given packet of data that arrives at the gateway dows, the paired windows depicting representations of a com 101, and a , which furnishes the actual path in and out mon Sub-portion of the printed circuit board design. of the gateway 101 for a given packet. In one general embodiment, a computer program product 15 Further included is at least one data server 114 coupled to for generating multiple schematic and layout windows the proximate network 108, and which is accessible from the depicting a printed circuit board design includes a computer remote networks 102 via the gateway 101. It should be noted readable storage medium having program code embodied that the data server(s) 114 may include any type of therewith, the program code executable by a processor to device/groupware. Coupled to each data server 114 is a plu cause the processor to: generate, by the processor, multiple rality of user devices 116. Such user devices 116 may include schematic windows of the printed circuit board design; gen a , lap-top computer, hand-held computer, erate, by the processor, multiple layout windows of the printer or any other type of logic. It should be noted that a user printed circuit board design; and output, by the processor, the device 111 may also be directly coupled to any of the net multiple schematic windows of the printed circuit board works, in one embodiment. design simultaneously with outputting the multiple layout 25 A 120 or series of 120, e.g., fac windows of the printed circuit board design. A first of the simile , printers, networked and/or local storage schematic windows is paired with a first of the layout win units or systems, etc., may be coupled to one or more of the dows, the paired windows depicting representations of a first networks 104, 106, 108. It should be noted that common Sub-portion of the printed circuit board design. A and/or additional components may be utilized with, or inte second of the schematic windows is paired with a second of 30 grated into, any type of network element coupled to the net the layout windows, the paired windows depicting represen works 104,106, 108. In the context of the present description, tations of a second common sub-portion of the printed circuit a network element may refer to any component of a network. board design, the second common Sub-portion of the printed According to Some approaches, methods and systems circuit board design being different than the first common described herein may be implemented with and/or on virtual Sub-portion of the printed circuit board design. Computer 35 systems and/or systems which emulate one or more other code is also provided for causing the processor to perform systems, such as a UNIX system which emulates an IBM cross-probing between the paired windows. Z/OS environment, a UNIX system which virtually hosts a In one general embodiment, a system includes a processor MICROSOFT WINDOWS environment, a MICROSOFT and logic integrated with and/or executable by the processor. WINDOWS system which emulates an IBM z/OS environ The logic is configured to receive a printed circuit board 40 ment, etc. This virtualization and/or emulation may be design in a memory; generate, using a processor, multiple enhanced through the use of VMWARE software, in some schematic windows of the printed circuit board design; gen embodiments. erate, using the processor, multiple layout windows of the In more approaches, one or more networks 104,106, 108, printed circuit board design; and output the multiple sche may represent a cluster of systems commonly referred to as a matic windows of the printed circuit board design simulta 45 "cloud. In cloud computing, shared resources, such as pro neously with outputting the multiple layout windows of the cessing power, peripherals, software, data, servers, etc., are printed circuit board design. A first of the schematic windows provided to any system in the cloud in an on-demand rela is paired with a first of the layout windows, the paired win tionship, thereby allowing access and distribution of services dows depicting representations of a first common Sub-portion across many computing systems. Cloud computing typically of the printed circuit board design. A second of the schematic 50 involves an Internet connection between the systems operat windows is paired with a second of the layout windows, the ing in the cloud, but other techniques of connecting the sys paired windows depicting representations of a second com tems may also be used. mon Sub-portion of the printed circuit board design, the sec FIG. 2 shows a representative hardware environment asso ond common Sub-portion of the printed circuit board design ciated with a user device 116 and/or server 114 of FIG. 1, in being different than the first common sub-portion of the 55 accordance with one embodiment. Such figure illustrates a printed circuit board design. Cross-probing is performed typical hardware configuration of a workstation having a between all of the windows showing a representation of a 210. Such as a , and a selected component. One of the layout windows depicts an number of other units interconnected via a 212. entire layout of the printed circuit board design. Logic is also The workstation shown in FIG. 2 includes a Random provided for receiving a user selection of the first sub-portion 60 Access Memory (RAM) 214, Read Only Memory (ROM) of the printed circuitboard design from the entire layout of the 216, an I/O adapter 218 for connecting peripheral devices printed circuit board design, and generating the first of the such as disk storage units 220 to the bus 212, a layout windows and the first of the schematic windows upon adapter 222 for connecting a keyboard 224, a mouse 226, a receiving the user selection. speaker 228, a microphone 232, and/or other user interface FIG. 1 illustrates an architecture 100, in accordance with 65 devices such as a touch screen and a digital camera (not one embodiment. As shown in FIG. 1, a plurality of remote shown) to the bus 212, adapter 234 for con networks 102 are provided including a first remote network necting the workstation to a communication network 235 US 9,411,925 B2 5 6 (e.g., a data processing network) and a display adapter 236 for specifically described in the illustrative embodiments listed connecting the bus 212 to a display device 238. herein. Further, the graphical output 400 presented herein The workstation may have resident thereon an operating may be used in any desired environment. system such as the Microsoft Windows(R Graphical output 400 includes the output pairings 402 of (OS), a MAC OS, a UNIXOS, etc. It will be appreciated that schematic windows 404 and layout windows 406 as described a (preferred embodiment may also be implemented on plat above, and may include a first pairing (A1-B1), a second forms and operating systems other than those mentioned. A pairing (A2-B2), up to n-pairings, of a schematic window and preferred embodiment may be written using XML, C, and/or a layout window, as illustrated by FIG.4, where n may be any C++ language, or other programming languages, along with reasonable number, e.g., 5, 10, 15, etc. Furthermore, the win an object oriented programming methodology. Object ori 10 dows in each pair depict representations of a respective com ented programming (OOP), which has become increasingly mon sub-portion of the printed circuit board design. These used to develop complex applications, may be used. common Sub-portions are each a smaller respective portion of Referring now to FIG. 3, a flowchart of a method 300 is the overall schematic or layout of the entire printed circuit shown according to one embodiment. The method 300 may board design, which will be described in greater detail below. be performed in accordance with the present invention in any 15 Note also that the number of schematic windows and lay of the environments depicted in any of the figures, among out windows may be different various approaches. For others, in various embodiments. Of course, more or less example, one illustrative output may include several paired operations than those specifically described in FIG.3 may be windows, and a layout window without a corresponding included in method 300, as would be understood by one of paired schematic window. Further, in Some approaches, the skill in the art upon reading the present descriptions. various windows may be opened and closed separately from Each of the steps of the method 300 may be performed by the others. any suitable component of the operating environment. For With continued reference to the output pairings 402, cross example, in various embodiments, the method 300 may be probing may be performed, e.g., in order to view in further partially or entirely performed by one or more processors, or detailboth the logical and physical connections of a long trace Some other device having one or more processors therein. The 25 on a PCB. Cross-probing may include design, review, verifi processor, e.g., processing circuit(s), chip(s), and/or cation, testing, etc. between all of the windows 404 and 406, module(s) implemented in hardware and/or Software, and showing a representation of a selected component e.g. traces, preferably having at least one hardware component may be hardware, Surface components, etc. utilized in any device to perform one or more steps of the The option of cross-probing between paired windows of a method 300. Illustrative processors include, but are not lim 30 PCB design proves advantageous, especially in PCB designs ited to, a central processing unit (CPU), an application spe containing long layout traces. This option allows a user to cific (ASIC), a field programmable gate view and compare both the driver and receiver portions of array (FPGA), etc., combinations thereof, or any other suit both the schematic and layout views of a PCB simulta able computing device known in the art. neously. Furthermore, a user selection of a component e.g. As shown in FIG. 3, method 300 may initiate with opera 35 traces, hardware, Surface components, etc. and/or highlight a tion 302, where a printed circuit board (PCB) design is portion of a PCB layout window may be received, upon which received in a memory. In operation 304, multiple schematic is output the corresponding component e.g. traces, hardware, windows of the printed circuit board design are generated Surface components, etc. and/or highlighted portion of the using a processor, e.g., of a type disclosed herein. Looking to paired PCB schematic window. Similarly, a user-selection of operation 306, using the processor, multiple layout windows 40 a component e.g. traces, hardware, Surface components, etc. of the printed circuitboard design are generated. Note that the and/or highlight a portion of a PCB schematic window may various windows generated in operations 304 and 306 may be be received, upon which is output the corresponding compo generated sequentially, on demand, etc. In operation 308, the nent e.g. traces, hardware, Surface components, etc. and/or multiple schematic windows of the printed circuit board highlighted portion of the paired PCB layout window. design are then output simultaneously with outputting mul 45 For example, by viewing details of both logical and physi tiple layout windows of the printed circuit board design. cal connections on both driver and receiver ends simulta During such outputting as in operation 308, a first of the neously, if a designer sees two traces crossing on the layout schematic windows is paired with a first of the layout win window, normally, this is not a good topology to route the dows, the paired windows depicting representations of a com traces on PAB design. The designer can highlight and cross mon Sub-portion of the printed circuit board design, which 50 probe between the two paired windows (e.g., showing the will be described in greater detail below. Furthermore, the driver end and receiver end). In this way, it is easier to deter common Sub-portion is a smaller portion of the overall sche mine how to make logical changes on the design schematic to matic or layout of the entire printed circuit board design. In avoid the crossing of two traces in the layout window. operation 310, pairing of one or more schematic windows to Cross-probing may further be performed between any corresponding layout windows, or vice versa, may be per 55 active layout window and any active schematic window. Such formed. The pairs may be selected manually on a one-by-one active layout and schematic windows may be open in the basis upon receiving user selection. In other approaches, the same monitor or in separate monitors. pairing may be performed automatically. Cross-probing may While cross-probing is preferably performed between also be performed. paired windows, in some approaches cross-probing may be FIG. 4 depicts a graphical output 400 of schematic and 60 performed between a second (B2) of the layout windows 406 layout window pairings in accordance with one embodiment. and a second (A2) of the schematic windows 404, the second As an option, the present graphical output 400 may be imple of the layout windows 406 and the second of the schematic mented in conjunction with features from any other embodi windows 404 not being paired windows 402. ment listed herein, such as those described with reference to Conventional PCB software limits a user in that he/she has the other FIGS. Of course, however, such graphical output 65 only the option of opening a single PCB layout window on a 400 and others presented herein ma be used in various appli monitor and viewing either a complete PCB layout overview cations and/or in permutations which may or may not be or a single Zoomed view of a portion of a PCB layout. US 9,411,925 B2 7 8 Embodiments described herein howeverallow a user to Zoom menus, pop-up menus, drag and drop ability, window size in on the driver and receiver ends of both schematic and quandranting (e.g., Snap function), etc. Additional optional layout windows, with the option of displaying multiple sepa window configurations may be generated and displayed on a rate windows containing schematic and layout views of a monitor(s) based on an existing window view. For example a PCB design on a monitor. Furthermore, a user is able to view user may select from a menu to display a layout window that and capture these multiple windows, which may include very corresponds and is then paired with a schematic window. detailed signals of the schematics, as well as physical pins and Likewise, a user may select from the menu to display a sche vias of the layouts. matic window that corresponds and is then paired with an FIGS. 5A-5C depict illustrative graphical outputs 500, open layout window. 520, 540 in accordance with several embodiments. As an 10 Referring now to FIG. 5C, graphical output 540 illustrates option, the present graphical outputs 500, 520, 540 may be multiple schematic windows 542, 544 of the printed circuit implemented in conjunction with features from any other board design output simultaneously while outputting the mul embodiment listed herein, such as those described with ref tiple layout windows 546, 548 of the printed circuit board erence to the other FIGS. Of course however, such graphical design. Layout windows may be displayed on a single moni outputs 500,520, 540 and others presented herein may be 15 tor 550, or multiple monitors. As mentioned in the description used in various applications and/or in permutations which of FIG. 4, the first of the schematic windows 542 is paired may or may not be specifically described in the illustrative with a first of the layout windows 546, the paired windows embodiments listed herein. Further, the graphical outputs 542, 546 depicting representations of a first common sub 500, 520, 540 presented herein may be used in any desired portion of the printed circuit board design. environment. Similarly, a second of the schematic windows 544 is paired Graphical output 500 of FIG.5A includes a window 508 on with a second of the layout windows 548, the paired windows a computer monitor 506, where the window 508 depicts an 544, 548 depicting representations of a second common sub entire layout of a printed circuit board (PCB) 504. Selection portion of the printed circuit board design. of a sub-portion 502 of the printed circuit board design may The second common Sub-portion of the printed circuit be received from a user. From this user selected sub-portion 25 board design may be different than the first common sub 502, a first of the layout windows and a first of the schematic portion of the printed circuit board design. In another windows may be generated as will be described in greater approach, the second common Sub-portion of the printed detail below. Additionally, additional and/or alternative user circuitboard design may be a Sub-portion of the first common selected sub-portions 510 and 512 may be received. Sub-portion. Referring now to FIG. 5B, graphical output 520 is pre 30 The option of depicting multiple sub-portions of a PCB is sented on a first monitor 524, which outputs a window 522 advantageous especially in terms of of a illustrating a more detailed view of sub-portion 502 of FIG. PCB design. Where previous approaches were limited to 5A of the printed circuit board design. Furthermore, a user capturing a single view of a PCB layout, various embodi may select sub-portions 510, 512 of the sub-portion (502 of ments including the option of displaying multiple user FIG.5A) of the printed circuitboard design (504 of FIG.5A). 35 selected sub-portions of a PCB layout as well as the entire A second, third, fourth, etc. layout window corresponding to PCB allow presentation of both detailed portions (schematics the user-selected sub-portion(s) of the sub-portion may then and layouts) as well as an overview of a PCB simultaneously. be generated. For example, layout windows 526, 528 may be The present invention may be a system, a method, and/or a generated and output to show the user-selected Sub-portions computer program product. The computer program product 510, 512 of the printed circuit board design. 40 may include a computer readable storage medium (or media) In further embodiments, with continued reference to FIG. having computer readable program instructions thereon for 5B, selection of one sub-portion 510 of the printed circuit causing a processor to carry out aspects of the present inven board design may cause automatic selection of another Sub tion. portion 512 that is connected to the user-selected sub-portion The computer readable storage medium can be a tangible 510. For example, selection of a driver portion may cause 45 device that can retain and store instructions for use by an automatic selection of a receiverportion of the printed circuit instruction execution device. The computer readable storage board design. Moreover, detailed schematic layout view 526, medium may be, for example, but is not limited to, an elec 528 and/or layout views may be generated automatically tronic storage device, a magnetic storage device, an optical and/or on demand. storage device, an electromagnetic storage device, a semicon Similarly, a second, third, fourth, etc. Schematic window 50 ductor storage device, or any suitable combination of the corresponding to the selected Sub-portion(s) of a schematic foregoing. A non-exhaustive list of more specific examples of Sub-portion of a printed circuit board design may be gener the computer readable storage medium includes the follow ated and paired with the schematic windows, as will be ing: a portable computer diskette, a hard disk, a random described in FIG.S.C. access memory (RAM), a read-only memory (ROM), an eras According to various embodiments, multiple windows 55 able program able read-only memory (EPROM or Flash may be simultaneously output to one monitor 524 and/or memory), a static random access memory (SRAM), a por multiple monitors 524, 530. Moreover, in various table compact disc read-only memory (CD-ROM), a digital approaches, the windows may be repositioned, resized, versatile disk (DVD), a memory stick, a floppy disk, a moved from monitor to monitor, etc. mechanically encoded device Such as punch-cards or raised A user may select a sub-portion as described above using a 60 structures in a groove having instructions recorded thereon, mouse, keyboard, touchpad, etc. or similar user interface and any Suitable combination of the foregoing. A computer tools. The selected sub-portion may be delineated by a box, readable storage medium, as used herein, is not to be con circle, oval, etc. area of the PCB design. Additionally, user Strued as being transitory signals perse, such as radio waves interface elements may be presented to allow a user to open or other freely propagating electromagnetic waves, electro new windows, select additional optional window configura 65 magnetic waves (propagating through a waveguide or other tions, perform cross-probing, etc. The user interface elements transmission media (e.g., light pulses passing through a fiber may be of any type known in the art, such as drop down optic cable), or electrical signals transmitted through a . US 9,411,925 B2 10 Computer readable program instructions described herein apparatus, or other device to cause a series of operational can be downloaded to respective computing/processing steps to be performed on the computer, other programmable devices from a computer readable storage medium or to an apparatus or other device to produce a computer implemented external computer or external storage device via a network, process, such that the instructions which execute on the com for example, the Internet, a local area network, a wide area 5 puter, other programmable apparatus, or other device imple network and/or a wireless network. The network may com ment the functions/acts specified in the flowchart and/or prise transmission cables, optical transmission fibers, block or blocks. wireless transmission, routers, firewalls, , gateway The flowchart and block diagrams in the Figures illustrate and/or edge servers. A network adapter card or the architecture, functionality, and operation of possible network interface in each computing/processing device 10 implementations of systems, methods, and computer pro receives computer readable program instructions from the gram products according to various embodiments of the network and forwards the computer readable program present invention. In this regard, each block in the flowchart instructions for storage in a computer readable storage or block diagrams may represent a module, segment, or por tion of instructions, which comprises one or more executable medium within the respective computing/processing device. instructions for implementing the specified logical Computer readable program instructions for carrying out 15 function(s). In some alternative implementations, the func operations of the present invention may be assembler instruc tions noted in the block may occur out of the order noted in the tions, instruction-set-architecture (ISA) instructions, figures. For example, two blocks shown in Succession may, in instructions, machine dependent instructions, fact, be executed substantially concurrently, or the blocks microcode, firmware instructions, state-setting data, or either may sometimes be executed in the reverse order, depending Source code or object code written in any combination of one 20 upon the functionality involved. It will also be noted that each or more programming languages, including an object ori block of the block diagrams and/or flowchart illustration, and ented such as Smalltalk, C++ or the combinations of blocks in the block diagrams and/or flow like, and conventional procedural programming languages, chart illustration, can be implemented by special purpose Such as the “C” programming language or similar program hardware-based systems that perform the specified functions ming languages. The computer readable program instructions 25 or acts or carry outcombinations of special purpose hardware may execute entirely on the user's computer, partly on the and computer instructions. user's computer, as a stand-alone software package, partly on Moreover, a system according to various embodiments the user's computer and partly on a remote computer or may include a processor and logic integrated with and/or entirety on the remote computer or server. In the latter sce executable by the processor, the logic being configured to nario, the remote computer may be connected to the user's 30 perform one or more of the process steps recited herein. By computer through any type of network, including a local area integrated with, what is meant is that the processor has logic network (LAN) or a wide area network (WAN), or the con embedded therewith as hardware logic, such as an application nection may be made to an external computer (for example, specific integrated circuit (ASIC), a field programmable gate through the Internet using an Internet Service Provider). In array (FPGA), etc. By executable by the processor, what is Some embodiments, electronic circuitry including, for 35 meant is that the logic is hardware logic; software logic Such example, programmable logic circuitry, field-programmable as firmware, part of an operating system, part of an applica gate arrays (FPGA), or programmable logic arrays (PLA) tion program; etc., or some combination of hardware and may execute the computer readable program instructions by Software logic that is accessible by the processor and config utilizing state information of the computer readable program ured to cause the processor to perform some functionality instructions to personalize the electronic circuitry, in order to 40 upon execution by the processor. Software logic may be perform aspects of the present invention. stored on local and/or remote memory of any memory type, as Aspects of the present invention are described herein with known in the art. Any processor known in the art may be used, reference to flowchart illustrations and/or block diagrams of Such as a software processor module and/or a hardware pro methods, apparatus (systems), and computer program prod cessor Such as an ASIC, a FPGA, a central processing unit ucts according to embodiments of the invention. It will be 45 (CPU), an integrated circuit (IC), a understood that each block of the flowchart illustrations and/ (GPU), etc. or block diagrams, and combinations of blocks in the flow It will be clear that the various features of the foregoing chart illustrations and/or block diagrams, can be imple systems and/or methodologies may be combined in any way, mented by computer readable program instructions. creating a plurality of combinations from the descriptions These computer readable program instructions may be pro- 50 presented above. vided to a processor of a general purpose computer, special It will be further appreciated that embodiments of the purpose computer, or other programmable data processing present invention may be provided in the form of a service apparatus to produce a machine. Such that the instructions, deployed on behalf of a customer to offer service on demand. which execute via the processor of the computer or other While various embodiments have been described above, it programmable data processing apparatus, create means for 55 should be understood that they have been presented by way of implementing the functions/acts specified in the flowchart example only, and not limitation. Thus, the breadth and scope and/or block diagram block or blocks. These computer read of a preferred embodiment should not be limited by any of the able program instructions may also be stored in a computer above-described exemplary embodiments, but should be readable storage medium that can direct a computer, a pro defined only in accordance with the following claims and grammable data processing apparatus, and/or other devices to 60 their equivalents. function in a particular manner, such that the computer read What is claimed is: able storage medium having instructions stored therein com 1. A method, comprising: prises an article of manufacture including instructions which receiving a printed circuit board design in a memory; implement aspects of the function/act specified in the flow generating, using a processor, multiple schematic windows chart and/or block diagram block or blocks. 65 of the printed circuit board design; The computer readable program instructions may also be generating, using the processor, multiple layout windows loaded onto a computer, other programmable data processing of the printed circuit board design; US 9,411,925 B2 11 12 outputting the multiple schematic windows of the printed ing representations of a first common Sub-portion of the circuit board design simultaneously with outputting the printed circuit board design, multiple layout windows of the printed circuit board wherein a second of the schematic windows is paired with design, a second of the layout windows, the paired windows wherein a first of the schematic windows is paired with a depicting representations of a second common Sub-por first of the layout windows, the paired windows depict tion of the printed circuit board design, the second com ing representations of a common Sub-portion of the mon Sub-portion of the printed circuit board design printed circuit board design; and being different than the first common sub-portion of the receiving user selection of the sub-portion of the printed printed circuit board design; and circuit board design shown in one of the windows via 10 performing cross-probing between the paired windows. direct user interaction with the one of the windows, and automatically selecting a second sub-portion that is con 10. The computer program product of claim 9, comprising nected to the selected sub-portion. program code executable by the processor to cause the pro 2. The method of claim 1, comprising performing cross cessor to perform cross-probing between all of the windows probing between all of the windows showing a representation 15 showing a representation of a selected component. of a selected component. 11. The computer program product of claim 9, comprising 3. The method of claim 1, comprising performing cross program code executable by the processor to cause the pro probing between a second of the layout windows and a second cessor to perform cross-probing between a third one of the of the schematic windows, the second of the layout windows layout windows and a third one of the schematic windows and the second of the schematic windows not being paired while simultaneously outputting the first and second sche windows. matic windows and the first and second layout windows, the 4. The method of claim 1, wherein the windows are simul third one of the layout windows and the third one of the taneously output to multiple monitors connected to a same schematic windows not being paired windows; and compris computer housing the processor. ing program code executable by the processor to cause the 5. The method of claim 1, wherein one of the layout win 25 processor to perform cross-probing between all of the win dows depicts an entire layout of the printed circuit board dows simultaneously showing a representation of a selected design, and comprising receiving a user selection of the Sub component. portion of the printed circuit board design by indication of the 12. The computer program product of claim 9, wherein the sub-portion by the user via an interface tool that selects the windows are simultaneously output to multiple monitors con sub-portion directly from the depicted entire layout of the 30 nected to a same computer housing the processor. printed circuit board design, and generating the first of the 13. The computer program product of claim 9, wherein one layout windows and the first of the schematic windows upon of the layout windows depicts an entire layout of the printed receiving the user selection. circuit board design, and comprising program code execut 6. The method of claim 1, comprising receiving a user able by the processor to cause the processor to receive a user selection of a sub-portion of the sub-portion of the printed 35 selection of the sub-portion of the printed circuitboard design circuit board design depicted in the first of the layout win from user interaction directly in the layout window having the dows corresponding to an area delineated by at least one of a depiction of the entire layout of the printed circuit board box, a circle and an oval created using a mouse coupled to the design via a user interface tool, and program code executable processor, and generating a second of the layout windows by the processor to cause the processor to generate the first of corresponding to the selected Sub-portion of the Sub-portion. 40 the layout windows and the first of the schematic windows 7. The method of claim 6, comprising generating a second upon receiving the user selection. of the schematic windows corresponding to the Sub-portion of 14. The computer program product of claim 9, comprising the Sub-portion and outputting the second schematic window program code executable by the processor to cause the pro simultaneously with the first layout window and the second cessor to receive a user selection of a Sub-portion of the layout window. 45 sub-portion of the printed circuit board design depicted in the 8. The method of claim 1, comprising automatically select first of the layout windows, and generate a second of the ing a second Sub-portion of the printed circuit board design layout windows corresponding to the selected Sub-portion of connected to the sub-portion of the printed circuit board the sub-portion. design depicted in the first of the windows, and generating a 15. The computer program product of claim 14, compris second of the layout windows depicting representations of the 50 ing program code executable by the processor to cause the second Sub-portion of the printed circuit board design. processor to generate a second of the schematic windows 9. A computer program product for generating multiple corresponding to the Sub-portion of the Sub-portion and out schematic and layout windows depicting a printed circuit putting the second schematic window simultaneously with board design, the computer program product comprising a the first layout window and the second layout window. computer readable storage medium having program code 55 16. The computer program product of claim 9, comprising embodied therewith, the program code executable by a pro program code executable by the processor to cause the pro cessor to cause the processor to: cessor to automatically select a third sub-portion of the generate, by the processor, multiple schematic windows of printed circuit board design connected to the first Sub-portion the printed circuit board design; of the printed circuit board design depicted in the first of the generate, by the processor, multiple layout windows of the 60 layout windows, and program code executable by the proces printed circuit board design; Sor to cause the processor to generate a third one of the layout output, by the processor, the multiple schematic windows windows depicting representations of the third Sub-portion of of the printed circuit board design simultaneously with the printed circuit board design. outputting the multiple layout windows of the printed 17. A system, comprising: circuit board design; 65 a processor and logic integrated with and/or executable by wherein a first of the schematic windows is paired with a the processor, the logic being configured to: first of the layout windows, the paired windows depict receive a printed circuit board design in a memory; US 9,411,925 B2 13 14 generate, using a processor, multiple schematic windows performing cross-probing between all of the windows of the printed circuit board design; showing a representation of a selected component; generate, using the processor, multiple layout windows of wherein one of the layout windows depicts an entire layout the printed circuit board design; of the printed circuit board design, receiving a user selection of the first sub-portion of the output the multiple schematic windows of the printed cir printed circuit board design from user interaction cuit board design simultaneously with outputting the directly in the layout window having the depiction of the multiple layout windows of the printed circuit board entire layout of the printed circuit board design via an design; and interface tool; and wherein a first of the schematic windows is paired with a generating the first of the layout windows and the first of first of the layout windows, the paired windows depict 10 the schematic windows upon receiving the user selec ing representations of a first common Sub-portion of the tion. printed circuit board design, 18. The system of claim 17, wherein the windows are wherein a second of the schematic windows is paired with simultaneously output to multiple monitors. a second of the layout windows, the paired windows 19. The system of claim 17, comprising receiving a user depicting representations of a second common Sub-por 15 selection of a sub-portion of the sub-portion of the printed tion of the printed circuit board design, the second com circuit board design depicted in the first of the layout win mon Sub-portion of the printed circuit board design dows, and generating a second of the layout windows corre being different than the first common sub-portion of the sponding to the selected Sub-portion of the Sub-portion. printed circuit board design; k k k k k