NUREG/CR-7006 "Review Guidelines for Field-Programmable Gate Arrays in Nuclear Power Plant Safety Systems."
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JTAG Programmer Overview for Hercules-Based Microcontrollers
Application Report SPNA230–November 2015 JTAG Programmer Overview for Hercules-Based Microcontrollers CharlesTsai ABSTRACT This application report describes the necessary steps needed by the third party developers to create a JTAG-based flash programmer for the Hercules™ family of microcontrollers. This document does not substitute the existing user guides on JTAG access to the target systems and how to program the Flash memory, but rather serves as a central location to reference these documents with clarifications specific to the implementation of the Hercules family of microcontrollers. Contents 1 Introduction ................................................................................................................... 2 2 Hercules JTAG Scan Architecture......................................................................................... 2 3 Creating the Firmware to Program the Flash Memory ................................................................ 22 4 Flash Verification ........................................................................................................... 23 5 References .................................................................................................................. 23 List of Figures 1 Hercules JTAG Scan Architecture......................................................................................... 3 2 Conceptual ICEPICK-C Block Diagram for Hercules Implementation ................................................ 5 3 Fields of the 32-Bit Scan Value for Accessing Mapped Registers -
Development of Printed Circuit Board Technology Embedding Active and Passive Devices for E-Function Module
Development of Printed Circuit Board Technology Embedding Active and Passive Devices for e-Function Module Noboru Fujimaki Kiyoshi Koike Kazuhiro Takami Sigeyuki Ogata Hiroshi Iinaga Background shortening of signal wirings between circuits, reduction of damping resistors and elimination of characteristic Higher functionality of today’s portable devices impedance controls. Embedded component module demands smaller, lighter and thinner electronic boards have been adopted for higher functionality of components. Looking at the evolution of package video cameras and miniaturizing wireless communication miniaturization from the flat structure (System in Package: devices. It is expected the use will spread to a wider SiP) -> silicon chip stack structure (Chip on Chip: CoC) -> range of areas including automotive, consumer products, package stack structure (Package on Package: PoP) -> Si industrial equipment and infrastructure equipment. To through chip contact structure, the technology has gone meet these needs, a technology to package and embed from two-dimensional to three-dimensional packaging the various components and LSI will be required. This achieving high density packages. The trends in printed article discusses the method of embedding components, circuit boards and their packaging are shown in Figure 1. soldering technology, production method, reliability and Among the printed circuit boards, the three-dimensional case examples of the embedded component module integrated printed circuit board (hereafter referred to as board. “embedded component module board”) is attracting great attention. Integrating components into embedded component module boards Component embedding enables passive components (1) Embedding active components to be positioned directly beneath the LSI mounted There are two methods of embedding active on the surface providing electrical benefits such as components. -
Utilising Commercially Fabricated Printed Circuit Boards As an Electrochemical Biosensing Platform
micromachines Article Utilising Commercially Fabricated Printed Circuit Boards as an Electrochemical Biosensing Platform Uroš Zupanˇciˇc,Joshua Rainbow , Pedro Estrela and Despina Moschou * Centre for Biosensors, Bioelectronics and Biodevices (C3Bio), Department of Electronic & Electrical Engineering, University of Bath, Claverton Down, Bath BA2 7AY, UK; [email protected] (U.Z.); [email protected] (J.R.); [email protected] (P.E.) * Correspondence: [email protected]; Tel.: +44-(0)-1225-383245 Abstract: Printed circuit boards (PCBs) offer a promising platform for the development of electronics- assisted biomedical diagnostic sensors and microsystems. The long-standing industrial basis offers distinctive advantages for cost-effective, reproducible, and easily integrated sample-in-answer-out diagnostic microsystems. Nonetheless, the commercial techniques used in the fabrication of PCBs produce various contaminants potentially degrading severely their stability and repeatability in electrochemical sensing applications. Herein, we analyse for the first time such critical technological considerations, allowing the exploitation of commercial PCB platforms as reliable electrochemical sensing platforms. The presented electrochemical and physical characterisation data reveal clear evidence of both organic and inorganic sensing electrode surface contaminants, which can be removed using various pre-cleaning techniques. We demonstrate that, following such pre-treatment rules, PCB-based electrodes can be reliably fabricated for sensitive electrochemical -
Best Practices for Board Layout of Motor Drivers
Application Report SLVA959A–November 2018–Revised January 2019 Best Practices for Board Layout of Motor Drivers .................................................................................................................. Motor Drive Business Unit ABSTRACT PCB design of motor drive systems is not trivial and requires special considerations and techniques to achieve the best performance. Power efficiency, high-speed switching frequency, low-noise jitter, and compact board design are few primary factors that designers must consider when laying out a motor drive system. Texas Instruments' DRV devices are ideal for such type of systems because they are highly integrated and well-equipped with protection circuitry. The goal of this application report is to highlight the primary factors of a motor drive layout when using a DRV device and provide a best practice guideline for a high performance solution that reduces thermal stress, optimizes efficiency, and minimizes noise in a motor drive application. Contents 1 Grounding Optimization ..................................................................................................... 3 2 Thermal Overview ........................................................................................................... 7 3 Vias........................................................................................................................... 11 4 General Routing Techniques ............................................................................................. 14 5 Bulk and Bypass -
Intel Quartus Prime Pro Edition User Guide: Programmer Send Feedback
Intel® Quartus® Prime Pro Edition User Guide Programmer Updated for Intel® Quartus® Prime Design Suite: 21.2 Subscribe UG-20134 | 2021.07.21 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Intel® Quartus® Prime Programmer User Guide..............................................................4 1.1. Generating Primary Device Programming Files........................................................... 5 1.2. Generating Secondary Programming Files................................................................. 6 1.2.1. Generating Secondary Programming Files (Programming File Generator)........... 7 1.2.2. Generating Secondary Programming Files (Convert Programming File Dialog Box)............................................................................................. 11 1.3. Enabling Bitstream Security for Intel Stratix 10 Devices............................................ 18 1.3.1. Enabling Bitstream Authentication (Programming File Generator)................... 19 1.3.2. Specifying Additional Physical Security Settings (Programming File Generator).............................................................................................. 21 1.3.3. Enabling Bitstream Encryption (Programming File Generator).........................22 1.4. Enabling Bitstream Encryption or Compression for Intel Arria 10 and Intel Cyclone 10 GX Devices.................................................................................................. 23 1.5. Generating Programming Files for Partial Reconfiguration......................................... -
MAT 253 Operating Manual - Rev
MAT 253 OPERATING MANUAL Issue 04/2002 Ident. No. 114 9090 Thermo Finnigan MAT GmbH Postfach 1401 62 28088 Bremen Germany Reparatur-Begleitkarte*) Repair-Covering Letter Absender: Geräte-Type: Despachter: Instrument Type: __________________________________ _________________________________ __________________________________ Service-Nr.: Service No Sie erhalten zur Reparatur unter unserer Bestell-Nr.: You receive for repair under our order no.: Festgestellte Mängel oder deren Auswirkung: Established defect or its effect: Bitte detaillierte Angaben machen / Please specify in detail Ein Austauschteil haben wir erhalten unter Kommissions-Nr.: An exchange part already received with commission no.: Ja/Yes Nein/No Die Anlage ist außer Funktion The system is out of function Ja/Yes Nein/No Durch die nachfolgende Unterschrift By signing this document I am/ we are certifying bestätige(n) ich /wir, daß die o.g. Teile frei von that the a. m. parts are free from hazardous gesundheitsschädlichen Stoffen sind, bzw. vor materials. In case the parts have been used for ihrer Einsendung an Thermo Finnigan MAT the analysis of hazardous substances I/we dekontaminiert wurden, falls die Teile mit attest that the parts have been decontaminated giftigen Stoffen in Verbindung gekommen sind. before sending them to Thermo Finnigan MAT. __________________________________ _________________________________ Datum / date Unterschrift / signature *) Bitte vollständig ausfüllen / Please fill in completely MAT 253 O P E R A T I N G M A N U A L TABLE OF CONTENTS 1 GETTING -
HSPICE Tutorial
UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE105 Lab Experiments HSPICE Tutorial Contents 1 Introduction 1 2 Windows vs. UNIX 1 2.1 Windows ......................................... ...... 1 2.1.1 ConnectingFromHome .. .. .. .. .. .. .. .. .. .. .. .. ....... 2 2.1.2 RunningHSPICE ................................. ..... 2 2.2 UNIX ............................................ ..... 3 2.2.1 Software...................................... ...... 3 2.2.2 RunningSSH.................................... ..... 4 2.2.3 RunningHSPICE ................................. ..... 4 3 Simulating Circuits in HSPICE and Awaves 5 3.1 HSPICENetlistSyntax ............................. .......... 5 3.2 Examples ........................................ ....... 6 3.2.1 Transient analysis of a simple RC circuit . ............... 6 3.2.2 Operatingpointanalysisforadiode . ............. 7 3.2.3 DCanalysisofadiode............................ ........ 8 3.2.4 ACanalysisofahigh-passfilter. ............ 9 3.2.5 Transferfunctionanalysis . ............ 10 3.2.6 Pole-zeroanalysis. .......... 10 3.2.7 The .measure command................................... 11 3.3 Includinganotherfile. .. .. .. .. .. .. .. .. .. .. .. .. ............ 12 4 Using Awaves 13 4.1 Interfacedescription . ............. 13 4.2 Deletingplots................................... .......... 13 4.3 Printingplots................................... .......... 13 4.4 Makingameasurement .............................. ......... 13 4.5 Zooming........................................ -
Intermittent Computation Without Hardware Support Or Programmer
Intermittent Computation without Hardware Support or Programmer Intervention Joel Van Der Woude, Sandia National Laboratories; Matthew Hicks, University of Michigan https://www.usenix.org/conference/osdi16/technical-sessions/presentation/vanderwoude This paper is included in the Proceedings of the 12th USENIX Symposium on Operating Systems Design and Implementation (OSDI ’16). November 2–4, 2016 • Savannah, GA, USA ISBN 978-1-931971-33-1 Open access to the Proceedings of the 12th USENIX Symposium on Operating Systems Design and Implementation is sponsored by USENIX. Intermittent Computation without Hardware Support or Programmer Intervention Joel Van Der Woude Matthew Hicks Sandia National Laboratories∗ University of Michigan Abstract rapid changes drive us closer to the realization of smart As computation scales downward in area, the limi- dust [20], enabling applications where the cost and size tations imposed by the batteries required to power that of computation had previously been prohibitive. We are computation become more pronounced. Thus, many fu- rapidly approaching a world where computers are not ture devices will forgo batteries and harvest energy from just your laptop or smart phone, but are integral parts their environment. Harvested energy, with its frequent your clothing [47], home [9], or even groceries [4]. power cycles, is at odds with current models of long- Unfortunately, while the smaller size and lower cost of running computation. microcontrollers enables new applications, their ubiqui- To enable the correct execution of long-running appli- tous adoption is limited by the form factor and expense of cations on harvested energy—without requiring special- batteries. Batteries take up an increasing amount of space purpose hardware or programmer intervention—we pro- and weight in an embedded system and require special pose Ratchet. -
Nanoelectronic Mixed-Signal System Design
Nanoelectronic Mixed-Signal System Design Saraju P. Mohanty Saraju P. Mohanty University of North Texas, Denton. e-mail: [email protected] 1 Contents Nanoelectronic Mixed-Signal System Design ............................................... 1 Saraju P. Mohanty 1 Opportunities and Challenges of Nanoscale Technology and Systems ........................ 1 1 Introduction ..................................................................... 1 2 Mixed-Signal Circuits and Systems . .............................................. 3 2.1 Different Processors: Electrical to Mechanical ................................ 3 2.2 Analog Versus Digital Processors . .......................................... 4 2.3 Analog, Digital, Mixed-Signal Circuits and Systems . ........................ 4 2.4 Two Types of Mixed-Signal Systems . ..................................... 4 3 Nanoscale CMOS Circuit Technology . .............................................. 6 3.1 Developmental Trend . ................................................... 6 3.2 Nanoscale CMOS Alternative Device Options ................................ 6 3.3 Advantage and Disadvantages of Technology Scaling . ........................ 9 3.4 Challenges in Nanoscale Design . .......................................... 9 4 Power Consumption and Leakage Dissipation Issues in AMS-SoCs . ................... 10 4.1 Power Consumption in Various Components in AMS-SoCs . ................... 10 4.2 Power and Leakage Trend in Nanoscale Technology . ........................ 10 4.3 The Impact of Power Consumption -
Writing Simple Spice Netlists
By Joshua Cantrell Page <1> [email protected] Writing Simple Spice Netlists Introduction Spice is used extensively in education and research to simulate analog circuits. This powerful tool can help you avoid assembling circuits which have very little hope of operating in practice through prior computer simulation. The circuits are described using a simple circuit description language which is composed of components with terminals attached to particular nodes. These groups of components attached to nodes are called netlists. Parts of a Spice Netlist A Spice netlist is usually organized into different parts. The very first line is ignored by the Spice simulator and becomes the title of the simulation.1 The rest of the lines can be somewhat scattered assuming the correct conventions are used. For commands, each line must start with a ‘.’ (period). For components, each line must start with a letter which represents the component type (eg., ‘M’ for MOSFET). When a command or component description is continued on multiple lines, a ‘+’ (plus) begins each following line so that Spice knows it belongs to whatever is on the previous line. Any line to be ignored is either left blank, or starts with a ‘*’ (asterik). A simple Spice netlist is shown below: Spice Simulation 1-1 *** MODEL Descriptions *** .model nm NMOS level=2 VT0=0.7 KP=80e-6 LAMBDA=0.01 vdd *** NETLIST Description *** R1 M1 M1 vdd ng 0 0 nm W=3u L=3u in 3µ/3µ + R1 in ng 50 ng 5V - Vdd Vdd vdd 0 5 50Ω Vin in 0 2.5 Vin + *** SIMULATION Commands *** - 2.5V 0 .op .end Figure 1: Schematic of Spice Simulation 1-1 Netlist The first line is the title of the simulation. -
PDF Package Information
This version: Apr. 2001 Previous version: Jun. 1997 PACKAGE INFORMATION 1. PACKAGE CLASSIFICATIONS This document is Chapter 1 of the package information document consisting of 8 chapters in total. PACKAGE INFORMATION 1. PACKAGE CLASSIFICATIONS 1. PACKAGE CLASSIFICATIONS 1.1 Packaging Trends In recent years, marked advances have been made in the electronics field. One such advance has been the progression from vacuum tubes to transistors and finally, to ICs. ICs themselves have been more highly integrated into LSIs, VLSIs, and now, ULSIs. With increased functions and pin counts, IC packages have had to change significantly in the last few years in order to keep-up with the advancement in semiconductor development. Functions required for conventional IC packages are as follows: 1) To protect IC chips from the external environment 2) To facilitate the packaging and handling of IC chips 3) To dissipate heat generated by IC chips 4) To protect the electrical characteristics of the IC Standard dual-in-line packages (DIP), which fulfill these basic requirements, have enjoyed wide usage in the electronics industry for a number of years. With increasing integration and higher speed ICs, and with the miniaturization of electronic equipment, newer packages have been requested by the industry which incorporate the functions listed below: 1) Multi-pin I/O 2) Ultra-miniature packages 3) Packages suited to high density ICs 4) Improved heat resistance for use with reflow soldering techniques 5) High throughput speed 6) Improved heat dissipation 7) Lower cost per pin In response to these requests, OKI has developed a diversified family of packages to meet the myriad requirements of today’s burgeoning electronics industry. -
SPICE Netlist Generation for Electrical Parasitic Modeling of Multi-Chip Power Module Designs Peter Tucker University of Arkansas, Fayetteville
University of Arkansas, Fayetteville ScholarWorks@UARK Electrical Engineering Undergraduate Honors Electrical Engineering Theses 5-2013 SPICE netlist generation for electrical parasitic modeling of multi-chip power module designs Peter Tucker University of Arkansas, Fayetteville Follow this and additional works at: http://scholarworks.uark.edu/eleguht Part of the Electrical and Electronics Commons, and the Electronic Devices and Semiconductor Manufacturing Commons Recommended Citation Tucker, Peter, "SPICE netlist generation for electrical parasitic modeling of multi-chip power module designs" (2013). Electrical Engineering Undergraduate Honors Theses. 4. http://scholarworks.uark.edu/eleguht/4 This Thesis is brought to you for free and open access by the Electrical Engineering at ScholarWorks@UARK. It has been accepted for inclusion in Electrical Engineering Undergraduate Honors Theses by an authorized administrator of ScholarWorks@UARK. For more information, please contact [email protected], [email protected]. SPICE NETLIST GENERATION FOR ELECTRICAL PARASITIC MODELING OF MULTI-CHIP POWER MODULE DESIGNS SPICE NETLIST GENERATION FOR ELECTRICAL PARASITIC MODELING OF MULTI-CHIP POWER MODULE DESIGNS An Undergraduate Honors College Thesis in the Department of Electrical Engineering College of Engineering University of Arkansas Fayetteville, AR by Peter Nathaniel Tucker April 2013 ABSTRACT Multi-Chip Power Module (MCPM) designs are widely used in the area of power electronics to control multiple power semiconductor devices in a single package. The work described in this thesis is part of a larger ongoing project aimed at designing and implementing a computer aided drafting tool to assist in analysis and optimization of MCPM designs. This thesis work adds to the software tool the ability to export an electrical parasitic model of a power module layout into a SPICE format that can be run through an external SPICE circuit simulator.