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OPERATION ASSIGNMENT with BOARD SPLITTING and MULTIPLE MACHINES in PRINTED CIRCUIT BOARD ASSEMBLY by SAKCHAI RAKKARN Submitted

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OPERATION ASSIGNMENT with BOARD SPLITTING and MULTIPLE MACHINES in PRINTED CIRCUIT BOARD ASSEMBLY by SAKCHAI RAKKARN Submitted OPERATION ASSIGNMENT WITH BOARD SPLITTING AND MULTIPLE MACHINES IN PRINTED CIRCUIT BOARD ASSEMBLY by SAKCHAI RAKKARN Submitted in partial fulfillment of the requirements For the degree of Doctor of Philosophy Dissertation Adviser: Dr. Vira Chankong Department of Electrical Engineering and Computer Science CASE WESTERN RESERVE UNIVERSITY May, 2008 CASE WESTERN RESERVE UNIVERSITY SCHOOL OF GRADUATE STUDIES We hereby approve the thesis/dissertation of ______________________________________________________ candidate for the ________________________________degree *. (signed)_______________________________________________ (chair of the committee) ________________________________________________ ________________________________________________ ________________________________________________ ________________________________________________ ________________________________________________ (date) _______________________ *We also certify that written approval has been obtained for any proprietary material contained therein. i Table of Contents Table of Contents…………………………………………………………………………..i List of Figures……………………………………………………………………………..v List of Tables…………………………………………………………………………….vii Acknowledgements………………………………………………………………………..x Abstract…………………………………………………………………………………...xi 1 Introduction……………………………………………………………………………...1 1.1 The Overview of Printed Circuit Board Assembly…………………………....1 1.2 Planning and Process for PCB Assembly……………………………………..2 1.3 Problem Statement and Rationale...…………………………………………...6 1.4 Research Objective……………………………………………………………8 1.5 Outline of the Thesis…………………………………………………………..8 2 Literature Review…………………………………………………………………...….10 2.1 Models for Generalized Operation Assignment for PCB Assignment Problems………..............................................................................................10 2.2 Generic Problems with Similar Model Structure……….…………………....13 Generalized Assignment Problem (GAP)………………………….…….13 Universal Facility Location Problem (UFLP)……………………………15 2.3 Solution Strategies and Methods for Combinatorial Optimization……...…...17 Binary Integer Programming (BIP)……………………...………………17 Branch-and-Bound……………………………………………………….18 Knapsack Problem……………………………………………………….20 Decomposition and Duality……………………………………………...21 ii Lagrangian Relaxation and Subgradient Method (LR+S)……….………24 Linear Programming……………………………………………….…….28 Heuristics…………………………………………………………….…..29 2.4 Existing Algorithms for Operation Assignment of PCB Assembly…………31 Greedy board heuristics for Single Automatic Machine…………………32 Greedy Board Algorithm with Multiple Automatic Machines…………..34 Stingy Component heuristics for Single Automatic Machine…………...36 Stingy Component Algorithm with Multiple Automatic Machines……..38 Lagrangian Relaxation Heuristic with Single Machine………………….39 Lagrangian Relaxation Heuristic with No Board Splitting and Multiple Machines…………………………………………………..44 3 Solution Algorithms for Multiple Machines with Board Splitting…………………….47 3.1 The Model Revisited…......…………………………………………………..47 Commonality Ratio and Problem Size…………………………………...52 3.2 The Proposed Solution Strategy…..………………………………………….53 3.3 Finding Multipliers………………………..………………………...……….60 LP Relaxation LPr………………………………………………………..61 Lagrangian Relaxation LR……………………………………………….62 3.4 The Final Step: Searching for the Primal Solution….……………………….69 Lower Bound Maintaining Algorithm (LBM)…………..……………….69 LBM Heuristics + Greedy Board ……………………..…………………72 LBM Heuristics + Greedy Component ………………….....……………74 Problem Space Search Method…………………………………………..75 iii 3.5 Implementing the LBM Algorithm……………….………….………………77 3.6 Computation Complexity…………………………………………………….79 4 Test Problems and Computation Results………………………………………………82 4.1 Test Problems...………………………………………………………………82 4.2 Computational Results……………………………………………………….85 4.2.1 Performance Tests………………………………………………….85 Single Machine Test……………………………………………..87 Multiple Unidentical Machines…………………………………..88 Multiple Machines Identical Machines…………………………..92 Multiple Machines with Unidentical/Identical Machines………..95 More Resuls: LBM vs.CPLEX for Identical Machines………….98 4.2.2 Sensitivity and Robustness Tests…………………………….…...100 Results and Analysis for Unidentical Multiple Machines……...101 Results and Analysis for Identical Multiple Machines….……...107 Results and Analysis for Unidentical/Identical Multiple Machines…………………………………………..….113 5 Actual Case Study and Results…………………………………………………….…120 5.1 Introduction to C.Y. Tech Co., Ltd…………………………………………120 5.2 Prepared Data and Information……………………………………………..124 Demand Data and Product Description…………………………………124 Process Information……………………………………………….........127 Pressing and Setup Time Data………………………………………….129 5.3 Existing Planning Method………………………………………………….130 iv 5.4 Results and Performance……………………………………………………131 5.5 Final Comments…………………………………………………………….134 6 Conclusions and Future Work…………………………………………………….….136 6.1 Conclusions…………………………………………………………………136 The Problem Addressed……………………………..………………….136 The Solution Strategy Used…………………………………………….136 Testing the Claims……………………………………………………...140 6.2 Future Works……………………………………………………………….145 Bibliography……………………………………………………………………….…...146 v List of Figures Figure 1.1: Auto Insertion Technology for PCBs………………………………………...2 Figure 1.2: Overall Production Planning of PCB: Decision/Information relationships….3 Figure 1.3: Relationships between three decision phases in PCB Assembly……………4 Figure 1.4 Typical Assembly Process for PCBs………………………………………….5 Figure 3.1 Conception of LBM-Based Feasible Solution Finder…………………..……72 Figure 3.2 Flow Process for LBM algorithm………………………………………...…..79 Figure 4.1 Average CPU Time between LBM and CPLEX for Unidentical Processes....89 Figure 4.2 Average CPU Time between LBM and CPLEX for Identical Processes…....92 Figure 4.3 Average CPU Time between LBM and CPLEX for Unidentical/Identical Processes…..………………………..…..…..……..95 Figure 4.4 Average Duality Gap between LBM and GRD for Problem Type A………102 Figure 4.5 Average Duality Gap between LBM and GRD for Problem Type B………103 Figure 4.6 Average Duality Gap between LBM and GRD for Problem Type C………104 Figure 4.7 Average Duality Gap between LBM and GRD for Problem Type D………105 Figure 4.8 Comparing Average Duality Gap between Problem Types and Sized Problem……..…………………..……………….106 Figure 4.9 Average Duality Gap between LBM and GRD for Problem Type A………108 Figure 4.10 Average Duality Gap between LBM and GRD for Problem Type B…..…109 Figure 4.11 Average Duality Gap between LBM and GRD for Problem Type C…..…110 Figure 4.12 Average Duality Gap between LBM and GRD for Problem Type D……..111 Figure 4.13 Comparing Average Duality Gap between Problem Types and Sized Problem………………………………112 vi Figure 4.14 Average Duality Gap between LBM and GRD for Problem Type A……..114 Figure 4.15 Average Duality Gap between LBM and GRD for Problem Type B…..…115 Figure 4.16 Average Duality Gap between LBM and GRD for Problem Type C…...…116 Figure 4.17 Average Duality Gap between LBM and GRD for Problem Type D..……117 Figure 4.18 Comparing Average Duality Gap between Problem Types and Sized Problem………………………….……118 Figure 5.1 Business Flow Chart of C.Y. Tech Co., Ltd………………………………...122 Figure 5.2 Process Flow Chart of Auto Insertion Technology……………………...….123 Figure 5.3 Layout of Printed Circuit Board Model RVD-164………………………….124 Figure 5.4 Axial Inserter 6292 VCD-DH6 Dual Head by Universal…………….……..127 Figure 5.5 Radial Inserter VC-5B by TDK……………………………………………..128 Figure 5.6 Axial Sequencer Machine by Universal…………………………………….128 Figure 5.7 Time Comparison of the Four Algorithms………………………………….132 Figure 5.8 Total Production Time: LBM v.s. Existing Method……………...…………133 vii List of Tables Table 3.1: The Procedure of LBM Algorithm………………………………………..….78 Table 4.1: Characteristics of Test Problem Designs……………………………………..84 Table 4.2 Results: Single Machine with identical processing and set up times…………87 Table 4.3 Results: Single Machine with unidentical processing and set up times………87 Table 4.4 Results: Problem Size 3×20×5…………………………………………….…..89 Table 4.5 Results: Problem Size 3×100×30………………………………………….…..90 Table 4.6 Results: Problem Size 4×100×30………………………………………….…..90 Table 4.7 Results: Problem Size 5×100×30……………………………………………...90 Table 4.8 Results: Problem Size 3×1000×100……………………………………….…..91 Table 4.9 Results: Problem Size 4×1000×100……………………………………….…..91 Table 4.10 Results: Problem Size 5×1000×100………………………………………….91 Table 4.11 Results: Problem Size 3×20×5……………………………………………….92 Table 4.12 Results: Problem Size 3×100×30……………………………………………93 Table 4.13 Results: Problem Size 4×100×30…………………………………………….93 Table 4.14 Results: Problem Size 5×100×30……………………………………………93 Table 4.15 Results: Problem Size 3×1000×100…………………………………….……94 Table 4.16 Results: Problem Size 4×1000×100…………………………………….……94 Table 4.17 Results: Problem Size 5×1000×100……………………………………….…94 Table 4.18 Results: Problem Size 3×20×5……………………………………………….96 Table 4.19 Results: Problem Size 3×100×30…………………………………………….96 Table 4.20 Results: Problem Size 4×100×30…………………………………………….96 viii Table 4.21 Results: Problem Size 5×100×30…………………………………………….97 Table 4.22 Results: Problem Size 3×1000×100………………………………………….97 Table 4.23 Results: Problem Size 4×1000×100…………………………………………97 Table 4.24 Results: Problem Size 5×1000×100………………………………………….98 Table 4.25 Results: Problem Size 5×1000×100……………………………………….…99 Table 4.26 Results: Problem Size 4×1000×100………………………………………….99 Table 4.27 Results: Problem Size 3×1000×100……………………………….…..……100 Table 4.28 Duality Gap between LBM and
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