Feasibility Study Gan Transistors Application in the Novel Split-Coils Inductive Power Transfer System with T-Type Inverter

energies

Article Feasibility Study GaN Transistors Application in the Novel Split-Coils Inductive Power Transfer System with T-Type Inverter

Viktor Shevchenko 1,* , Bohdan Pakhaliuk 1,2, Oleksandr Husev 1,3,*, Oleksandr Veligorskyi 1, Deniss Stepins 4 and Ryszard Strzelecki 2,*

1 Chernihiv Power Electronics Laboratory, BRAS Department, Educational-Scientiﬁc Institute of Electronic and Information Technologies, Chernihiv National University of Technology, 14039 Chernihiv, Ukraine; [email protected] (B.P.); [email protected] (O.V.) 2 Faculty of Electrical and Control Engineering, Gdansk University of Technology, 80-233 Gdansk, Poland 3 Power Electronics Research Group, Tallinn University of Technology, 12616 Tallinn, Estonia 4 Institute of Industrial Electronics and Electrical Engineering, Riga Technical University, 12/K1 Azenes Street, LV-1658 Riga, Latvia; [email protected] * Correspondence: [email protected] (V.S.); [email protected] (O.H.); [email protected] (R.S.); Tel.: +380-93-957-4211 (V.S.); +380-96-985-5012 (O.H.)

Received: 17 July 2020; Accepted: 28 August 2020; Published: 1 September 2020

Abstract: A promising solution for inductive power transfer and wireless charging is presented on the basis of a single-phase three-level T-type Neutral Point Clamped GaN-based inverter with two coupled transmitting coils. The article focuses on the feasibility study of GaN transistor application in the wireless power transfer system based on the T-type inverter on the primary side. An analysis of power losses in the main components of the system is performed: semiconductors and magnetic elements. System modeling was performed using Power Electronics Simulation Software (PSIM). It is shown that the main losses of the system are static losses in the ﬁlter inductor and rectiﬁer diodes on the secondary side, while GaN transistors can be successfully used for the wireless power transfer system. The main features of the Printed Circuit Board (PCB) design of GaN transistors are considered in advance.

Keywords: wireless power transfer; inductive power transmission; multilevel converter; AC-DC power converters; T-type inverter; GaN-transistors; electromagnetic coupling

1. Introduction Interest in inductive wireless power transmission is constantly growing due to the increasing interests of both low-power wireless chargers for mobile and wireless charging stations of medium and high power for electric bikes and electric vehicles. Such chargers transfer the electric energy wirelessly from primary to secondary inductor by means of inductive coupling [1]. Inductive wireless power transfer systems consist of a transmitting part (contains an inverter, compensation circuit and primary inductor) and a receiving part (receiving inductor, compensation circuit, rectiﬁer) [1]. The researchers have already analyzed the main possible topologies of compensation schemes, their advantages and disadvantages, and described the general recommendations for their implementation. It is well known that Wireless Power Transfer (WPT) systems have some limitations, such as short transmission distance(centimeters or dozens of centimeters at acceptable levels of transmission eﬃciency) [2,3], sensitivity to the exact positioning of the receiving coil relative to the transmission coil [2,4], size and cost of the system.

Energies 2020, 13, 4535; doi:10.3390/en13174535 www.mdpi.com/journal/energies Energies 2020, 13, x FOR PEER REVIEW 2 of 16

Among existing limitations, the issue of the size and cost of the WPT system is one of the most Energiesimportant.2020, 13Researchers, 4535 are still looking for the optimal system configurations and topologies2 of of 16 power converters that would best meet the above requirements. Different types of switches are utilized in the power electronics converters [5–8]. The conventionalAmong existingInsulated limitations, Gate Bipola ther Transistors issue of the (IGBTs) size and are cost gradually of the WPT going system out of is use one in of industrial the most important.circuits of ResearchersWPT systems are due still to looking their forlow the switching optimal systemcapability configurations [9]. The reverse and topologies blocking of voltage power converterscapability of that the would conventional best meet IGBT the is above very requirements.low; there are relatively large power losses [10]. It is well knownDi ffthaterent the types use of wideband switches are gap utilized semiconductors in the power (such electronics as GaN-transistors) converters [5 –instead8]. The of conventional classical Si Insulatedpower switches Gate Bipolarcan significantly Transistors reduce (IGBTs) the are power gradually losses goingthat lead out to of the use increasing in industrial of the circuits system of WPTefficiency systems or significantly due to their increase low switching switching capability frequency [9]. reducing The reverse size blockingof passive voltage elements capability [11–13]. ofIt theis advisable conventional to use IGBT GaN istransistors very low; for there T-type are topo relativelylogies large[5–8,14]. power The lossesGaN fe [10atures]. It isfast well switching, known thatlow parasitic the use of charges, wideband reverse gap semiconductorsconductivity with (such zero as recovery GaN-transistors) charge and instead low driving of classical power Si powerlosses switchesand dynamic can significantly losses; compared reduce theto Si-IGBTs power losses and that SiC-MOSFETs lead to the increasing [5,6,15–18], of thehigher system efficiency, efficiency low or significantlyparasitic output increase capacitance switching [16–18] frequency can be reducingachieved. sizeThe ofadvantage passiveelements of GaN over [11– Si13 is]. Itmostly is advisable visible toat higher use GaN frequencies transistors in for dynamic T-type losses topologies [15,19]. [5– However,8,14]. The the GaN conduction features fast losses switching, are comparable low parasitic with charges,the SIC semiconductors reverse conductivity [18,19]. with zero recovery charge and low driving power losses and dynamic losses;The compared main goal to Si-IGBTsof the article and SiC-MOSFETsis to study the [5 ,feasibility6,15–18], higherof GaN effi transistorciency, low application parasitic outputin the capacitanceproposed non-traditional [16–18] can be (non-classical) achieved. The WPT advantage system. This of GaN will be over based Si is on mostly the loss visible analysis at higherof the frequenciesmain components in dynamic of the lossescircuit. [15 ,19]. However, the conduction losses are comparable with the SIC semiconductorsThe paper, consisting [18,19]. of seven sections, proposes a new solution of the wireless power transfer systemThe based main on goal two of theparallel article single-phase is to study the T-type feasibility GaN-based of GaN invertors transistor (dual application T-type in inverter) the proposed with non-traditionaltwo transmitting (non-classical) coils on one ferrite WPT core system. (coupled This transmitting will be based inductances). on the loss The analysis case study of the system main componentsdescription and of the advantages circuit. of such solution are represented in Section 2 of the paper. According to previousThe paper,research consisting [20], more of than seven 70% sections, of the losse proposess in WPT a new systems solution for of various the wireless cases of power power, transfer loads systemand working based onfrequencies two parallel depend single-phase on semiconduc T-type GaN-basedtors and invertors inductors (dual [20,21]. T-type Therefore, inverter) withthe twocontribution transmitting of such coils parameters on one ferrite was coretaken (coupled into account transmitting in calculations inductances). in this paper. The case Confirmation study system of descriptionthe advantages and advantagesof the proposed of such solution, solution made are represented mainly by in power Section losses2 of the analysis, paper. Accordingdescribed toin previousSections 3–5. research Section [20 ],3 moreand 4 than proposes 70% of the the losses losses models in WPT of systems the GaN for transistors various cases and ofcoil power, inductors, loads andrespectively. working frequenciesSimulation dependand experimental on semiconductors verifica andtion inductors of the proposed [20,21]. Therefore, solution theis described contribution in ofSection such parameters5, with conclusions was taken and into list account of patents in calculations devoted to in the this proposed paper. Confirmation WPT system ofon the Section advantages 6 and of7, respectively. the proposed solution, made mainly by power losses analysis, described in Sections3–5. Sections3 and4 proposes the losses models of the GaN transistors and coil inductors, respectively. Simulation and2. Case experimental Study System verification Description of the proposed solution is described in Section5, with conclusions and list of patents devoted to the proposed WPT system on Sections6 and7, respectively. Figure 1 depicts the proposed circuit of a multi-level converter for WPT. The primary converter 2.consists Case Studyof a System full-bridge Description three-level T-type inverter connected to bidirectional auxiliary semiconductor switches. The GaN-based T-type inverter is first proposed for use in a WPT system togetherFigure with1 depicts two coupled the proposed inductors. circuit It provides of a multi-level a number converter of advantages for WPT. over The existing primary analogues. converter consistsThe of DC a full-bridgesource is applied three-level to the T-type T-type inverter inverter. connected The energy to bidirectional is transmitted auxiliary to the secondary semiconductor side switches.through the The primary GaN-based coils T-type with an inverter air gap is (Figure first proposed 1). The for output use in current a WPT is system rectified together by the with passive two coupledfull-bridge inductors. rectifier, Itfiltered provides and a supplied number of to advantages the load. over existing analogues.

Figure 1. ProposedProposed Inductive Inductive Power Power Transfer IPT converter.

Energies 2020, 13, 4535 3 of 16

The DC source is applied to the T-type inverter. The energy is transmitted to the secondary side through the primary coils with an air gap (Figure1). The output current is rectified by the passive full-bridge rectifier, filtered and supplied to the load. In the scheme, Vdc is the source of the input dc voltage; C1, C2—input capacitors; S1–S4—switches of the single-phase full-bridge inverter; S5, S6 and S7, S8—auxiliary bidirectional switches; Lprim1,2—coupled primaries inductances; Cprim1, Cprim2—primaries compensating capacitances; Lsec—secondary inductance; Csec—secondary compensating capacitance; D1–D4—bridge rectifier; Cf—filter capacitor; Lf—filter inductance; RL—output resistive load. First of all, the multi-level inverters have a number of advantages over conventional H-bridge inverters, including better Electromagnetic Compatibility EMC and higher efficiency [14,22–24], which are extremely important for wireless power transmission systems [24]. However, analysis of the existed publications shows that using of multi-level inverters for WPT systems are just at the beginning stage [25]. Each multi-level circuit has its advantages and disadvantages, but among these types, T-type has some advantages over other types: smaller size, simpler operation principles, lower THD, lower conduction losses and smaller number of semiconductors [10,14,23]. The most important advantage of T-type solution in the WPT application is that only half of dc-link voltage applied to the primary side coil which in turn reduces the primary inductance and size of the coil [14]. The equation (1) for calculating the primary inductance Lprim at SP compensation analytically confirms this fact [20]:

!2 8 V L L in , (1) Prim Sec 2 ≈ π knom Vout where Lsec-secondary side self-inductance, knom—nominal coupling, Vin and Vout—input and output voltages, respectively. Finally, the splitting of the transmitting coils will reduce the conduction and overall diameter of the primary inductance. The application of two coupled transmission coils of inductance on a single ferrite core reduces the total dimensions of the magnetic components on the primary side (and the losses in copper and ferrite). Multiple magnetic resonant coils lead to higher transmission efficiency and longer transmission distances [26]. In addition, the coupling coefficient between them is considered constant, which simplifies certain calculations of the system. Furthermore, this solution reduces the current through each coil. This leads to a lower overall resistance of the transmission coils, which, in turn, increases the Q factor and the energy transfer efficiency. It is expected that wireless power transmission systems based on of multi-coil circuits with GaN-based T-type inverters in the transmission part is a promising solution, joining the advantages of the parts which already existed. The proposed solution does not have any heatsinks, has reduced the size of primary coils and can be considered for industrial application. Such a system can be used directly in power supply systems for transmission on different power levels. Compensating capacitors are required to compensate the leakage inductance on the primary and secondary sides in the WPT systems. In this case, the possible distance between the coils increases [2]. Systems with Series-Parallel (SP) compensation work efficiently with a wide range of loads in addition to the advantages for middle-power and low-power applications and allow reducing dimensions of the receiver coil [20]. Series-Series (SS) compensation does not depend on the change of magnetic coupling and load. These compensation topologies are most widely used for wireless charging. This solution is very well investigated; its benefits and drawbacks are well known [2,27–29].

3. Losses Models of the GaN Transistors The main sequence of the calculations is presented in this section and Section5. Initially, the control signals and the shape of voltage and current signals in the inverter were derived from simulation and are used for calculations of power losses in semiconductors. Energies 2020, 13, x FOR PEER REVIEW 4 of 16

3.1. T-type Inverter Operation Mode

Two auxiliary switches S5 and S6 (Figure 1) are turned on in the T-type topology (Figure 2). Switching states and the voltage are shown for the 3-level T-type Neutral Point Clamped NPC inverter in Table 1 for Figure 1 (for one leg).

Table 1. Switching States and Voltage for the 3-Level T-Type NPC Inverter [23]. Energies 2020, 13, 4535 4 of 16 Level S1 S5 S6 S2 Voltage Positive (+) 1 1 0 0 +Vdc/2 3.1. T-type Inverter Operation ModeNeutral (N) 0 1 1 0 0 Negative (−) 0 0 1 1 −Vdc/2 Two auxiliary switches S5 and S6 (Figure1) are turned on in the T-type topology (Figure2). SwitchingFigure states 2 shows and the voltagecontrol aresignal shown sequence for the of 3-level the transistor T-type Neutral (shown Point for one Clamped phase), NPC the invertervoltage (inVInv Table) and1 forthe Figureinverter1 (for output one current leg). (IInv).

Figure 2. ControlControl signalsignal sequences sequences and and shapes shapes of of the the voltage voltage and and the currentthe current of the of IPT the converter. IPT converter. Static Staticlosses losses are calculated, are calculated, knowing knowing the current the current through through each transistor each transistor at a certain at a certain interval. interval.

3.2. Losses ModelTable of the 1. GaNSwitching Transistor States under and Voltage Compensation for the 3-Level Condition T-Type NPC Inverter [23].

It is well knownLevel that the conduction S1 lossesS5 are aS significant6 S2 componentVoltage to estimate the total losses in the transistorsPositive [19]. (+) In addition, 1 the dyna 1mic losses 0 in GaN 0 transistors+Vdc /should2 be taken into account. Neutral (N) 0 1 1 0 0 Negative ( ) 0 0 1 1 V /2 The total transistor power− losses are determined by the sum of the static− dc and dynamic losses [17]. Figure2 shows the control signal sequence= of the+ transistor (shown for one phase), the voltage PTotal PCond PDyn , (2) (VInv) and the inverter output current (IInv). where PCond–static losses (conduction losses), PDyn—dynamic losses. 3.2. Losses Model of the GaN Transistor under Compensation Condition The equation that determines the conduction losses (when the transistor is fully on) is as follows:It is well known that the conduction losses are a signiﬁcant component to estimate the total losses in the transistors [19]. In addition, the dynamic losses2 in GaN transistors should be taken into account. P = I + R , The total transistor power losses areCond determinedDrms by theDS (on sum) of the static and dynamic losses(3) [17 ]. where IDrms–rms current value through drain, RDS(on)—on-resistance of a transistor’s drain-source. PTotal = PCond + PDyn, (2) The current IDrms is determined at each interval (Figure 2) for the positive half wave as follows:

t 2 where PCond–static losses (conduction losses), 1PDyn—dynamic losses. I 2 = ()i sin(ωt) 2dt, The equation that determines the conductionS1S 5  m losses (when the transistor is fully on) is as follows:(4) T t1 2 where im—amplitude value of drain current,PCond = ωI—angularDrms + RDS frequency,(on), T—period. For the negative half (3) wave: where IDrms–rms current value through drain, RDS(on)—on-resistance of a transistor’s drain-source.

The current IDrms is determined at each interval (Figure2) for the positive half wave as follows:

Zt2 2 1 2 I = (im sin(ωt)) dt, (4) S1S5 T t1 Energies 2020, 13, 4535 5 of 16

where im—amplitude value of drain current, ω—angular frequency, T—period. For the negative half wave: ZT 2 1 2 I = (im sin(ωt)) dt. (5) S2S6 T t3 Two sections are deﬁned for the zero state (Figure2):

Zt1 Zt3 2 1 2 1 2 I = (im sin(ωt)) dt + (im sin(ωt)) dt. (6) S5S6 T T t0 t2

Currents are added from all sections and multiplied by the resistance of the transistor over a period of time due to (3) to calculate the conduction losses of the transistor. Total dynamic power losses [17]:

PDyn = PSW(on) + PSW(o f f ) + PG + Prcl + Poss + PRR, (7) where PSW(on) and PSW(oﬀ)—switching losses, PG—gate charge losses, Prcl—power loss due to the reverse conduction voltage through the body diode; PRR—reverse recovery loss; POSS—power loss due to the output capacitance. Gate charge power losses of a transistor:

PG = QG + Vdr fsw, (8) where QG—total gate charge of a transistor, Vdr—driving voltage, fsw—switching frequency. The equations show, that charge losses are increasing at high switching frequency. Reverse recovery loss is caused by the charge stored in the junction of the internal body diode of a transistor in the T-type inverter [19]: V P = Q In f , (9) RR RR 2 sw where QRR is the reverse recovery charge, Vin—input voltage of the inverter. In the transistor datasheet, GaN transistors do not contain the internal body diode, so, reverse recovery loss is not present in these devices. Power losses due to the output capacitance [17] are the following:

ZVin POSS = fsw (VDSCOSS(VDS))dvDS, (10) 0 where COSS—output capacitance of the transistor (determined by the dependencies in the datasheet). These losses are independent of power and are insigniﬁcant at the increase of power, but the contribution of this type of losses is signiﬁcant at low power and high switching frequency. The power losses due to the reverse conduction voltage through the body diode (or dead-time losses):

Prcl = VREVIDtdead fsw, (11) where tdead—length of the dead-time (reverse diode conduction time), VREV—reverse voltage drop in a GaN transistor. The exact equations from [17,19], take into account several values (values of switching time, level of corresponding voltages, etc.) from the simulation data or the experimental data. It is not possible to accurately determine the switching time of the transistors from the model in PSIM and at high frequency. The approximate switch-on time is 4.9 ns, the switch-off time is 3.4 ns according to the Energies 2020, 13, 4535 6 of 16 datasheet. At the same time, the duration of the on- and off-transistors of each of the shoulders in the model is much larger. Therefore, a simplified equation is used to estimate the magnitude of switching losses quantitatively [18]: Turn-on switching losses of a transistor:

tZ_rise PSW(on) = (VDSID)dt, (12) 0

Turn-oﬀ switching losses of a transistor:

tZ_ f all PSW(o f f ) = (VDSID)dt, (13) 0 where trise and tfall—transistor’s time for turn-on and turn-off (values from datasheet), Vds—drain-source voltage, ID—drain current. According to [19], at frequencies below 100 kHz, switching losses of transistors are very low. Switching losses are increasing at frequencies up to 500 kHz but they have no significant effect on the total loss estimation [19]. Thus, most transistor losses are conduction losses and power losses due to the output capacitance.

3.3. Losses Model of Rectifier Diode Losses The losses in rectifying diodes are also significant, especially at high switching frequency and high current through diodes. The parameters of high-speed Schottky diodes were used for modeling and in the experimental verification. It is known that the static losses in a diode are determined by the current flow through the diode multiplied by the voltage drop across the diode. Two diodes simultaneously conduct current in the case of a diode bridge: PCond.D = 2I f orvVdrop, (14) where Iforv is the forward current value through the diode, Vdrop—voltage drop per diode. Dynamic losses in the diode are switching losses. All diodes in the diode bridge are involved in the process of rectification. If a QRR value (this is the reverse recovery charge) is given in the datasheet, then the equation is as follows: PSW_D = 4QrrVrev fsw. (15)

Reverse recovery charge value is deﬁned as a product of Cjunction (junction capacitance) by Vrev (the reverse voltage on the diode). The result in (16) is obtained by substituting this product into Equation (15): 2 PSW_D = 4VrevCjunction fsw. (16) The total losses in all semiconductors in this scheme are higher than the losses in the transmitting and receiving coils.

4. Design and Losses Models of Coils Inductors Coupled primary coils were calculated with a nominal value of 90 µH each and a receiving coil with a nominal value of 24 µH (Table2). Energies 2020, 13, 4535 7 of 16

Table 2. Parameter Table for Experiments.

Symbol Description Value

Vin Input voltage 300 V

S1-S8 GaN transistors GS66508T

Fsw Switching frequency 150; 200 kHz

Csn Snubber capacity 100; 470 pF

D1-D4 Rectifying diodes RB228NS100TL

Energies 2020, 13, x FOR PEERLprim1,2 REVIEW Primary inductances 90 µH 7 of 16

Lsec Secondary inductance 24 µH kk Coupling Coupling coefficient coeﬃcient 0.7; 0.9 0.7; 0.9

4.1. Design of the Transmitter and Receiver Coils 4.1. Design of the Transmitter and Receiver Coils The simulation was performed in almost the same order as described in [4]. The model of coils The simulation was performed in almost the same order as described in [4]. The model of coils was carried out in ANSYS Electrimagnetic Suite and designed using the Finite Elements Modeling was carried out in ANSYS Electrimagnetic Suite and designed using the Finite Elements Modeling (FEM) method. The transmission coils are on the top and the receiving coil is on the bottom (Figure (FEM) method. The transmission coils are on the top and the receiving coil is on the bottom (Figure3). 3).

Figure 3. Designed model of coils for WPT. Figure 3. Designed model of coils for WPT.

The primaryprimary coilcoil consistsconsists of of two two coils coils connected connected in in parallel parallel at at one one lead. lead. One One end end of of the the coil coil pins pins is drawnis drawn through through a holea hole in in the the ferrite. ferrite. They They do do not not interfere interfere with with the the coils coilsas asclose close asas possiblepossible toto eacheach other andand dodo not not distort distort the the magnetic magnetic flux flux with with this this solution. solution. Both Both primary primary coils coils have have equal equal turns turns each. Theyeach. areThey arranged are arranged in two layers,in two onelayers, above one the above other. th Thise other. solution This reducessolution losses reduces in copper losses andin copper ferrite and alsoferrite the and total also dimensions the total dimensions of the magnetic of the components magnetic components on the primary on the side. primary Multiple side. magnetic Multiple resonantmagnetic coilsresonant lead tocoils higher lead transmissionto higher transmission efficiencies efficiencies and longer and transmission longer transmission distances. distances. The secondary coil consists of double turns (shown in the figurefigure withwith anan enlargedenlarged fragment)fragment) inin one layer. Coil Coil winding winding with with double double turns turns reduces reduces the the coil’s coil’s own own resistance resistance at the at thesame same value value of the of theinductance inductance itself itself and and increases increases the the quality quality factor factor.. It Itincreases increases also also the the maximum maximum current current that thethe secondary coilcoil misses.misses.

4.2. Losses Model of the Coils Inductors underUnder CompensationCompensation ConditionCondition Certain simpliﬁcationssimplifications are allowed in in the the calculations calculations of of losses losses in in the the inductors. inductors. It Itis isquite quite a acomplex complex mathematical mathematical problem problem to to determine determine the the core core losses losses and and eddy current losses, especiallyespecially includingincluding thethe skin skin and and proximity proximity eﬀects effects of inductors of inductors [30].It [30]. is not It always is not possiblealways topossible achieve to acceptable achieve accuracyacceptable of accuracy calculations of calculat even whenions thoseeven losseswhen arethose determined. losses are Thedetermined. challenges The are challenges caused by theare complexcaused by physical the complex nature physical of these nature phenomena. of these phenomena. The core is mainly intended for shielding the magnetic induction flux in the WPT system [4]. Losses in the core are determined by the modified bulky Steinmetz equation at non-ideal sinusoidal voltage [20,30]. However, it is difficult to determine the ferrite coefficients for the equation since an experimental procedure is needed for a specific material under right conditions with high quality equipment. These factors are given rarely by the manufacturer. Therefore, determination of the value of core losses by other methods for this material is not accurate and has no scientific validity. Most of the available FE tools do not support Litz wire modeling. In addition, magnetic field H differs from turn to turn at determining the proximity effect [4]. Hence, H must be evaluated in the center of each turn individually to calculate the proximity loss for each turn [20]. Conduction losses are usually added to this value at determining a skin effect [20,30]. The Litz wire reduces the skin effect and proximity effect significantly. Furthermore, the proximity effect is minimal between the transmitting and the receiving coils due to the large air gap.

Energies 2020, 13, 4535 8 of 16

The core is mainly intended for shielding the magnetic induction flux in the WPT system [4]. Losses in the core are determined by the modified bulky Steinmetz equation at non-ideal sinusoidal voltage [20,30]. However, it is difficult to determine the ferrite coefficients for the equation since an experimental procedure is needed for a specific material under right conditions with high quality equipment. These factors are given rarely by the manufacturer. Therefore, determination of the value of core losses by other methods for this material is not accurate and has no scientific validity. Most of the available FE tools do not support Litz wire modeling. In addition, magnetic field H differs from turn to turn at determining the proximity effect [4]. Hence, H must be evaluated in the center of each turn individually to calculate the proximity loss for each turn [20]. Conduction losses are usually added to this value at determining a skin effect [20,30]. The Litz wire reduces the skin effect and proximity effect significantly. Furthermore, the proximity effect is minimal between the transmitting and the receiving coils due to the large air gap. The value of DC conduction losses is sufficient to understand the effect of the geometrical parameters of the coils on the losses value in transistors and coils. Conduction (ohmic) losses in the primary coils:

2 PLprim12 = ILprim_rms (2RLprim), (17) where ILprim_rms—current through primary coils; RLprim—resistance of one primary coil. Both paired transmitting coils are the same and have the same resistance in this case. Conduction losses in the secondary coil are as follows:

2 PL sec = IL sec _rms RL sec, (18) where ILsec_rms—current through the secondary coil. Power losses in the primary coils mostly depend on the inverter current, together with the own resistance of the primary coil.

5. Results of Experiments and Simulation An experimental model was made to check the feasibility of using GaN transistors in the described scheme (Figure4). Transistors GS66508Twere used with maximum drain current of 30 A, maximum drain-to-source voltage 650 V, drain-to-source on resistance at 25 ◦C equal to 50 mΩ. The transistor has zero reverse recovery loss, fast fall and rise times, low inductance and low thermal resistance in a small package. The GS66508T is a top-side cooled transistor that offers very low junction-to-case thermal resistance. Transistors are located at the bottom of the Printed Circuit Board (PCB) without additional radiators. These features combine to provide very high efficiency of power switching. The PCB consists of four copper layers, divided into signal and power parts. In the signal part of the board top and bottom layers are devoted for signal traces and internal layers for power supply voltage and ground polygons. In contrast, all layers, external as well as internal, are used for power traces. Some special techniques were used on the PCB aiming increase the efficiency and decrease power losses. First of all, high-current power traces were repeated on all four layers and stitched with via matrix to reduce parasitic resistance of such traces. GaN transistors, as it was mentioned above, were placed on the bottom side of the board in accordance to the producer’s recommendations [31]. Taking into account that GaN transistors can operate on high frequencies, EMC considerations was implemented on the board. Image of the bottom side of the board with power GaN transistors and other components of one half of T-type circuit is shown on Figure5. It should be noted that component designators on Figure5 corresponds to designators on Figure1. Highlighted components representing current flow in the circuit for switching states marked as “Positive (+)” in the Table1. As it can be seen, such placement of the components on PCB provides as low as possible square of current loops. Energies 2020, 13, 4535 9 of 16 Energies 2020, 13, x FOR PEER REVIEW 9 of 16

Figure 4. Experimental laboratory GaN-based WPT system: ( 1))—primary—primary side Printed Circuit Board (PCB); (2(2)—transmitting)—transmitting and and receiving receiving coils; coils; (3)—secondary (3)—secondary side PCB; side ( 4PCB;)—electronic (4)—electronic dc load; (5dc)—GaN load; (transistors5)—GaN transistors located on located the bottom on th ofe bottom the primary of the PCB. primary PCB.

Figure 5. Bottom side of the power part of primary PCB.

The similarsimilar square square of of current current loops loops on PCBon arePCB also are provided also provided for other for switching other switching states, presented states, presentedin the Table in1. the Therefore, Table 1. such Therefore, small squares such small of the squares current of loops the current in all possible loops in operation all possible modes operation of the modesinverter of provide the inverter low electromagnetic provide low electromagnetic interferences ofinterferences the power converter, of the power improving converter, EMC improving of WPT. EMCThe of WPT. experiments were performed at a distance between the coils of 1 cm (coupling coeﬃcient = 0.9) and atThe a distance experiments of 2 cm were (k = performed0.7)—Table at2. a The distance dependences between of the the coils output of parameters1 cm (coupling on the coefficient operating = 0.9)frequency and at (150 a distance and 200 of kHz) 2 cm were (k =investigated 0.7) –Table 2. at The diﬀerent dependences load resistances of the output for each parameters of these distances. on the operating frequency (150 and 200 kHz) were investigated at different load resistances for each of these distances. A wirewound resistor was connected for power distribution since the available electronic load has a maximum power of 300 W.

Energies 2020, 13, x FOR PEER REVIEW 10 of 16 Energies 2020, 13, 4535 10 of 16 Combinations of the two frequencies described above and the two coupling coefficients were investigated. Figure 6, for example, shows the cases at a coupling coefficient of 0.7. A wirewoundFigure 6 resistorshows wasthat, connectedin general, for the power efficiency distribution in the sincemodel the was available slightly electronic higher than load hasin the a Energies 2020, 13, x FOR PEER REVIEW 10 of 16 maximumexperiments. power However, of 300 W.the experimental efficiency also reached more than 90%. The unevenness of Combinations of the two frequencies described above and the two coupling coeﬃcients were the experimentalCombinations graphs of the twois explained frequencies by describedthe fact that above the andvoltage the intwo the coupling grid can coefficients vary constantly were investigated. Figure6, for example, shows the cases at a coupling coe ﬃcient of 0.7. investigated.during the experiment, Figure 6, for while example, in the shows model, the the cases desired at a valuecoupling is specified. coefficient of 0.7. Figure 6 shows that, in general, the efficiency in the model was slightly higher than in the 96 500 100 400 experiments.94 However, the experimental efficiency450 also reached more than 90%. The unevenness of 350 92 400 95 the experimental90 graphs is explained by the350 fact that the voltage in the grid can vary constantly300 during88 the experiment, while in the model, 300the desired90 value is specified. 250 86 250 200 84 200 85 150 Efficiency,% 82 150 Efficiency,%

96 500 power,W Output 100 400100 power,W Output 9480 450100 80 78 50 35050 92 400 95 9076 3500 75 3000 88 5 10122123253050100300 90 5 1315182123253050100250 86 Load resistance,Ω 250 Load resistance,Ω 200 84 Efficiency (experiment) Efficiency (model) 200 85 Efficiency (experiment) Efficiency (model) 150 Efficiency,% 82 150 Efficiency,% Output power,W Output Output power (experiment) Output power (model) Output power (experiment) Output power (model)100 power,W Output 80 100 80 78 50 50 76 0 75 0 FigureFigure5 6. 101221232530501006. Experimental and and simulation simulation dependencies dependencies at at 5the the 1315182123253050100load load resistance resistance variable variable at atk =k 0.7:= 0.7: (a) Load resistance,Ω Load resistance,Ω (aefficiency)Efficiency eﬃciency (experiment) and and output output power powerEfficiency on on the the (model) load load resistance resistance for f Efficiency= 150150 kHz;(experiment) kHz; ( b) eefficiencyﬃciency andandEfficiency outputoutput (model) power power ononOutput the the loadpower load (experiment) resistance resistance for forf f= =Output 200200 kHz. kHz.power (model) Output power (experiment) Output power (model)

FigureThe investigated6 shows that, maximum in general, transmitted the e fficiency power in was the 360 model W during was slightly the experiment higher than under in thethe Figure 6. Experimental and simulation dependencies at the load resistance variable at k = 0.7: (a) experiments.operating frequency However, of the200 experimentalkHz and load e resistancefficiency also of 15 reached Ω (Figure more 6b). than The 90%. measured The unevenness temperatures of efficiency and output power on the load resistance for f = 150 kHz; (b) efficiency and output power the experimental graphs is explained by the fact that the voltage in the grid can vary constantly during are shownon the load in Figure resistance 7. The for ftemperature = 200 kHz. on the transistors surface and coils has almost not changed the(40 experiment, °C and 42 while°C, respectively) in the model, during the desired a long-ter valuem is operation specified. of the circuit at this power. This indicatesThe investigatedinvestigated to the power maximum reserve in transmittedthese elements power (they was can 360withstand W duringduring more thethe power). experimentexperiment The temperature underunder thethe operatingincreased frequency to 89 °C on ofof 200the200 rectifier kHzkHz andand diodes. loadload resistanceresistance Obviousl ofofy, 1515 the ΩΩ losses (Figure(Figure in6 6b). b).the The Thediodes measuredmeasured are thetemperatures temperatures largest of the arewhole shownshown scheme, inin FigureFigure which7 7.. TheThe confirms temperaturetemperature the power onon thethe losses transistorstransistors calculations. surfacesurface andandThe coils coilsheatin hashasg almostalmosttemperature notnot changedchanged can be (40(40reduced ◦°CCand and by 42 42using◦C, °C, respectively) arespectively) larger radiator during during or a long-termforced a long-ter air operationcooling.m operation As of thea conclusion,of circuit the atcircuit this the power. atdiode this This lossespower. indicates are This the toindicatesmain the powerlimitation to the reserve power factor in thesereserveof the elements further in these switching (they elements can withstandfrequency (they can more increasing.withstand power). more The power). temperature The temperature increased to 89increased◦C on the to rectifier89 °C on diodes. the rectifier Obviously, diodes. the Obviousl losses iny, the the diodes losses arein the the diodes largest ofare the the whole largest scheme, of the whichwhole confirmsscheme, thewhich power confirms losses the calculations. power losses The heatingcalculations. temperature The heatin cang be temperature reduced by usingcan be a largerreduced radiator by using or forced a larger air radiator cooling. Asor forced a conclusion, air cooling. the diode As a losses conclusion, are the the main diode limitation losses factor are the of themain further limitation switching factor frequency of the further increasing. switching frequency increasing.

Figure 7. Pictures from the thermal camera at RL = 15 Ω, k = 0.7, f = 200 kHz, Vin = 300 V: (a) transistors temperature; (b) coils temperature; (c) temperature of rectifying diodes.

Large coupling coefficients has been studied to obtain more power (Figure 8). Higher power with a larger duty cycle is of course due to the longer time when the transistors are open and Figure 7.7. Pictures fromfrom thethe thermalthermal camera camera at atR RL L= = 1515 ΩΩ,, kk= = 0.7,0.7, ff == 200 kHz,kHz, VVinin = 300300 V: V: ( a) transistors conducting.temperature;temperature; The (( bbduration)) coilscoils temperature;temperature; of the zero ((cc) )voltage temperaturetemperature level of ofis rectifying rectifyingminimal diodes. diodes.under such conditions (Figure 9). The change in the duty cycle has little effect on the efficiency. The dead-time of the transistors was selectedLarge taking couplingcoupling into coe accountcoefficientsﬃcients the has maximumhas been been studied studied efficiency to obtainto ofobtain energy more more powertransf powerer. (Figure Dead-time (Figure8). Higher 8). in Higher the power transistors power with awithwas larger seta larger dutyless than cycle duty 5% is cycle ofof coursethe is period. of duecourse to the due longer to th timee longer when time the transistorswhen the aretransistors open and are conducting. open and conducting. The duration of the zero voltage level is minimal under such conditions (Figure 9). The change in the duty cycle has little effect on the efficiency. The dead-time of the transistors was selected taking into account the maximum efficiency of energy transfer. Dead-time in the transistors was set less than 5% of the period.

Energies 2020, 13, 4535 11 of 16

Energies 2020, 13, x FOR PEER REVIEW 11 of 16 The duration of the zero voltage level is minimal under such conditions (Figure9). The change in the 100 500 95 80 duty cycle90 has little effect on the effi450ciency. The dead-time of the transistors was selected taking into 70 80 400 90 account70 the maximum efficiency of350 energy transfer. Dead-time in the transistors60 was set less than 5% Energies60 2020, 13, x FOR PEER REVIEW 300 85 50 11 of 16 of the50 period. 250 40 40 200 Energies 2020, 13, x FOR PEER REVIEW 80 30 11 of 16

Efficiency,% 30 150 Efficiency,%

100 500 power,W Output 20 20 100 7595 80 1090 50450 voltage,V Output 10 10080 500400 70 0 0 9590 80 9070 450350 70 060 0.1 0.3 0.5 0.7 0.9 70 8060 400300 9085 11.94 106.5 244.91 378.3 463.9 50 0.1 0.3 0.5 0.7 0.9 70 Duty cycle 350 60 50 250 Output power,W 40 Duty cycle 6040 Efficiency Output power 300200 50 8580 30

Efficiency,% 5030 250150 Efficiency,% 40

Output power,W Output 20 4020 200100 8075 30 voltage,V Output Efficiency,% 3010 15050 10 Efficiency,%

Output power,W Output 20 20 0 1000 7570 0 10 50 voltage,V Output 10 Figure 0.18. Experimental 0.3 0.5 0.7dependencies 0.9 at RL =11.94 10 Ω 106.5, k = 0.9, 244.91 f = 378.3150 kHz, 463.9 Vin = 3000.1 V: (a 0.3) efficiency 0.5 0.7 and 0.9 0 Duty cycle 0 70 0 Output power,W Duty cycle output0.1 powerEfficiency 0.3 on 0.5the duty 0.7Output cycle; 0.9 power (b) efficiency11.94 on 106.5 the output 244.91 378.3 powe 463.9r with the duty0.1 0.3cycle 0.5 change; 0.7 0.9(c) Duty cycle Output power,W Duty cycle output voltageEfficiency on the dutyOutput cycle. power

Figure 8. Experimental dependencies at RL = 10 Ω, k = 0.9, f = 150 kHz, Vin = 300 V: (a) efficiency and The shape of the signals in the experiment is shown in Figure 9 for one of the used cases. In Figureoutput 8. power Experimental on the duty dependencies dependencies cycle; (b) efficiencyat at RRLL == 1010 ΩonΩ, kthe, =k =0.9, output0.9, f =f 150 =powe150 kHz,r kHz, with Vin V= the in300= duty V:300 (a V:cycle) efficiency (a) change; eﬃciency and (c ) particular, the voltage at the output of the inverter (V_inv), the current through the primary coil andoutputoutput output power voltage power on on the onthe duty the duty duty cycle; cycle. cycle; ( b) efficiency (b) eﬃciency on the on theoutput output powe powerr with with the theduty duty cycle cycle change; change; (c) (I_prim_coil(outputc) output ),voltage the voltage voltage on onthe the (dutyV_sec_coil duty cycle. cycle. ) and current on the secondary coil (I_sec_coil) were recorded. The shape of the signals in the experiment is shown in Figure 9 for one of the used cases. In particular,The shape the ofvoltage the signals at the inoutput the experiment of the inverter is sh own(V_inv in), Figure the current 9 for onethrough of the the used primary cases. coilIn particular,(I_prim_coil the), the voltage voltage at (theV_sec_coil output) andof the current inverter on the (V_inv secondary), the current coil (I_sec_coil through) were the primaryrecorded. coil (I_prim_coil), the voltage (V_sec_coil) and current on the secondary coil (I_sec_coil) were recorded.

Figure 9. The waveforms on the primary and secondary sides at RL = 30 Ω, k = 0.9, f = 150 kHz, Vin = Figure 9. The waveforms on the primary and secondary sides at RL = 30 Ω, k = 0.9, f = 150 kHz, 300 V: (a) experiment; (b) simulation. Vin = 300 V: (a) experiment; (b) simulation.

The shape shape and of the the signals magnitude in the of experimentthe currents is and shown the voltages in Figure are9 for very one close. of the The used resonance cases. Figure 9. The waveforms on the primary and secondary sides at RL = 30 Ω, k = 0.9, f = 150 kHz, Vin = conditionIn particular, is fulfilled. the voltage at the output of the inverter (V_inv), the current through the primary coil Figure300 V: 9.(a )The experiment; waveforms (b )on simulation. the primary and secondary sides at RL = 30 Ω, k = 0.9, f = 150 kHz, Vin = (I_prim_coilThe300 V:influence (),a) the experiment; voltage of the ((V_sec_coil bsnubber) simulation. )capacity and current on the on thepower secondary and energy coil ( I_sec_coiltransfer )efficiency were recorded. was also investigatedTheThe shape shape experimentally and and the the magnitude magnitude (Figure 10). of of the the currents currents and and the the voltages voltages are are very very close. close. The The resonance resonance conditionconditionThe shape is is fulfilled. fulfilled. and the magnitude of the currents and the voltages are very close. The resonance 93 220 conditionThe influence is fulfilled. of the snubber capacity on the power and energy transferWithout snubbers effi (model)ciency was also The92 influence of the snubber capacity on the 200power and energy transfer efficiency was also 180 Without snubbers investigatedinvestigatedThe 91influence experimentally experimentally of the snubber (Figure (Figure capacity10 10).). on the power and energy transfer efficiency was also 160 Snubbers 100pF 90 Snubbers 470pF investigated experimentally (Figure 10). 140 89

Efficiency,% 93 Without snubbers (model) 120220 88 Without snubbers (model) Without snubbers power,W Output 200 9392 100220 87 Snubbers 100pF 180 WithoutWithout snubbers snubbers (model) 91 20080 92 Snubbers 470pF Snubbers 100pF 86 18060160 Without snubbers 9190 Snubbers 470pF 85 16040140 Snubbers 100pF 9089

Efficiency,% Snubbers 470pF 5 15202530354045100Without snubbers (model) 140120 15 20 25 30 35 40 45 100 88 89 LoadWithout resistance, snubbersΩ power,W Output 100 Load resistance,Ω Efficiency,% Without snubbers (model) 120 Snubbers 100pF 8887 Without snubbers power,W Output 80 Snubbers 470pF 100 86 Snubbers 100pF 87 8060 Snubbers 470pF Figure86 8510. Experimental and simulation dependencies 60at40 the load resistance variable at k = 0.9, f = 150 5 15202530354045100 15 20 25 30 35 40 45 100 85 40 kHz, Vin = 300 V: (a) efficiencyLoad resistance, onΩ the load resistance; (b) output power onLoad the resistance, loadΩ resistance. 5 15202530354045100 15 20 25 30 35 40 45 100 Load resistance,Ω Load resistance,Ω The snubber capacitance was designed to reduce voltage peaks when the transistor is turned on FigureFigure 10.10. ExperimentalExperimental and and simulation simulation dependencies dependencies at atthe the load load resistance resistance variable variable at k = at 0.9,k =f =0.9, 150 and off, especially at voltage levels close to critical. Snubber capacitors of different capacities were fFigurekHz,= 150 V 10. kHzin = Experimental 300, Vin V:= (300a) efficiency V: and (a) esimulationﬃ onciency the load on dependencies the resistance; load resistance; (atb) theoutput load (b) output power resistance poweron the variable onload the resistance. at load k = resistance.0.9, f = 150 alternately installed between the drain-source leads of the transistors. The addition of a small kHz, Vin = 300 V: (a) efficiency on the load resistance; (b) output power on the load resistance. snubberThe capacity snubber in capacitance the bridges was of thedesign T-typeed to scheme reduce hasvoltage almost peaks no wheneffect theon thetransistor energy is efficiency turned on (Figureand Theoff, 10a). snubberespecially The capacitanceeffect at voltage was more was levels designnoticeable closeed to to critical.with reduce an Snubber voltageincreasing peaks capacitors capacitor when of the value different transistor and capacitiesan is increasing turned were on operatingandalternately off, especially frequency installed at of voltagebetween the transistors. levels the drain-sourceclose to critical. leads Snubber of the capacitors transistors. of differentThe addition capacities of a weresmall alternatelysnubber capacity installed in thebetween bridges the of drain-source the T-type scheme leads ofhas the almost transistors. no effect The on additionthe energy of efficiency a small snubber(Figure capacity10a). The in effect the bridgeswas more of thenoticeable T-type schemewith an hasincreasing almost nocapacitor effect onvalue the andenergy an efficiencyincreasing (Figureoperating 10a). frequency The effect of thewas transistors. more noticeable with an increasing capacitor value and an increasing operating frequency of the transistors.

Energies 2020, 13, 4535 12 of 16

The snubber capacitance was designed to reduce voltage peaks when the transistor is turned on and off, especially at voltage levels close to critical. Snubber capacitors of different capacities were alternately installed between the drain-source leads of the transistors. The addition of a small Energiessnubber 2020 capacity, 13, x FOR in PEER the REVIEW bridges of the T-type scheme has almost no effect on the energy effi12ciency of 16 (Figure 10a). The effect was more noticeable with an increasing capacitor value and an increasing operatingThe distribution frequency ofof thelosses transistors. is shown at changing the load resistance for the case k = 0.7, f = 150k Hz, VThein = distribution300 V (Figure of losses11). The is shown circuit at model changing made the loadin PSIM resistance simulation for the is case ank exact= 0.7, copyf = 150 of kHzthe , experimental circuit. The data were taken from the model to calculate the losses in the circuit Vin = 300 V (Figure 11). The circuit model made in PSIM simulation is an exact copy of the experimental elements.circuit. The data were taken from the model to calculate the losses in the circuit elements.

9 8 7 6 5

Current,A 4 3 2 1 0 10 12 21 23 25 30 50 100 Load resistance,Ω

Input current Current through one primary coil Current through secondary coil Output current

35 30 25 Power losses in inductors Power losses in diodes 20 Power losses in transistors 15 Other losses

Power losses,W 10 5 0 10 12 21 23 25 30 50 100 Load resistance, Ω

20 Power losses in primary coils 15 Power losses in secondary coil Power losses in filter inductor 10 Power losses,W 5

0 10 12 21 23 25 30 50 100 Load resistance, Ω

FigureFigure 11. 11. CalculationCalculation of of power power losses at k = 0.7,0.7, ff == 150150 kHz, kHz, VVinin = =300300 V Vand and change change of of load load resistance: resistance: ((aa)) dependencies ofof currentscurrents through through elements elements on on the the load load resistance; resistance; (b) distribution(b) distribution of losses of losses by major by majorgroups; groups; (c) power (c) power losses losses in inductors. in inductors.

TheThe losses losses in in the the inductors inductors and and diodes diodes are are decreasing decreasing significantly signiﬁcantly with with an an increasing increasing resistance resistance (and(and hence hence with with a adecreasing decreasing current: current: see seeFigure Figure 11a. 11Evidencea. Evidence for this for is thisshown is shownin the charts in the (Figure charts 11b,c).(Figure Other 11b,c). losses Other are losses also aredecreasing also decreasing with increasing with increasing load resistance load resistance for the for same the samereasons. reasons. The total power losses in the transistor remain at approximately the same level in this case. It means that GaN transistors do not reach the maximum current, which they can pass through themselves. The losses distribution in the semiconductor and magnetic components of the circuit for the same case k = 0.7, f = 150 kHz, Vin = 300 V at a load resistance of 10 Ω and 50 Ω are compared in more detail in Figure 12. The static losses in the inductors and diodes are significant (predominant) (Figure 12a). The reason is that with less resistance there is more input and output current. The total

Energies 2020, 13, 4535 13 of 16

The total power losses in the transistor remain at approximately the same level in this case. It means that GaN transistors do not reach the maximum current, which they can pass through themselves. The losses distribution in the semiconductor and magnetic components of the circuit for the same case k = 0.7, f = 150 kHz, Vin = 300 V at a load resistance of 10 Ω and 50 Ω are compared in more detail in Figure 12. The static losses in the inductors and diodes are significant (predominant) (Figure 12a). TheEnergies reason 2020 is, 13 that, x FOR with PEER less REVIEW resistance there is more input and output current. The total calculated13 of 16 losses are 84% relative to other losses. This ratio is already 95% in Figure 12 that confirms the statement describedcalculated in losses [32]. are It can 84% be relative explained to other due losses. to a significant This ratio is decrease already in95% the in currentFigure 12 value that throughconfirms all elementsthe statement of the described circuit, especially in [32]. It the can output be explained current. due to a significant decrease in the current value through all elements of the circuit, especially the output current.

Total losses calculation (W) at load Power losses calculation at load resistance 10 Ω resistance 10 Ω 25 23.2 Primary coils Secondary coil 7.89 20 Filter inductor Conduction losses in transistors Dynamic losses in transistors 10.109 In inductors 15 Conduction losses in diodes In transistors Dynamic losses in diodes In diodes Other losses 9.9 10 7.89 Other losses losses,W Power 3.67 5 29.23 2.36 2.44 1.03 0.209 3.47 0 In inductors In transistors In diodes Other losses

Total losses calculation (W) at load resistance Power losses calculation at load resistance 50 Ω 50 Ω 3 0.32 2.44 2.42 2.5

2.709 2.213 2

1.5 1.3 In inductors In transistors 1 0.76 Power losses,W In diodes 0.5 0.289 0.32 Other losses 0.153 0.067 0 In inductors In transistors In diodes Other losses

Primary coils Secondary coil Filter inductor 2.507 Conduction losses in transistors Dynamic losses in transistors Conduction losses in diodes Dynamic losses in diodes Other losses

Figure 12. Power losses calculation at k = 0.7, f = 150 kHz, Vin = 300 V: (a) distribution of losses by Figure 12. Power losses calculation at k = 0.7, f = 150 kHz, Vin = 300 V: (a) distribution of losses by majormajor groups groups for for the the load load resistance resistance 10 10Ω Ω;(; b(b)detailed)detailed distribution distribution ofof losseslosses forfor thethe loadload resistanceresistance 10 Ω; (c)Ω distribution; (c) distribution of losses of losses by major by major groups groups for the for load the load resistance resistance 50 Ω 50;( dΩ)detailed; (d)detailed distribution distribution of losses of losses for the load resistance 50 Ω. for the load resistance 50 Ω.

TheThe current current in in the the secondary secondary coilcoil isis higher due to to the the lower lower resistance resistance in in the the secondary secondary coil coil and and thethe value value of of the the self-inductance self-inductance (turns (turns ratio). ratio). This This causes causes greater greater losses losses compared compared to to the the primary primary coils coils (Figures 12b and 12d). (Figure 12b,d). The effect of dynamic losses in the transistor is less noticeable with an increasing transmission The effect of dynamic losses in the transistor is less noticeable with an increasing transmission power. It means that the contribution of the transistor dynamic losses to the total power losses will power. It means that the contribution of the transistor dynamic losses to the total power losses will be be smaller (because they are almost constant due to the large value of Poss). smaller (because they are almost constant due to the large value of P ). The dynamic losses of the diode are not significant (Figure 12b,d).oss They are dependent on the changeThe dynamicof output lossesvoltage of and the the diode operating are not frequency significant according (Figure 12to b,d).the expression They are dependent(15) and do onnot the changedepend of on output the current. voltage and the operating frequency according to the expression (15) and do not dependIn on summary, the current. in this topology and these transistors, it is possible to obtain an efficiency of up to 95%In and summary, a power in greater this topology than that and shown these in transistors,this article. This it is possiblerequires very to obtain accurate an einstrumentsfficiency of for up to 95%measuring and a power data and greater more than careful that selection shown inof thisrectifier article. diodes. This requires very accurate instruments for measuring data and more careful selection of rectifier diodes. 6. Conclusions The paper analyzes the feasibility of utilizing of GaN transistor in the three-level T-type NPC inverter with two coupled transmitting coils for WPT. The promising T-type topology of the inverter was selected because of the advantages described in the paper over the classical solutions. To study the system operation, a detailed analysis of the calculation of static and dynamic losses in the transistors and rectifier diodes and static losses in the inductors was conducted. A series of

Energies 2020, 13, 4535 14 of 16

6. Conclusions The paper analyzes the feasibility of utilizing of GaN transistor in the three-level T-type NPC inverter with two coupled transmitting coils for WPT. The promising T-type topology of the inverter was selected because of the advantages described in the paper over the classical solutions. To study the system operation, a detailed analysis of the calculation of static and dynamic losses in the transistors and rectifier diodes and static losses in the inductors was conducted. A series of experiments followed, focused on changing different input and output parameters and calculated power losses in the magnetic components and semiconductors. It was established that the greatest losses have concentrated in the magnetic components and rectifying diodes. These losses are mainly of conduction nature, caused by the significant current through these elements. At the same time, the total losses in the transistors are the smallest compared to all other losses on the circuit elements, which shows that this transistor type is absolutely justified for wireless power transfer in this non-classical circuit. However, these transistors are more critical to overvoltage (surges) on the drain-source than other types of transistors. Due to this fact, the particular attention should be paid to PCB design. The overall energy transfer efficiency was 90% at the maximum experimentally investigated power of 360 W, which is at the level of industrial samples. The system showed excellent stability at different load resistances and changes in different parameters. At the same time, due to the T-type application, along with GaN transistors, this solution has reduced primary coil and does not have heatsink. It has great potential and can operate at higher power with greater efficiency of wireless power transfer.

7. Patents Ukrainian patent No. 142050 “Wireless power transfer system based on three-level T-type inverter and two coupled transmission coils”.

Author Contributions: Idea, supervising: O.H.; theoretical review and writing: D.S.; analytical calculations, simulations and final writing of paper: V.S.; PCB design: O.V.; software and the experiments: B.P.; final editing, revising: R.S. All authors have read and agreed to the published version of the manuscript. Funding: This research and paper was funded by Ukrainian Ministry of Education and Science (Grants No. 0117U007260 “A highly effective system for low-voltage charging of low-voltage accumulators” and No. 0118U003865 “High-efficient wireless power transfer systems based on new semiconductor converters topologies”) and Ukrainian-Latvian project (Grant No. 0119U102105 “Novel power electronics facilities for wireless power transfer”). Also it was supported by the Estonian Research Council grant PRG675. Acknowledgments: The authors would like to acknowledge the financial support of the Ukrainian Ministry of Education and Science (Grants No. 0117U007260 and No. 0118U003865) and Ukrainian-Latvian project (Grant No. 0119U102105). Conflicts of Interest: The authors declare no conflict of interest.

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