UNCLASSIFIED

REPORT NUMBER ,4 4C zO .- )'5 I/ 5

LEGAL NOTICE This report was prepared as an account of Government sponsored work. Neither the United States, nor the Commission, nor any person acting on behalf of the Commission: A. Makes any warranty or representation, expressed or implied, with respect to the accu- racy, completeness, or usefulness of the information contained in this report, or that the use of any information, apparatus, method, or process disclosed in this report may not infringe privately owned rights; or B. Assumes any liabilities with respect to the use of, or for damages resulting from the use of any information, apparatus, method, or process disclosed in this report. As used in the above, "person acting on behalf of the Commission" includes any em- ployee or contractor of the Commission, or employee of such contractor, to the extent that such employee or contractor of the Commission, or employee of such contractor prepares, disseminates, or provides access to, any information pursuant to his employment or contract with the Commission, or his employment with such contractor.

LECH~NELOGY DI

SERIAL

UNITED STATES ATOMIC ENERGY COMMISSION Technical Information Service Extension, Oak Ridge, Tennessee fCC

UNCLASSIFIED AEC COLLECTION Sc 1004-A(3-55) ---

w1MMM NEI;

.1aTHIS MEMORANDUM IS NOT TO BE RE - PRODUCED WITHOUT THE EXPRESS WRITTEN PERMISSION OF SANDIA COR - PORA TION.

119-57-14

TRANSISTORS Counters

Neith Pollard - 1413

ABSTRACT

Two transistor plug-in decade counters are described, one of which operates over the SCS-7 temperature range. A transistor digital scanner with storage and parallel readout is described. It utilizes one of the plug-in decades. A sim- ple design procedure for flip-flops is presented.

Work performed under AEC Contract AT-(29-1)-789.

metadc100780 May 29, 195' Case No. 416. 10 I 00 -i TABLE OF CONTENTS

Page

A 100-KC TRANSISTOR PLUG-IN DECADE COUNTER . 4 A 1.4-MC TRANSISTOR PLUG-IN DECADE COUNTER . 4 A TRANSISTOR DIGITAL SCANNER ...... 10 DESIGN PHILOSOPHY FOR TRANSISTOR COUNTERS . . 14 Typical Design for a Flip-Flop ...... 14 Frequency Response Considerations ...... 20 Triggering...... 20

LIST OF ILLUSTRATIONS Figure 1. External and internal views of a 100-kc transistor plug-in

decade counter ...... 5 2. Schematic diagram of a 100-kc transistor plug-in decade counter...... -...... 6

3. Counter sequence ...... 7 4. External and internal views of a 1.4-mc transistor plug-in decade counter 8 5. Schematic diagram of a 1.4-mc transistor plug-in decade counter . 9 6. Top, front, and bottom views of a transistor digital scanner. . . . . 11 7. Schematic diagram of a transistor digital scanner 12 8. Transistor digital scanner block diagram 13 9. Flip-flop circuit configuration...... 15 10. Transistor static curves...... 16

11. Flip-flop circuit ...... 17 12. Flip-flop circuit for two conditions of collector resistance...... 18 13. Composite characteristics for two temperatures ...... 19 14. Common-emitter output characteristic ...... 21

15. Pulse-routing diagrams ...... 21

497 002 3 TRANSISTORS Counters

A 100-KC TRANSISTOR PLUG-IN DECADE COUNTER

Photographs of the 100-kc decade are shown in Fig. 1. The package dimensions are roughly 1-1/2 x 2 x 5 inches. The schematic diagram is shown in Fig. 2. The circuit con- sists of four stages of bistable multivibrators (flip-flops) and two feedback circuits which artifically add six counts, thus.changing the scale-of-16 to scale-of-10. The input and cou- pling circuits each consist of two AC gates connected in parallel to provide proper pulse routing.

The counting sequence is as follows:

Positive input pulses having a minimum size of 1 volt versus 1 microsecond are counted in binary fashion through the 7th pulse. The 8th pulse sets a "1" in the 4th binary which then sets the 2nd and 3rd binary to "1", thereby adding a 2 and a 4 so that 8 counts look like 14. The 9th count looks like 15, and the 10th count resets all binaries to "0", causing a positive step to appear at the output. *The counting se juence is shown in Fig. 3.

To reset, the bases on the right-hand transistor of each flip-flop are momentarily grounded, turning on those transistors. This condition is defined as "0" condition. Of course, it is possible to use a negative supply also. In this case, those points marked "+" are re- turned to ground and those marked "ground" to B-. Reset would then be accomplished by returning the bases to B- rather than ground during reset.

The decade will operate over a supply voltage range of 2 to 35 volts and a temperature range of -90 to +1700F.

A 1.4-MC TRANSISTOR PLUG-IN DECADE COUNTER

Figure 4 shows external and internal views and Fig. 5, a schematic diagram of a de- cade counter which will respond to pulses having a repetition rate up to 1.4 mc.

The Sylvania 2N94A has an alpha cutoff frequency of 6 mc and a common emitter gain of approximately 10. Therefore its common emitter cutoff is about 600 kc. The flip-flop operation is pushed to twice this amount by employing emitter followers in the cross-coupling circuits from collector to opposite base. A better impedance match is obtained with a re- sultant unloading of the collectors and much faster switching times. The maximum resolution frequency of the counter is then determined as the point beyond which the loop gain is less than 1.

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Note: All transistors are type 2N123

Fig. 2 -- Schematic diagram of a 100-kc transistor plug-in decade counter IN t I I II I I I 1 I I I COUNTI1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0

10 VOLTS(IF B+L) OUT t I15VOLTS) CONDITIONOF EACHII' B I N A R Y 1O-

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Fig. 3 -- Counting sequence

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1 2K 0 06 2K 2K 03 04 2K 2K -07 Q8 2K 2 K 101 012 2K - 2K 0 016

5.1KH 5. 1K 5.1 K 5.5K -10 -10-- - 5.5K D3 D4 5.1K D 7 D 8 5.1 D II D12 5.1 D 15 Di K 014 -10 05 -10 02 ~~05 '10 06 09 013 -10 16K 16K 16K 16K 16 K 16 K 16 K 16K

100 100 100 100 100 100 100 100 55K IIK IIlK IIK _lK DS I 9 I D14 aI D2 D 013 20K 20K 20K 20K 20K 20K 20K 20K 0 9-:- 00 100 100 - 100::. 00 -10 10 -10 10 -10O 2 - -00

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PINS I56B 2 INPUT 01 THRU 016 ARE SYLVANIA 2N94A 3 >;-+I0 PIN 4 RESET DI THRU 058 ARE TRANSITRON T9 IMC-DECADE SCALER 9> - 10 PIN . 8 OUTPUT K - 1000 OHMS ALL CAPACITORS ALUES IN MICRO-MICROFARADS

Co Fig. 5 - - Schematic diagram of a 1.3-mc transistor plug-in decade counter Negative pulses are required to trigger the decade. The power supply requirements are +10 volts 2 and -10 volts 2.

The same feedback scheme is used as described for the 100-kc counter.

A TRANSISTOR DIGITAL SCANNER

Figure 6 shows top, front, and bottom views and Fig. 7, a schematic diagram of a counter and storage device. The device will count for a period of time governed by the "start" and "stop" commands and store a five-decade number (through 99, 999).

It will count pulses greater than 0. 2 volt in amplitude which have a repetition rate be- low 3. 5 kc. (The repetition rate is limited by stepping switches which constitute the last three decades.)

The first two decades are the 100-kc, plug-in counters described previously. There is no visual readout from these decades, but there is a relay sampling matrix connected to each.

The last three decades are stepping switches which provide their own storage and also drive Inditron numerical indicators which provide visual readout of the three most significant figures.

The specific application for which the scanner was developed is to count output pulses from a Geiger-Muller (g-m) tube for 1-minute periods and to provide contact closures so that the number stored can be punched automatically on IBM cards. The scanner was connect- ed in parallel with a commercial digital scanner for 10, 000 operations and showed exact agreement.

A block diagram of the transistor scanner is shown in Fig. 8.

The pulse standardizer shapes pulses generated by the g-m tube. Both the pulse width and pulse amplitude are determined by the pulse standardizer for all pulses generated by the g-m tube that have an amplitude greater than a preset threshold.

The amplitude of the pulses generated by the g-m tube depends on two things: 1. The time between impinging beta particles and 2. The size of the capacitance from the anode of the g-m tube to ground.

The time between impinging beta particles determines the amplitude of the g-m tube output pulses when the tube does not have a long enough time to recover between impinging beta particles. Therefore, an amplitude threshold is set so that there will be no difference between counts from one digitizer to the other.

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Fig. 6 -- Views of a transistor digital scanner /2- _. 1 + V 1SV + -45V A 6 C8 / PEjET BUS R - - -- A+15V OvC05 Rh2 82KRI 2N43A ol

C16 -+15V C3 4 +r5 4 C10 CII R24 8 250 62N430.01 I00.25 5430 15V OK -O- ---- 2 2 497 CI4 R26 RI SV 33OLUF 5 7 CR R22 30K 30 15K 029 IMEG J4C6-lRe 03BAKC 66 MI6 5 C2 754 I 21443 C100 i K 2N78 446 -R25 C1 C 6KV - 0 R27 02 03 04 UUF + ISOV R19 F4SIK 11000K 4 INPUT FROM -02. ,4 634 2 U3 K26 020 027 IN58 4 +5K 24A3 4iSV T5 411 2 34 9 112 13145 20 GEIGER R223 C2N123R N 567u8 16171819 22K_ 2N43A 6 C4_ MEG K6 2 24K 56 1-'1428 429 100 0 T .2 C 2 DECK B 2w C2 C13 100 -I DECK C E 3S HI- VOLTAGE R3 0.01 2K 2 4K 24 - R R23 1115 C +K 4V 0 K- 24 PIN4 +900V 470 -2C e22.44K 10 oK 15 36K MS UHF "+15V C +15+15V E +15V 30K ,13DECK2 WIPER6j NUMER CAL 2 NDCATOR I (BACK) +15V '- ( FRONT PANEL) Hl +150 21 +150 V

R16 R R17 KIS 3 6K 44W 00 RESET 2 w1 RESET C9 |1000 T 25+ 150 - K12 l R 87 TRRU R96 R65 C39 1_ 0.33 MEG EACH 25 DECK~~ ~C 1/2 w 14700 0 DEC K E K R 2 R58 74K 8R60 K9 R62 K7 R700756K2SPRN36

30K -3 30K 30K KS 53 3 30K3 30K 42R4 R49 30K 305i016 017 018 019 020 R32M -30K R5 3 K q}7 30K 3040 K250K 021 024 025 9 010 Ol 2N43 014 01565 06 0 7 08 09 442 2N43A A4343A348 7 READ 2N43A 2N43A 2N43A 2N43A 30 9 C27 R63 C2 R71 394

3 R543 39K C22 R524 R47 3919 0.01 1 39KC R 6 39K.001 R?39K 0.0 3 89K 39 C19 5IK 001 51K 3.8K 2 R33 9K Ci8 R38 39K i+1v +ISV +15v ;001 51K ~0 01 + 15V SIKI39KS01 3.5KV2W 6 + 1V.+15v 51K .KRITTKIH, 64 R67 610 HI +IV30K 30Kr10023' +15V V+5V . R41 47 022 Z3 i TOGGLE CR 012 0 i3 4 9679 80 .Ge INISS PIDGE 2N43A 2N 43A 484 CS3[9 DECK H l RLK L R69 R69 C30 RED SYO PRIMARY Ds DECK C- DECK E TO DECK_,000'S A- DECK H S.K 39K -0.0 AC RECPT. I5K 39K +.16 o K14 PN4 COLUMN EMMITTER - Tm INDITRON SUPPLY (BACK) C20 C21 + ON JONES STRIP R34 -100 400 0.12 - 50V 50V no's RELAY NOTES MEG 7- 6 DECKS A 6 H ON RELAYS 4K1 4 MOM -MICRO STAR ARE IDENTICAL TO DECKS COLUMN-E MI iFR 8 K12 COLUMN EMITTER ITE R COUNT IN93 NC L---...-

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Fig. 7 -- Schematic diagram of a transistor digital scanner OJT 12 INPUT IOO'S 1000'S 10 K'S IBS DECADE IOSDECAD DECADE DECADE IN PULSE DECAD E (PLUG- IN) (PLUG- IN) a a A STANDARDIZER STORAGE STORAGE STORAGE

START COUNT

I.SO'S VISUAL STOP SAMPLING SAMPLING COUNT MATRIX MATRIX READOUT

RESET T y READOUr wool,

PARALLEL READOUT TO IBM PUNCH

-45V SUPPLY FOR RELAYS

+ 15V 115 - SUPPLY FOR 60 "\L TRANSISTORS

I 220V SUPPLY FOR INDITRONS

Fig. 8 -- Transistor digital scanner block diagram

The coaxial cable that connects the g-m tube output to the pulse standardizer must have a particular length since coaxial cables have capacity and will attenuate the g-m output pulse. In order to standardize the count between units, one defined coaxial-cable length must be chosen.

The negative-going output pulse from the g-m tube is applied to the base of Q 1 through

the differentiating network C1 and R 1 . Q1 is an emitter-follower whose input impedance is

approximately 2. 5 megohms. The biasing network, R1 and R2 , holds Q1 near cutoff.

The negative-going pulse drives the base- negative which causes the emitter to follow the -

base within 0.2 volt of the base driving pulse. The negative-going pulse at the top of R2 is

applied to the base of Q 2 through the coupling networkC 2 and R3 . Q 3 is a pulse amplifier

Corrected 7/30/57 13 r'i 01? /6 whose gain is set approximately by the ratio of the collector-to-emitter circuit resistors.

The- inverted and amplified pulse is coupled from the collector of Q2 to the base of Q3 through the differentiating network, C3 and R6' 3 is a high-gain amplifier and also sets the thres- hold level by means of the emitter-base biasing arrangement. When a count is desired, relay

contacts connect the base of Q2 to ground through R6. The emitter bias is set by R8 and R so

that Q3 is in the off condition. R8 and R9 are adjusted so that a 250-millivolt pulse at the in- put of Q1 from the g-m tube will cause Q3 to conduct. The 250-millivolt threshold sensitivity is chosen so that vacuum tube and transistor digitizers may be compared.

When the positive pulse applied to the base of Q3 exceeds the bias voltage applied to the emitter, Q3 conducts. The pulse at the collector of Q3 is amplified and inverted. This negative-going pulse is applied to the base of Q4 , turning Q4 on. The collector of Q4 rises to +11.4 volts. The right-hand side of capacitor C6 which was initially at +11.6 volts rises with

the collector of Q4 to 23 volts. This action turns off the base-to-emitter diode of Q5 by 11.4 volts. Capacitor C6 charges through R1 1 , Q4 , and R1 5 until the base of Q5 reaches +11.6 volts. Q5 starts to turn on. The collector of Q5 rises toward +11. 6 volts turning the base of Q4 off. The collector of Q4 returns to ground potential. Capacitor 6 discharges through a low-impedance path, consisting of R 1 0 , base-emitter diode of Q5, and R 1 5, to its initial con- dition. The positive-going output pulse is taken from the collector of Q and routed to the in- put of the first decade counter. This output pulse is of fixed size and shape, independent of input, fora wide variation in input pulse shape.

Details of the relay sampling matrix are apparent from the schematic diagram, Fig. 8. The output from each binary of the decade is necessary to drive the matrix. An emitter follower, Q6 , for example, is used to isolate each matrix relay from the decade.

The main.virtue of the transistor scanner over the vacuum tube version is the reduction of power required and a resultant reduction in heat dissipation. The vacuum tube scanner has serial readout and requires external circuitry to switch its storage matrix from one decade to the next, greatly increasing readout time. The external circuitry also requires an addi- tional power .supply.

DESIGN PHILOSOPHY FOR TRANSISTOR COUNTERS

Typical Design for a Flip- Flop

The general circuit is shown in Fig. 9.

The object here is to have the "on" transistor held in conduction by bias voltages pro- vided by the "off" transistor. Likewise, the "off" side is held off by biases provided from the "on" side. If the "off" side is turned on, the opposite condition will prevail.

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Fig. 9 -- Flip-flop circuit configuration

Consider a flip-flop built around PNP transistors having a collector voltage rating of -45 volts, a common emitter gain of 50 at 5 ma, and a leakage current, ICOB' of 10 micro- amperes.

To hold a transistor in the nonconducting state, the base-emitter diode must be back- biased; i. e., base-positive with respect to emitter for a PNP. If only one supply voltage is to be used, it is then necessary to have the emitter potential below the most positive point in the circuit. This is done by inserting a resistor in series with the emitters. It is then pos- sible to drive the bases positive with respect to their emitters.

Since one or the other of the transistors is always conducting, a DC potential will exist across the resistor, R, in common with both emitters and can be held reasonably constant by connecting a bypass capacitor, C , in parallel with it. A crude criterion for C is that the R C product be long compared to a trigger-pulse length. e e A design center of 1-volt back bias insures adequate margin for wide variation in tran- sistors. Therefore, we shall design conservatively for a 2-volt drop across the emitter resistor at 5 ma. (One uses 5 ma because this is well within the rating of the transistor in question. )

2 ohms R e =-=4005

Since the collector voltage swing is approximately equal to the supply voltage less the emitter voltage, and a large swing is desirable, the emitter voltage should be kept reasonably low.

15 If we assume that the "on" transistor is saturated (collector positive with respect to base), then the emitter-to-collector voltage is less than 1/2 volt. The saturation voltage can be read directly from the transistor static curves (see Fig. 10).

SLOPE = RSAT

IC -- 5MA

VSAT. VC

Fig. 10 -- Transistor static curves

Therefore, using a negative supply, the collector of the "on" transistor is at VRe + the "on" VSAT below ground, or about -2. 5 volts. For a 15-volt supply, the drop across collector resistor is 15 - 2. 5 = 12. 5 volts. For Ic = 5 mils,

Ib = = 0. 1 mil B50 Insert a large safety factor here to insure sufficient base drive for saturation, say, 0.5 mil. Then, neglecting the forward drop across the emitter-base junction, Vb for the "on" transistor equals Ve = -2 volts.

Choose R large with respect to the emitter-base resistance, say, 10 k. Then IR =Ok = 0. 2 mil andlIR =b + IR = 0. 7 mil. b n b

R . Considering the "on" transistor Now determine c

- VSUPPLYVc _ 15 -2.5=2.4 K c=I +I 5.10 c RbOFF

Now determine RN.

c"OFF" = SUPPLY -Rc RN

= 15 - 2.4 x 0.70 = 13.3 volts

R = c"OFF" ~-Vb"ON" - 13.3 - 2.5 n RN 0.7

16 it The final circuit then appears as in Fig. 11.

2.4K 2.4K -13V .7MA -5V 0.1M 15K 15K t-2.5V '5MA OFF-IVON

I0 K 0.1 MA IOK

-2V 0.4 K -2V

Fig. 11 -- Flip-flop circuit

Check the cross-coupling circuit for the off base; IRN 25K = 0. 1 mil (Ib"OFF"=0). the VbOFF.= 0. 1 mil x 10 K = -1 volt. Since the off emitter is at -2 volts, Vbe = 1 volt, and transistor is turned solidly off.

This flip-flop is bistable. That is, the side which is turned on will continue to conduct until the other side is turned on.

The safety factor built into the base driving current should receive some comment here. One reason for a large safety factor is that the common-emitter current gain, B, is greatly reduced at saturation. It is not unusual for a transistor to have B reduced by a factor of 5 for saturation versus nonsaturation for the same collector current. The actual B can be exactly determined experimentally for a particular transistor. It is only necessary to obtain a set of static output characteristics and read off the ratio Ic to Ib'

If the flip-flop is to operate over some temperature range, then the most straight- forward design approach is the following. Consider the two conditions illustrated in Fig. 12: condition 1 for a collector resistance R and condition 2 for a collector resistance RL. The 1 2 two sets of common-emitter output characteristics are to the same scale and for the same transistor at the two extremes of the operating temperature range. Notice how the curves move away from the voltage axis as temperature increases. The implication is that the transistor gain increases as the temperature increases. Generally this is true. Also, the leakage current increases with temperatures (doubles every 100 C, approximately), which helps to bias the transistor on. As a result of these effects, the same base drive, Ib2, for example, yields considerably more collector current at high temperature than at low temperature.

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Fig. 12 -- Flip-flop circuit for two conditions of collector resistance o If the "on" and "off" base currents are Ib 3 and Ib1 , respectively, the flip-flop will not have two stable states for RL1 at high temperature, Al and Bl. Note that Ib 1, the base cur- rent for the "off" condition, is sufficient to saturate the transistor so the "off" condition, I. I point B1 , is the same as the "on" condition, point A 1 .

However, if the load is decreased to some value, RL2, two stable states, A and B , 2 2 2 will exist for Ib3 and Ib1 , respectively.

A simple summary of the above: choose the "on" collector current larger than the "off" collector leakage current at the upper temperature limit. The ratio, of course, will determine the output voltage swing, VC -VC ON COFF It is recommended that the output characteristics be obtained at the temperature limits as the first step in the design procedure. If the two sets of curves are superimposed on the same axes, Fig. 13, then the allowable range for the value of load, i. e. , collector, resistance will be apparent.

HI ON

LLOW ON

HI OFF

IC LOW OFF

Fig. 13 -- Composite characteristics for two temperatures

From Fig. 13, RL is the limit for the maximum value of RL because at high temper- atures, the "off" intercept is the same as the "on" intercept, point A. The minimum value of

RL is limited by1 the low 1temperature "on" condition, point B. An allowable range for RL is between R and RL The required output voltage swing will then determine whether or not Ltet a s s o nqe to il m e h p lc to e u r m n s the transistor in question will meet the application requirements.

19 Frequency Response Considerations

If the flip-flop is to be used at high frequency the first consideration is, of course, a good high-frequency transistor.

The 3-db frequency in a common emitter configuration is f /B. An SB-100 transistor having an fa of 30 megacycles and a B of 20 could not be expected to operate above 1. 5 mega- cycles in a standard flip-flop configuration.

Certain circuit modifications will result in improved high-frequency operation. These are:

1. Connecting capacitors in parallel with each cross-coupling resistor, RN. These capacitors allow large driving currents to flow during the initial stages of switching, which shortens the response time. 2. Reducing the tolerances for "on" and "off" conditions. For example, set the "off" base at a few tenths of a volt rather than at 1 volt. 3. Couple from collector to opposite base through emitter followers. This provides a better impedance match and greatly decreases switching time. 4. Limit the collector swing with clipping and clamping diodes. The clamping diodes limit the lower swing of VC so that saturation does not occur and t1, the hole-storage time, equals zero. The clipping diodes permit the use of a higher supply voltage than the transistor rating and thus shorten switching time.

The circuit of Fig. 14 includes all of these refinements.

Triggering

If the binary is to be used to divide by two from a single source, it is nec essary to pro- vide a routing scheme for the trigger pulses so that successive pulses will appear on alternate bases. The trigger is usually applied to the base for that is the most sensitive point.

Two AC gates connected together provide a simple pulse-routing scheme. Such a

scheme is shown in Fig. 15. The diode bias.resistors, R1 , cause the diodes to alternately block, then pass the trigger pulses, depending on the collector voltage state.

For PNP's, a positive pulse applied to the base of the "on" transistor will turn it off. Likewise, a-negative pulse applied to the base of the "off" transistor will tend to turn it on. The reverse is true for NPN's.

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Fig. 15 -- Pulse-routing diagrams

Corrected 7/30/57 21

9 7 220 If both positive and negative pulses are available frcmz the source, then the decision as to which to use will be based on whether one wants sensitivity or speed.

For maximum trigger sensitivity turn the "on" transistor off. This requires that the least trigger pulse amplitude for the "on" bias be only the forward voltage drop across the emitter-base diode, nominally 0. 1 to 0.2 volt.

For maximum switching speed, the "off" transistor should be turned on. This drives the transistor into an active conditon, i. e. , a gain greater than 1. The other transistor is already active so that- both transistors assist in switching.

NEITH POLLARD - 1413

Case No. 416. 10

22 . 1 1