DOCSLIB.ORG

Z3/EV Z3/EV Is One of the Experiment Boards That Constitute the Interactive Practical Electronics System – I.P.E.S

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Z3/EV Z3/EV Is One of the Experiment Boards That Constitute the Interactive Practical Electronics System – I.P.E.S INTRODUCTION Z3/EV Z3/EV is one of the experiment boards that constitute the Interactive Practical Electronics System – I.P.E.S. It consists of a set of components and circuits for performing BE (32 BIT experiments. The lessons included in this module can be developed in: MICROPROCESSORS) - Standard mode: using the switches of the equipment and consulting the handbook; -Computerized mode: the interactive software version of the handbook - SW-D-Z3/EV - interfaced to the module via Control Unit SIS3-U/EV, is used. This software inserts circuit variations and faults automatically enabling the development of lessons even without teacher’s assistance. Z3/EV The Z3/EV 32-bit microprocessor board is a system developed for studying the most advanced microprocessors, and their most important applications. It contains all typical components of microprocessor systems: the microprocessor, RAM, EPROM, digital and analog I/O devices, etc. The choice of the microprocessor used also on Personal Computers makes it a necessary educational equipment for studying the hardware and software structure of the Personal Computer. The instructions of the program to be carried out are usually entered from the keyboard and displayed on the module TRAINING PROGRAM: display. • Programming of 32-bit microprocessor systems: ELECTRONICS AND SYSTEMS When the complexity of the applications to be developed programming introduction, machine code and assembler increases, the system can be connected to a Personal Computer language programming, advanced programming; creating a Development System with the following phases: • 80386EX microprocessor; • Programs insertion into the PC in Assembler using a Text • Management control; editor; • Data and address bus; • Program compiling and linking for machine code transformation by the microprocessor; • Control bus; • Program transfer via serial or parallel interface into the • Instructions and address modes; RAM of the microprocessor; • Maskable and not-maskable interruptions; • Program debug phase directly on the microprocessor • RAM and EPROM interfacing; module with the same module hardware; • Keyboard and LCD display control • Transfer of the perfectly operating and completely PC • Parallel interface tested program to an EPROM programmer for the definitive programming of the EPROM and its insertion into • Serial interface the proper base of the microprocessor system • A/D and D/A conversion • PC communication The EPROM monitor contains all commands for programs execution and testing, and the control software for peripherals. The system is provided with test points for checking the signals and fault insertion possibility. -Z3-1 20B-E-BE ELETTRONICA VENETA S.P.A. - 31045 Motta di Livenza (TV) Italy - Via Postumia 16 - Tel. +39 0422 765 802 - Fax +39 0422 861 901 - E-mail: [email protected] BE 41 TECHNICAL SPECIFICATIONS: GENERAL FEATURES: • 32-bit microprocessor • Printed circuit with protective treatment and silk screen BE • 32-KB static RAM mimic diagram • 16-KB EPROM • Additional modules (optional boards) are available for • 8-bit parallel interface other applications • RS-232 serial interface • Keyboard with hexadecimal and function keys • LCD Display DEVELOPMENT SOFTWARE • Test points for Data Bus, Address Bus and Control Bus Program for editing, compiling, linking and parallel transmission • Analog-to-Digital converter from Personal Computer to board mod. Z3/EV. • Digital-to-analog converter • Monitor program in EPROM with commands for: – Data insertion/change in RAM – Register content display/change – I/O ports control – Continuous, stepper programs execution – Breakpoint control • Fault simulation • Test and interconnection points, Ø 2 mm • Jumpers for rapid circuit modification • 37-pin connector to the control unit • 8-wire connector to the power supply unit Dimensions: 386 x 248 x 40 mm It’s possible to connect and to experience the following mod. F04/EV application modules: F04-0/EV ELECTRONICS AND SYSTEMS F04-1/EV F04-2/EV F04-3/EV F04-4/EV F04-5/EV REQUIRED F04-6/EV PS1-PSU/EV POWER SUPPLY F04-7/EV POWER SUPPLY UNIT ±12 Vdc – 0.5A (see details from pag. EB53) - NOT INCLUDED - +5 Vdc – 2A SUPPLIED WITH STUDENT HANDBOOK: THEORY AND EXERCISES TEACHER HANDBOOK: WIRING DIAGRAMS AND SOLUTIONS OF EXERCISES OPTIONAL PERSONAL COMPUTER FAULT INSERTION UNIT SIS3-U/EV AND MULTIMEDIA SOFTWARE SW-D-Z3/EV -Z3-1 EPROM PROGRAMMER 20B-E-BE EPROM ERASER BE 42 ELETTRONICA VENETA S.P.A. - 31045 Motta di Livenza (TV) Italy - Via Postumia 16 - Tel. +39 0422 765 802 - Fax +39 0422 861 901 - E-mail: [email protected].
Load more

Recommended publications
  • Vax 6135 Car Vax Uk - Service Parts List
    VAX 6135 CAR VAX UK - SERVICE PARTS LIST Item Vax Part No. Description Price Code Service Item Item Vax Part No. Description Price Code Service Item 2 1-2-31-01-006 FILTER-FOAM-EXHAUST S1 CS 34 1-2-30-01-015 SEAL-FILTER/RESERVOIR K1 S 5 1-2-11-04-007 CABLE CLAMP L1 CS 35 1-3-15-03-007 FILTER HSG ASSY-UNIV-BLACK T3 S 29 1-2-31-01-002 FILTER DISC-BONDINI A1 CS 39 1-2-14-02-001 BALL VALVE N1 S 32 1-2-31-01-007 FILTER -FIBRE-MOULDED X1 CS 40 1-3-09-06-007 RESERVOIR ASSY-UNIV-BLACK W3 S 44 1-3-13-02-001 UPHOLSTERY TOOL Y1 CS 41 1-2-30-02-002 SEAL-CONICAL DUCT D2 S 47 1-2-39-01-010 CREVICE TOOL Y1 CS 42 1-2-30-02-003 SEAL-EXHAUST D2 S 48 1-3-13-01-001 DUSTBRUSH H2 CS 43 1-2-124731-12 RECOVERY BUCKET/SPIDER ASSY Z3 S 50 1-2-13-02-002 TUBE-EXTN-STAINLESS B3 CS 45 1-2-32-01-002 CASTOR-TWO WHEEL X1 S 52 1-3-18-01-022 HOSE & GRIP ASSY W3 CS 60 1-9-124423-00 TUBE-PUMP TO QRV A1 S 53 1-9-124962-00 WASH HEAD J3 CS 62 1-1-06-01-073 FEMALE QRV ASSY S2 S 54 1-9-124961-00 FLOOR BRUSH F3 CS 63 1-3-124422-00 ELBOW-QRV-ET408 C2 S 64 1-2-11-03-007 RETAINER CLIP-SPRING H1 CS 65 1-2-13-04-008 INLET TUBE-PVC A1 S 74 1-2-124594-00 UPHOLSTERY WASH TOOL K3 CS 66 1-3-124424-00 FIXING STRAP-ET408 L1 S 75 1-9-125226-00 TURBO TOOL-100mm R3 CS 67 1-7-124677-00 FILTER-WATER-INLET E2 S 77 1-9-125549-00 CREVICE TOOL-EXTRA LONG G2 CS 68 1-5-124419-00 PUMP-ET408 S3 S 101 1-2-124805-00 WATER TUBE ASSY-STRAIGHT Z2 CS 69 1-6-124425-00 SEAL-PUMP ET408 L1 S 3 1-3-124588-03 COVER-ACCESS-B R GREEN X1 NS 99 1-2-07-03-001 DUCT-CONICAL X1 S 6 1-2-36-04-004 CORD PROTECTOR A1 NS 102
    [Show full text]
  • CS 6290 Chapter 1
    Spring 2011 Prof. Hyesoon Kim Xbox 360 System Architecture, „Anderews, Baker • 3 CPU cores – 4-way SIMD vector units – 8-way 1MB L2 cache (3.2 GHz) – 2 way SMT • 48 unified shaders • 3D graphics units • 512-Mbyte DRAM main memory • FSB (Front-side bus): 5.4 Gbps/pin/s (16 pins) • 10.8 Gbyte/s read and write • Xbox 360: Big endian • Windows: Little endian http://msdn.microsoft.com/en-us/library/cc308005(VS.85).aspx • L2 cache : – Greedy allocation algorithm – Different workloads have different working set sizes • 2-way 32 Kbyte L1 I-cache • 4-way 32 Kbyte L1 data cache • Write through, no write allocation • Cache block size :128B (high spatial locality) • 2-way SMT, • 2 insts/cycle, • In-order issue • Separate vector/scalar issue queue (VIQ) Vector Vector Execution Unit Instructions Scalar Scalar Execution Unit • First game console by Microsoft, released in 2001, $299 Glorified PC – 733 Mhz x86 Intel CPU, 64MB DRAM, NVIDIA GPU (graphics) – Ran modified version of Windows OS – ~25 million sold • XBox 360 – Second generation, released in 2005, $299-$399 – All-new custom hardware – 3.2 Ghz PowerPC IBM processor (custom design for XBox 360) – ATI graphics chip (custom design for XBox 360) – 34+ million sold (as of 2009) • Design principles of XBox 360 [Andrews & Baker] - Value for 5-7 years -!ig performance increase over last generation - Support anti-aliased high-definition video (720*1280*4 @ 30+ fps) - extremely high pixel fill rate (goal: 100+ million pixels/s) - Flexible to suit dynamic range of games - balance hardware, homogenous resources - Programmability (easy to program) Slide is from http://www.cis.upenn.edu/~cis501/lectures/12_xbox.pdf • Code name of Xbox 360‟s core • Shared cell (playstation processor) ‟s design philosophy.
    [Show full text]
  • MPC5634M Microcontroller Data Sheet, Rev
    Freescale Semiconductor MPC5634M Rev. 9.2, 01/2015 MPC5634M Microcontroller Datasheet This is the MPC5634M Datasheet set consisting of the following files: • MPC5634M Datasheet Addendum (MPC5634M_AD), Rev. 1 • MPC5634M Datasheet (MPC5634M), Rev. 9 © Freescale Semiconductor, Inc., 2015. All rights reserved. Freescale Semiconductor MPC5634M_AD Datasheet Addendum Rev. 1.0, 01/2015 MPC5634M Microcontroller Datasheet Addendum This addendum describes corrections to the MPC5634M Table of Contents Microcontroller Datasheet, order number MPC5634M. 1 Addendum List for Revision 9 . 2 For convenience, the addenda items are grouped by 2 Revision History . 2 revision. Please check our website at http://www.freescale.com/powerarchitecture for the latest updates. The current version available of the MPC5634M Microcontroller Datasheet is Revision 9. © Freescale Semiconductor, Inc., 2015. All rights reserved. 1 Addendum List for Revision 9 4 Table 1. MPC5634M Rev 9 Addendum Location Description Section 4.11, “Temperature In “Temperature Sensor Electrical Characteristics” table, update the Min and Max value of Sensor Electrical “Accuracy” parameter to -20oC and +20oC, respectively. Characteristics”, Page 81 2 Revision History Table 2 provides a revision history for this datasheet addendum document. Table 2. Revision History Table Rev. Number Substantive Changes Date of Release 1.0 Initial release. 12/2014 MPC5634M_AD, Rev. 1.0 2 Freescale Semiconductor How to Reach Us: Information in this document is provided solely to enable system and software Home Page: implementers to use Freescale products. There are no express or implied copyright freescale.com licenses granted hereunder to design or fabricate any integrated circuits based on the Web Support: information in this document. freescale.com/support Freescale reserves the right to make changes without further notice to any products herein.
    [Show full text]
  • Automated Synthesis of Symbolic Instruction Encodings from I/O Samples
    Automated Synthesis of Symbolic Instruction Encodings from I/O Samples Patrice Godefroid Ankur Taly Microsoft Research Stanford University PLDI’2012 Page 1 June 2012 Need for Symbolic Instruction Encodings Symbolic Execution is a key l 1 : m o v eax, i n p 1 component of precise binary m o v c l , i n p 2 program analysis tools s h l eax, c l j n z l2 j m p l3 - SAGE, BitBlaze, BAP, etc. l 2 : d i v ebx, eax // Is this safe ? - Static analysis tools / / I s e a x ! = 0 ? l 3 : … PLDI’2012 Page 2 June 2012 Problem: Symbolic Instruction Encoding Bit Vector[X] Instruction Bit Vector[Y] Inp 1 ? Op1 Inpn Opm Problem: Given a processor and an instruction name, symbolically describe the input-output function for the instruction • Express the encoding as bit-vector constraints (ex: SMT-Lib format) PLDI’2012 Page 3 June 2012 So far, only manual solutions… • From the instruction architecture manual (X86, ARM, …) implemented by the processor Limitations: • Tedious, expensive - X86 has more than 300 unique instructions, each with ~10 OPCodes, 2000 pages • Error-prone - Written in English, many corner cases • Imprecise - Spec is often under-specified • Partial - Not all instructions are covered X86 spec for SHLD • Can we trust the spec ? PLDI’2012 Page 4 June 2012 Here: Automated Synthesis Approach Searches for a function f that respects truth table Partial Truth- table S Sample inputs Synthesis Function (C with in-lined engine f assembly) Goals: • As automated as possible so that we can boot-strap a symbolic execution engine on an arbitrary instruction
    [Show full text]
  • Toshiba 32-Bit Arm Core-Based Microcontroller Product Guide
    SUBSIDIARIES AND AFFILIATES (As of July 1, 2017) Toshiba America Toshiba Electronics Europe GmbH Toshiba Electronics Asia, Ltd. Nov. 2017 Semiconductor Catalog Nov. 2017 Electronic Components, Inc. • Düsseldorf Head Office Tel: 2375-6111 Fax: 2375-0969 • Irvine, Headquarters Tel: (0211)5296-0 Fax: (0211)5296-400 Toshiba Electronics (China) Co., Ltd. BCE0085H Tel: (949)462-7700 Fax: (949)462-2200 • France Branch • Shanghai Head Office • Buffalo Grove (Chicago) Tel: (1)47282181 Tel: (021)6139-3888 Fax: (021)6190-8288 Tel: (847)484-2400 Fax: (847)541-7287 • Italy Branch • Beijing Branch • Duluth/Atlanta Tel: (039)68701 Fax:(039)6870205 Tel: (010)6590-8796 Fax: (010)6590-8791 Tel: (404)639-9520 Fax: (404)634-4434 • Munich Office • Chengdu Branch • El Paso Tel: (089)20302030 Fax: (089)203020310 Tel: (028)8675-1773 Fax: (028)8675-1065 Tel: (915)533-4242 • Spain Branch • Hangzhou Office • Marlborough Tel: (91)660-6794 Tel: (0571)8717-5004 Fax: (0571)8717-5013 Tel: (508)481-0034 Fax: (508)481-8828 • Sweden Branch • Nanjing Office • Parsippany Tel: (08)704-0900 Fax: (08)80-8459 Tel: (025)8689-0070 Fax: (025)5266-5106 Tel: (973)541-4715 Fax: (973)541-4716 • U.K. Branch • Qingdao Branch 32-Bit Microcontrollers 32-Bit Microcontrollers • San Jose Tel: (1932)841600 Tel: (532)8579-3328 Fax: (532)8579-3329 Tel: (408)526-2400 Fax: (408)526-2410 Toshiba Electronics Asia (Singapore) Pte. Ltd. • Shenzhen Branch • Wixom (Detroit) Tel: (65)6278-5252 Fax: (65)6271-5155 Tel: (0755)3686-0880 Fax: (0755)3686-0816 Tel: (248)347-2607 Fax: (248)347-2602 Toshiba Electronics Service (Thailand) Co., Ltd.
    [Show full text]
  • Problem Solving and Troubleshooting in AIX 5L
    Front cover Problem Solving and Troubleshooting in AIX 5L Introduction of new problem solving tools and changes in AIX 5L Step by step troubleshooting in real environments Complete guide to the problem determination process HyunGoo Kim JaeYong An John Harrison Tony Abruzzesse KyeongWon Jeong ibm.com/redbooks International Technical Support Organization Problem Solving and Troubleshooting in AIX 5L January 2002 SG24-5496-01 Take Note! Before using this information and the product it supports, be sure to read the general information in “Special notices” on page 439. Second Edition (January 2002) This edition applies to IBM ^ pSeries and RS/6000 Systems for use with the AIX 5L Operating System Version 5.1 and is based on information available in August, 2001. Comments may be addressed to: IBM Corporation, International Technical Support Organization Dept. JN9B Building 003 Internal Zip 2834 11400 Burnet Road Austin, Texas 78758-3493 When you send information to IBM, you grant IBM a non-exclusive right to use or distribute the information in any way it believes appropriate without incurring any obligation to you. © Copyright International Business Machines Corporation 1999-2002. All rights reserved. Note to U.S Government Users – Documentation related to restricted rights – Use, duplication or disclosure is subject to restrictions set forth in GSA ADP Schedule Contract with IBM Corp. Contents Figures . xiii Tables . xv Preface . xvii The team that wrote this redbook. xvii Special notice . xix IBM trademarks . xix Comments welcome. xix Chapter 1. Problem determination introduction. 1 1.1 Problem determination process . 3 1.1.1 Defining the problem . 3 1.1.2 Gathering information from the user .
    [Show full text]
  • 8-Bit Microcontroller with 16K Bytes In-System
    Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-Chip 2-cycle Multiplier • High Endurance Non-volatile Memory segments – 16K Bytes of In-System Self-programmable Flash program memory – 512 Bytes EEPROM – 1K Bytes Internal SRAM 8-bit – Write/Erase cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C(1) – Optional Boot Code Section with Independent Lock Bits Microcontroller In-System Programming by On-chip Boot Program True Read-While-Write Operation with 16K Bytes – Programming Lock for Software Security • JTAG (IEEE std. 1149.1 compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard In-System – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Programmable • Peripheral Features – 4 x 25 Segment LCD Driver Flash – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator –Four PWM Channels ATmega169P – 8-channel, 10-bit ADC – Programmable Serial USART ATmega169PV – Master/Slave SPI Serial Interface – Universal Serial Interface with Start Condition Detector – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up
    [Show full text]
  • John Vincent Atanasoff
    John Vincent Atanasoff: Inventor of the Digital Computer October 3, 2006 History of Computer Science (2R930) Department of Mathematics & Computer Science Technische Universiteit Eindhoven Bas Kloet 0461462 [email protected] Paul van Tilburg 0459098 [email protected] Abstract This essay is about John Vincent Atanasoff’s greatest invention, the Atana- soff Berry Computer or ABC. We look into the design and construction of this computer, and also determine the effect the ABC has had on the world. While discussing this machine we cannot avoid the dispute and trial surrounding the ENIAC patents. We will try to put the ENIAC in the right context with respect to the ABC. Copyright c 2006 Bas Kloet and Paul van Tilburg The contents of this and the following documents and the LATEX source code that is used to generate them is licensed under the Creative Commons Attribution-ShareAlike 2.5 license. Photos and images are excluded from this copyright. They were taken from [Mac88], [BB88] and [Mol88] and thus fall under their copyright accordingly. You are free: • to copy, distribute, display, and perform the work • to make derivative works • to make commercial use of the work Under the following conditions: Attribution: You must attribute the work in the manner specified by the author or licensor. Share Alike: If you alter, transform, or build upon this work, you may distribute the resulting work only under a license identical to this one. • For any reuse or distribution, you must make clear to others the license terms of this work. • Any of these conditions can be waived if you get permission from the copyright holder.
    [Show full text]
  • Pioneercomputertimeline2.Pdf
    Memory Size versus Computation Speed for various calculators and computers , IBM,ZQ90 . 11J A~len · W •• EDVAC lAS• ,---.. SEAC • Whirlwind ~ , • ENIAC SWAC /# / Harvard.' ~\ EDSAC Pilot• •• • ; Mc;rk I " • ACE I • •, ABC Manchester MKI • • ! • Z3 (fl. pt.) 1.000 , , .ENIAC •, Ier.n I i • • \ I •, BTL I (complexV • 100 ~ . # '-------" Comptometer • Ir.ne l ' with constants 10 0.1 1.0 10 100 lK 10K lOOK 1M GENERATIONS: II] = electronic-vacuum tube [!!!] = manual [1] = transistor Ime I = mechanical [1] = integrated circuit Iem I = electromechanical [I] = large scale integrated circuit CONTENTS THE COMPUTER MUSEUM BOARD OF DIRECTORS The Computer Museum is a non-profit. Kenneth H. Olsen. Chairman public. charitable foundation dedicated to Digital Equipment Corporation preserving and exhibiting an industry-wide. broad-based collection of the history of in­ Charles W Bachman formation processing. Computer history is Cullinane Database Systems A Compcmion to the Pioneer interpreted through exhibits. publications. Computer Timeline videotapes. lectures. educational programs. C. Gordon Bell and other programs. The Museum archives Digital Equipment Corporation I Introduction both artifacts and documentation and Gwen Bell makes the materials available for The Computer Museum 2 Bell Telephone Laboratories scholarly use. Harvey D. Cragon Modell Complex Calculator The Computer Museum is open to the public Texas Instruments Sunday through Friday from 1:00 to 6:00 pm. 3 Zuse Zl, Z3 There is no charge for admission. The Robert Everett 4 ABC. Atanasoff Berry Computer Museum's lecture hall and rece ption The Mitre Corporation facilities are available for rent on a mM ASCC (Harvard Mark I) prearranged basis. For information call C.
    [Show full text]
  • Automatic Generation of Invariants in Processor Verification
    Automatic Generation of Invariants in Processor Veri®cation Jeffrey X. Su, David L. Dill, and Clark W. Barrett Computer Science Department Stanford University Abstract. A central task in formal veri®cation is the de®nition of invariants, which characterize the reachable states of the system. When a system is ®nite- state, invariants can be discovered automatically. Our experience in verifying microprocessors using symbolic logic is that ®nding adequate invariants is extremely time-consuming. We present three techniquesfor automating the discovery of some of these invariants. All of them are essentially syntactic transformations on a logical formula derived from the state transition function. The goal is to eliminate quanti®ers and extract small clauses implied by the larger formula. We have implemented the method and exercised it on a description of the FLASH ProtocolProcessor(PP), a microprocessordesignedat Stanford for handling com- munications in a multiprocessor. We had previously veri®ed the PP by manually deriving invariants. Although the method is simple, it discovered 6 out of 7 of the invariants needed for veri®cation of the CPU of the processor design, and 28 out of 72 invariants neededfor veri®cation of the memory system of the processor. We believe that, in the future, the discovery of invariants can be largely automated by a combination of different methods, including this one. 1 Introduction As microprocessors become more complex, an increasingly large fraction of the design time is spent on validation. Validation techniques which rely entirely on simulation are limited because of the many possible cases which must be accounted for. Sometimes, signi®cant bugs are found after a processor is commercially released, which is both embarrassing and costly.
    [Show full text]
  • Vax 6131Bls Uk - Service Parts List
    VAX 6131BLS UK - SERVICE PARTS LIST Item Vax Part No. Description Price Code Service Item Item Vax Part No. Description Price Code Service Item 2 1-2-31-01-006 FILTER-FOAM-EXHAUST S1 CS 34 1-2-30-01-015 SEAL-FILTER/RESERVOIR K1 S 5 1-2-11-04-007 CABLE CLAMP L1 CS 35 1-3-15-03-007 FILTER HOUSING ASSY-UNIV-BLACK T3 S 29 1-2-31-01-002 FILTER DISC-BONDINI A1 CS 36 1-3-124592-00 HSG-MOULDED FILTER-PURPLE S2 S 37 1-7-124833-00 FILTER-CAN-FOAM SLEEVE-CARTRIDGE L2 CS 39 1-2-14-02-001 BALL VALVE N1 S 40 1-2-124732-01 RESERVOIR ASSY-PMP-PURPLE W3 CS 41 1-2-30-02-002 SEAL-CONICAL DUCT D2 S 44 1-3-13-02-001 UPHOLSTERY TOOL Y1 CS 42 1-2-30-02-003 SEAL-EXHAUST D2 S 47 1-2-39-01-010 CREVICE TOOL Y1 CS 43 1-2-124731-09 REC BUCKET/SPIDER ASSY-6131BLS Z3 S 48 1-3-13-01-001 DUSTBRUSH H2 CS 45 1-2-32-01-002 CASTOR-TWO WHEEL X1 S 50 1-2-13-02-002 TUBE-EXTN-STAINLESS B3 CS 60 1-9-124423-00 TUBE-PUMP TO QRV A1 S 52 1-3-18-01-022 HOSE & GRIP ASSY W3 CS 62 1-1-06-01-073 FEMALE QRV ASSY S2 S 53 1-9-124962-00 WASH HEAD K3 CS 63 1-3-124422-00 ELBOW-QRV-ET408 C2 S 54 1-9-124961-00 FLOOR BRUSH F3 CS 65 1-2-13-04-008 INLET TUBE-PVC A1 S 64 1-2-11-03-007 RETAINER CLIP-SPRING H1 CS 66 1-3-124424-00 FIXING STRAP-ET408 L1 S 74 1-2-124594-00 UPHOLSTERY WASH TOOL K3 CS 67 1-7-124677-00 FILTER-WATER-INLET E2 S 101 1-2-124805-00 WATER TUBE ASSY-STRAIGHT-LATE Z2 CS 68 1-5-124419-00 PUMP-ET408 S3 S 3 1-3-124588-00 COVER-ACCESS-PURPLE X1 NS 69 1-6-124425-00 SEAL-PUMP ET408 L1 S 6 1-2-36-04-004 CORD PROTECTOR A1 NS 93 1-3-123613-00 DEFLECTOR A2 S 8 1-3-124578-01 COVER-HANDLE-PMP-NVAR-PURPLE
    [Show full text]
  • The Z1: Architecture and Algorithms of Konrad Zuse's First Computer
    The Z1: Architecture and Algorithms of Konrad Zuse’s First Computer Raul Rojas Freie Universität Berlin June 2014 Abstract This paper provides the first comprehensive description of the Z1, the mechanical computer built by the German inventor Konrad Zuse in Berlin from 1936 to 1938. The paper describes the main structural elements of the machine, the high-level architecture, and the dataflow between components. The computer could perform the four basic arithmetic operations using floating-point numbers. Instructions were read from punched tape. A program consisted of a sequence of arithmetical operations, intermixed with memory store and load instructions, interrupted possibly by input and output operations. Numbers were stored in a mechanical memory. The machine did not include conditional branching in the instruction set. While the architecture of the Z1 is similar to the relay computer Zuse finished in 1941 (the Z3) there are some significant differences. The Z1 implements operations as sequences of microinstructions, as in the Z3, but does not use rotary switches as micro- steppers. The Z1 uses a digital incrementer and a set of conditions which are translated into microinstructions for the exponent and mantissa units, as well as for the memory blocks. Microinstructions select one out of 12 layers in a machine with a 3D mechanical structure of binary mechanical elements. The exception circuits for mantissa zero, necessary for normalized floating-point, were lacking; they were first implemented in the Z3. The information for this article was extracted from careful study of the blueprints drawn by Zuse for the reconstruction of the Z1 for the German Technology Museum in Berlin, from some letters, and from sketches in notebooks.
    [Show full text]