The Z1: Architecture and Algorithms of Konrad Zuse's First Computer
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Wearable-Based Pedestrian Inertial Navigation with Constraints Based on Biomechanical Models
Wearable-based pedestrian inertial navigation with constraints based on biomechanical models Dina Bousdar Ahmed∗ and Kai Metzger† ∗ Institute of Communications and Navigation German Aerospace Center (DLR), Munich, Germany Email: [email protected] † Technical University of Munich, Germany Email: kai [email protected] Abstract—Our aim in this paper is to analyze inertial nav- sensor to correct the heading estimation [4]. The combina- igation systems (INSs) from the biomechanical point of view. tion of inertial sensors and WiFi measurements is useful in We wanted to improve the performance of a thigh INS by indoor environments. Chen et al. use the position estimated applying biomechanical constraints. To that end, we propose a biomechanical model of the leg. The latter establishes a through WiFi measurements to correct the position estimates relationship between the orientation of the thigh INS and the of an inertial navigation system [5]. The latter is based on a kinematic motion of the leg. This relationship allows to observe smartphone. the effect that the orientation errors have in the expected motion The detection of known landmarks, e.g. turns, elevators, etc, of the leg. We observe that the errors in the orientation estimation can improve the position estimation. Chen et al. [5] incorporate of an INS translate into incoherent human motion. Based on this analysis, we proposed a modified thigh INS to integrate landmarks to improve the performance of their navigation biomechanical constraints. The results show that the proposed system. Munoz et al. [6] use also landmarks to correct directly system outperforms the thigh INS in 50% regarding distance the heading estimation of a thigh-mounted inertial navigation error and 32% regarding orientation error. -
On the Hardware Reduction of Z-Datapath of Vectoring CORDIC
On the Hardware Reduction of z-Datapath of Vectoring CORDIC R. Stapenhurst*, K. Maharatna**, J. Mathew*, J.L.Nunez-Yanez* and D. K. Pradhan* *University of Bristol, Bristol, UK **University of Southampton, Southampton, UK [email protected] Abstract— In this article we present a novel design of a hardware wordlength larger than 18-bits the hardware requirement of it optimal vectoring CORDIC processor. We present a mathematical becomes more than the classical CORDIC. theory to show that using bipolar binary notation it is possible to eliminate all the arithmetic computations required along the z- In this particular work we propose a formulation to eliminate datapath. Using this technique it is possible to achieve three and 1.5 all the arithmetic operations along the z-datapath for conventional times reduction in the number of registers and adder respectively two-sided vector rotation and thereby reducing the hardware compared to classical CORDIC. Following this, a 16-bit vectoring while increasing the accuracy. Also the resulting architecture CORDIC is designed for the application in Synchronizer for IEEE shows significant hardware saving as the wordlength increases. 802.11a standard. The total area and dynamic power consumption Although we stick to the 2’s complement number system, without of the processor is 0.14 mm2 and 700μW respectively when loss of generality, this formulation can be adopted easily for synthesized in 0.18μm CMOS library which shows its effectiveness redundant arithmetic and higher radix formulation. A 16-bit as a low-area low-power processor. processor developed following this formulation requires 0.14 mm2 area and consumes 700 μW dynamic power when synthesized in 0.18μm CMOS library. -
Simulating Physics with Computers
International Journal of Theoretical Physics, VoL 21, Nos. 6/7, 1982 Simulating Physics with Computers Richard P. Feynman Department of Physics, California Institute of Technology, Pasadena, California 91107 Received May 7, 1981 1. INTRODUCTION On the program it says this is a keynote speech--and I don't know what a keynote speech is. I do not intend in any way to suggest what should be in this meeting as a keynote of the subjects or anything like that. I have my own things to say and to talk about and there's no implication that anybody needs to talk about the same thing or anything like it. So what I want to talk about is what Mike Dertouzos suggested that nobody would talk about. I want to talk about the problem of simulating physics with computers and I mean that in a specific way which I am going to explain. The reason for doing this is something that I learned about from Ed Fredkin, and my entire interest in the subject has been inspired by him. It has to do with learning something about the possibilities of computers, and also something about possibilities in physics. If we suppose that we know all the physical laws perfectly, of course we don't have to pay any attention to computers. It's interesting anyway to entertain oneself with the idea that we've got something to learn about physical laws; and if I take a relaxed view here (after all I'm here and not at home) I'll admit that we don't understand everything. -
The Advent of Recursion & Logic in Computer Science
The Advent of Recursion & Logic in Computer Science MSc Thesis (Afstudeerscriptie) written by Karel Van Oudheusden –alias Edgar G. Daylight (born October 21st, 1977 in Antwerpen, Belgium) under the supervision of Dr Gerard Alberts, and submitted to the Board of Examiners in partial fulfillment of the requirements for the degree of MSc in Logic at the Universiteit van Amsterdam. Date of the public defense: Members of the Thesis Committee: November 17, 2009 Dr Gerard Alberts Prof Dr Krzysztof Apt Prof Dr Dick de Jongh Prof Dr Benedikt Löwe Dr Elizabeth de Mol Dr Leen Torenvliet 1 “We are reaching the stage of development where each new gener- ation of participants is unaware both of their overall technological ancestry and the history of the development of their speciality, and have no past to build upon.” J.A.N. Lee in 1996 [73, p.54] “To many of our colleagues, history is only the study of an irrele- vant past, with no redeeming modern value –a subject without useful scholarship.” J.A.N. Lee [73, p.55] “[E]ven when we can't know the answers, it is important to see the questions. They too form part of our understanding. If you cannot answer them now, you can alert future historians to them.” M.S. Mahoney [76, p.832] “Only do what only you can do.” E.W. Dijkstra [103, p.9] 2 Abstract The history of computer science can be viewed from a number of disciplinary perspectives, ranging from electrical engineering to linguistics. As stressed by the historian Michael Mahoney, different `communities of computing' had their own views towards what could be accomplished with a programmable comput- ing machine. -
Turing's Influence on Programming — Book Extract from “The Dawn of Software Engineering: from Turing to Dijkstra”
Turing's Influence on Programming | Book extract from \The Dawn of Software Engineering: from Turing to Dijkstra" Edgar G. Daylight∗ Eindhoven University of Technology, The Netherlands [email protected] Abstract Turing's involvement with computer building was popularized in the 1970s and later. Most notable are the books by Brian Randell (1973), Andrew Hodges (1983), and Martin Davis (2000). A central question is whether John von Neumann was influenced by Turing's 1936 paper when he helped build the EDVAC machine, even though he never cited Turing's work. This question remains unsettled up till this day. As remarked by Charles Petzold, one standard history barely mentions Turing, while the other, written by a logician, makes Turing a key player. Contrast these observations then with the fact that Turing's 1936 paper was cited and heavily discussed in 1959 among computer programmers. In 1966, the first Turing award was given to a programmer, not a computer builder, as were several subsequent Turing awards. An historical investigation of Turing's influence on computing, presented here, shows that Turing's 1936 notion of universality became increasingly relevant among programmers during the 1950s. The central thesis of this paper states that Turing's in- fluence was felt more in programming after his death than in computer building during the 1940s. 1 Introduction Many people today are led to believe that Turing is the father of the computer, the father of our digital society, as also the following praise for Martin Davis's bestseller The Universal Computer: The Road from Leibniz to Turing1 suggests: At last, a book about the origin of the computer that goes to the heart of the story: the human struggle for logic and truth. -
18-447 Computer Architecture Lecture 6: Multi-Cycle and Microprogrammed Microarchitectures
18-447 Computer Architecture Lecture 6: Multi-Cycle and Microprogrammed Microarchitectures Prof. Onur Mutlu Carnegie Mellon University Spring 2015, 1/28/2015 Agenda for Today & Next Few Lectures n Single-cycle Microarchitectures n Multi-cycle and Microprogrammed Microarchitectures n Pipelining n Issues in Pipelining: Control & Data Dependence Handling, State Maintenance and Recovery, … n Out-of-Order Execution n Issues in OoO Execution: Load-Store Handling, … 2 Reminder on Assignments n Lab 2 due next Friday (Feb 6) q Start early! n HW 1 due today n HW 2 out n Remember that all is for your benefit q Homeworks, especially so q All assignments can take time, but the goal is for you to learn very well 3 Lab 1 Grades 25 20 15 10 5 Number of Students 0 30 40 50 60 70 80 90 100 n Mean: 88.0 n Median: 96.0 n Standard Deviation: 16.9 4 Extra Credit for Lab Assignment 2 n Complete your normal (single-cycle) implementation first, and get it checked off in lab. n Then, implement the MIPS core using a microcoded approach similar to what we will discuss in class. n We are not specifying any particular details of the microcode format or the microarchitecture; you can be creative. n For the extra credit, the microcoded implementation should execute the same programs that your ordinary implementation does, and you should demo it by the normal lab deadline. n You will get maximum 4% of course grade n Document what you have done and demonstrate well 5 Readings for Today n P&P, Revised Appendix C q Microarchitecture of the LC-3b q Appendix A (LC-3b ISA) will be useful in following this n P&H, Appendix D q Mapping Control to Hardware n Optional q Maurice Wilkes, “The Best Way to Design an Automatic Calculating Machine,” Manchester Univ. -
Preparation and Investigation of Highly Charged Ions in a Penning Trap for the Determination of Atomic Magnetic Moments
Preparation and Investigation of Highly Charged Ions in a Penning Trap for the Determination of Atomic Magnetic Moments Präparation und Untersuchung von hochgeladenen Ionen in einer Penning-Falle zur Bestimmung atomarer magnetischer Momente Dissertation approved by the Fachbereich Physik of the Technische Universität Darmstadt in fulfillment of the requirements for the degree of Doctor of Natural Sciences (Dr. rer. nat.) by Dipl.-Phys. Marco Wiesel from Neustadt an der Weinstraße June 2017 — Darmstadt — D 17 Preparation and Investigation of Highly Charged Ions in a Penning Trap for the Determination of Atomic Magnetic Moments Dissertation approved by the Fachbereich Physik of the Technische Universität Darmstadt in fulfillment of the requirements for the degree of Doctor of Natural Sciences (Dr. rer. nat.) by Dipl.-Phys. Marco Wiesel from Neustadt an der Weinstraße 1. Referee: Prof. Dr. rer. nat. Gerhard Birkl 2. Referee: Privatdozent Dr. rer. nat. Wolfgang Quint Submission date: 18.04.2017 Examination date: 24.05.2017 Darmstadt 2017 D 17 Title: The logo of ARTEMIS – AsymmetRic Trap for the measurement of Electron Magnetic moments in IonS. Bitte zitieren Sie dieses Dokument als: URN: urn:nbn:de:tuda-tuprints-62803 URL: http://tuprints.ulb.tu-darmstadt.de/id/eprint/6280 Dieses Dokument wird bereitgestellt von tuprints, E-Publishing-Service der TU Darmstadt http://tuprints.ulb.tu-darmstadt.de [email protected] Die Veröffentlichung steht unter folgender Creative Commons Lizenz: Namensnennung – Keine kommerzielle Nutzung – Keine Bearbeitung 4.0 International https://creativecommons.org/licenses/by-nc-nd/4.0/ Abstract The ARTEMIS experiment aims at measuring magnetic moments of electrons bound in highly charged ions that are stored in a Penning trap. -
System Design for a Computational-RAM Logic-In-Memory Parailel-Processing Machine
System Design for a Computational-RAM Logic-In-Memory ParaIlel-Processing Machine Peter M. Nyasulu, B .Sc., M.Eng. A thesis submitted to the Faculty of Graduate Studies and Research in partial fulfillment of the requirements for the degree of Doctor of Philosophy Ottaw a-Carleton Ins titute for Eleceical and Computer Engineering, Department of Electronics, Faculty of Engineering, Carleton University, Ottawa, Ontario, Canada May, 1999 O Peter M. Nyasulu, 1999 National Library Biôiiothkque nationale du Canada Acquisitions and Acquisitions et Bibliographie Services services bibliographiques 39S Weiiington Street 395. nie WeUingtm OnawaON KlAW Ottawa ON K1A ON4 Canada Canada The author has granted a non- L'auteur a accordé une licence non exclusive licence allowing the exclusive permettant à la National Library of Canada to Bibliothèque nationale du Canada de reproduce, ban, distribute or seU reproduire, prêter, distribuer ou copies of this thesis in microform, vendre des copies de cette thèse sous paper or electronic formats. la forme de microficbe/nlm, de reproduction sur papier ou sur format électronique. The author retains ownership of the L'auteur conserve la propriété du copyright in this thesis. Neither the droit d'auteur qui protège cette thèse. thesis nor substantial extracts fkom it Ni la thèse ni des extraits substantiels may be printed or otherwise de celle-ci ne doivent être imprimés reproduced without the author's ou autrement reproduits sans son permission. autorisation. Abstract Integrating several 1-bit processing elements at the sense amplifiers of a standard RAM improves the performance of massively-paralle1 applications because of the inherent parallelism and high data bandwidth inside the memory chip. -
A Biased History Of! Programming Languages Programming Languages:! a Short History Fortran Cobol Algol Lisp
A Biased History of! Programming Languages Programming Languages:! A Short History Fortran Cobol Algol Lisp Basic PL/I Pascal Scheme MacLisp InterLisp Franz C … Ada Common Lisp Roman Hand-Abacus. Image is from Museo (Nazionale Ramano at Piazzi delle Terme, Rome) History • Pre-History : The first programmers • Pre-History : The first programming languages • The 1940s: Von Neumann and Zuse • The 1950s: The First Programming Language • The 1960s: An Explosion in Programming languages • The 1970s: Simplicity, Abstraction, Study • The 1980s: Consolidation and New Directions • The 1990s: Internet and the Web • The 2000s: Constraint-Based Programming Ramon Lull (1274) Raymondus Lullus Ars Magna et Ultima Gottfried Wilhelm Freiherr ! von Leibniz (1666) The only way to rectify our reasonings is to make them as tangible as those of the Mathematician, so that we can find our error at a glance, and when there are disputes among persons, we can simply say: Let us calculate, without further ado, in order to see who is right. Charles Babbage • English mathematician • Inventor of mechanical computers: – Difference Engine, construction started but not completed (until a 1991 reconstruction) – Analytical Engine, never built I wish to God these calculations had been executed by steam! Charles Babbage, 1821 Difference Engine No.1 Woodcut of a small portion of Mr. Babbages Difference Engine No.1, built 1823-33. Construction was abandoned 1842. Difference Engine. Built to specifications 1991. It has 4,000 parts and weighs over 3 tons. Fixed two bugs. Portion of Analytical Engine (Arithmetic and Printing Units). Under construction in 1871 when Babbage died; completed by his son in 1906. -
The History of Computers: Part II
The History Of Computers: Part II You will learn about the computers of the 20th century and the people behind those machines. Some of the clipart images come from the sites: •http://www.clipartheaven.com/ •http://www.horton-szar.net/ •http://www.shootpetoet.be •www.dpw.wau.nl/pv/temp/ clipart/screenbeans.htm James Tam Categories Of 20th Century Computers •The mechanical monsters of the twenty first century - The machines of Konrad Zuse - The Bell telephone models - Howard Aiken and the Harvard computers •The computers of the electronic revolution -The ABC -The ENIAC - The Colossus machines of Bletchley Park •The first modern (stored program/memory) computers - The Manchester machine -The EDSAC - The EDVAC James Tam Computer History: Part II 1 The Mechanical Monsters •Performed calculations using moving mechanical parts rather than using electronics Images from the History of Computing Technology by Michael R. Williams James Tam The Mechanical Monsters •Many were used to solve equations that were either impossible or very time consuming to solve analytically. •Often conducting experiments were also impractical. James Tam Computer History: Part II 2 The Mechanical Monsters •Konrad Zuse -Z1 –Z4 •George Stibitz - Bell relay based computers Model I - VI •Howard Aiken - Harvard Mark I - IV James Tam The First Set Of Mechanical Monsters Were Created By Konrad Zuse •Developed a series of mechanical calculating machines (Z1, Z2, Z3, Z4). •Motivated by the need to perform complex calculations because current approaches were unsatisfactory. James Tam Computer History: Part II 3 The Z1 •It was entirely mechanical From the History of Computing Technology by Michael R. -
Vax 6135 Car Vax Uk - Service Parts List
VAX 6135 CAR VAX UK - SERVICE PARTS LIST Item Vax Part No. Description Price Code Service Item Item Vax Part No. Description Price Code Service Item 2 1-2-31-01-006 FILTER-FOAM-EXHAUST S1 CS 34 1-2-30-01-015 SEAL-FILTER/RESERVOIR K1 S 5 1-2-11-04-007 CABLE CLAMP L1 CS 35 1-3-15-03-007 FILTER HSG ASSY-UNIV-BLACK T3 S 29 1-2-31-01-002 FILTER DISC-BONDINI A1 CS 39 1-2-14-02-001 BALL VALVE N1 S 32 1-2-31-01-007 FILTER -FIBRE-MOULDED X1 CS 40 1-3-09-06-007 RESERVOIR ASSY-UNIV-BLACK W3 S 44 1-3-13-02-001 UPHOLSTERY TOOL Y1 CS 41 1-2-30-02-002 SEAL-CONICAL DUCT D2 S 47 1-2-39-01-010 CREVICE TOOL Y1 CS 42 1-2-30-02-003 SEAL-EXHAUST D2 S 48 1-3-13-01-001 DUSTBRUSH H2 CS 43 1-2-124731-12 RECOVERY BUCKET/SPIDER ASSY Z3 S 50 1-2-13-02-002 TUBE-EXTN-STAINLESS B3 CS 45 1-2-32-01-002 CASTOR-TWO WHEEL X1 S 52 1-3-18-01-022 HOSE & GRIP ASSY W3 CS 60 1-9-124423-00 TUBE-PUMP TO QRV A1 S 53 1-9-124962-00 WASH HEAD J3 CS 62 1-1-06-01-073 FEMALE QRV ASSY S2 S 54 1-9-124961-00 FLOOR BRUSH F3 CS 63 1-3-124422-00 ELBOW-QRV-ET408 C2 S 64 1-2-11-03-007 RETAINER CLIP-SPRING H1 CS 65 1-2-13-04-008 INLET TUBE-PVC A1 S 74 1-2-124594-00 UPHOLSTERY WASH TOOL K3 CS 66 1-3-124424-00 FIXING STRAP-ET408 L1 S 75 1-9-125226-00 TURBO TOOL-100mm R3 CS 67 1-7-124677-00 FILTER-WATER-INLET E2 S 77 1-9-125549-00 CREVICE TOOL-EXTRA LONG G2 CS 68 1-5-124419-00 PUMP-ET408 S3 S 101 1-2-124805-00 WATER TUBE ASSY-STRAIGHT Z2 CS 69 1-6-124425-00 SEAL-PUMP ET408 L1 S 3 1-3-124588-03 COVER-ACCESS-B R GREEN X1 NS 99 1-2-07-03-001 DUCT-CONICAL X1 S 6 1-2-36-04-004 CORD PROTECTOR A1 NS 102 -
CS 6290 Chapter 1
Spring 2011 Prof. Hyesoon Kim Xbox 360 System Architecture, „Anderews, Baker • 3 CPU cores – 4-way SIMD vector units – 8-way 1MB L2 cache (3.2 GHz) – 2 way SMT • 48 unified shaders • 3D graphics units • 512-Mbyte DRAM main memory • FSB (Front-side bus): 5.4 Gbps/pin/s (16 pins) • 10.8 Gbyte/s read and write • Xbox 360: Big endian • Windows: Little endian http://msdn.microsoft.com/en-us/library/cc308005(VS.85).aspx • L2 cache : – Greedy allocation algorithm – Different workloads have different working set sizes • 2-way 32 Kbyte L1 I-cache • 4-way 32 Kbyte L1 data cache • Write through, no write allocation • Cache block size :128B (high spatial locality) • 2-way SMT, • 2 insts/cycle, • In-order issue • Separate vector/scalar issue queue (VIQ) Vector Vector Execution Unit Instructions Scalar Scalar Execution Unit • First game console by Microsoft, released in 2001, $299 Glorified PC – 733 Mhz x86 Intel CPU, 64MB DRAM, NVIDIA GPU (graphics) – Ran modified version of Windows OS – ~25 million sold • XBox 360 – Second generation, released in 2005, $299-$399 – All-new custom hardware – 3.2 Ghz PowerPC IBM processor (custom design for XBox 360) – ATI graphics chip (custom design for XBox 360) – 34+ million sold (as of 2009) • Design principles of XBox 360 [Andrews & Baker] - Value for 5-7 years -!ig performance increase over last generation - Support anti-aliased high-definition video (720*1280*4 @ 30+ fps) - extremely high pixel fill rate (goal: 100+ million pixels/s) - Flexible to suit dynamic range of games - balance hardware, homogenous resources - Programmability (easy to program) Slide is from http://www.cis.upenn.edu/~cis501/lectures/12_xbox.pdf • Code name of Xbox 360‟s core • Shared cell (playstation processor) ‟s design philosophy.