8-Bit Microcontroller with 1K Bytes In-System Programmable Flash
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Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Througput at 20 MHz • High Endurance Non-volatile Memory segments – 1K Bytes of In-System Self-programmable Flash program memory – 64 Bytes EEPROM 8-bit – 64 Bytes Internal SRAM – Write/Erase cyles: 10,000 Flash/100,000 EEPROM Microcontroller – Data retention: 20 years at 85°C/100 years at 25°C (see page 6) – Programming Lock for Self-Programming Flash & EEPROM Data Security with 1K Bytes • Peripheral Features In-System – One 8-bit Timer/Counter with Prescaler and Two PWM Channels – 4-channel, 10-bit ADC with Internal Voltage Reference Programmable – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator Flash • Special Microcontroller Features – debugWIRE On-chip Debug System – In-System Programmable via SPI Port – External and Internal Interrupt Sources ATtiny13 – Low Power Idle, ADC Noise Reduction, and Power-down Modes ATtiny13V – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator • I/O and Packages – 8-pin PDIP/SOIC: Six Programmable I/O Lines – 20-pad MLF: Six Programmable I/O Lines • Operating Voltage: – 1.8 - 5.5V for ATtiny13V – 2.7 - 5.5V for ATtiny13 • Speed Grade – ATtiny13V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V – ATtiny13: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V • Industrial Temperature Range • Low Power Consumption – Active Mode: • 1 MHz, 1.8V: 240 µA – Power-down Mode: • < 0.1 µA at 1.8V Rev. 2535J–AVR–08/10 1. Pin Configurations Figure 1-1. Pinout ATtiny13/ATtiny13V 8-PDIP/SOIC (PCINT5/RESET/ADC0/dW) PB5 1 8 VCC (PCINT3/CLKI/ADC3) PB3 2 7 PB2 (SCK/ADC1/T0/PCINT2) (PCINT4/ADC2) PB4 3 6 PB1 (MISO/AIN1/OC0B/INT0/PCINT1) GND 4 5 PB0 (MOSI/AIN0/OC0A/PCINT0) 20-QFN/MLF DNC DNC DNC DNC DNC (PCINT5/RESET/ADC0/dW) PB5 1 20 19 18 17 16 15 VCC (PCINT3/CLKI/ADC3) PB3 2 14 PB2 (SCK/ADC1/T0/PCINT2) DNC 3 13 DNC DNC 4 12 PB1 (MISO/AIN1/OC0B/INT0/PCINT1) (PCINT4/ADC2) PB4 5 11 PB0 (MOSI/AIN0/OC0A/PCINT0) 6 7 8 9 10 DNC DNC DNC DNC GND NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect 10-QFN/MLF (PCINT5/RESET/ADC0/dW) PB5 1 10 VCC (PCINT3/CLKI/ADC3) PB3 2 9 PB2 (SCK/ADC1/T0/PCINT2) DNC 3 8 DNC (PCINT4/ADC2) PB4 4 7 PB1 (MISO/AIN1/OC0B/INT0/PCINT1) GND 5 6 PB0 (MOSI/AIN0/OC0A/PCINT0) NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect 2 ATtiny13 2535J–AVR–08/10 ATtiny13 1.1 Pin Descriptions 1.1.1 VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB5:PB0) Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny13 as listed on page 54. 1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 18-1 on page 115. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin. 3 2535J–AVR–08/10 2. Overview The ATtiny13 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram 8-BIT DATABUS STACK CALIBRATED POINTER WATCHDOG INTERNAL OSCILLATOR OSCILLATOR SRAM WATCHDOG TIMING AND VCC TIMER CONTROL PROGRAM MCU CONTROL COUNTER REGISTER GND MCU STATUS REGISTER PROGRAM FLASH TIMER/ COUNTER0 INSTRUCTION GENERAL REGISTER PURPOSE INTERRUPT UNIT REGISTERS X PROGRAMMING INSTRUCTION Y LOGIC DECODER Z CONTROL DATA LINES ALU EEPROM STATUS REGISTER ADC / DATA REGISTER DATA DIR. ANALOG COMPARATOR PORT B REG.PORT B PORT B DRIVERS RESET CLKI PB0-PB5 4 ATtiny13 2535J–AVR–08/10 ATtiny13 The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. The ATtiny13 provides the following features: 1K byte of In-System Programmable Flash, 64 bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working reg- isters, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4- channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three soft- ware selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Inter- rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny13 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits. 5 2535J–AVR–08/10 3. General Information 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen- tation for more details. 3.3 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 6 ATtiny13 2535J–AVR–08/10 ATtiny13 4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.1 Architectural Overview Figure 4-1. Block Diagram of the AVR Architecture Data Bus 8-bit Program Status Flash Counter and Control Program Memory 32 x 8 Instruction General Register Purpose Interrupt Registrers Unit Instruction Watchdog Decoder Timer ALU Analog Control Lines Comparator Direct Addressing Indirect Addressing I/O Module1 Data I/O Module 2 SRAM I/O Module n EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruc- tion is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory. 7 2535J–AVR–08/10 The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ- ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic opera- tion, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word for- mat. Every Program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.