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8-Bit Microcontroller with 16K Bytes In-System

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8-Bit Microcontroller with 16K Bytes In-System Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-Chip 2-cycle Multiplier • High Endurance Non-volatile Memory segments – 16K Bytes of In-System Self-programmable Flash program memory – 512 Bytes EEPROM – 1K Bytes Internal SRAM 8-bit – Write/Erase cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C(1) – Optional Boot Code Section with Independent Lock Bits Microcontroller In-System Programming by On-chip Boot Program True Read-While-Write Operation with 16K Bytes – Programming Lock for Software Security • JTAG (IEEE std. 1149.1 compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard In-System – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Programmable • Peripheral Features – 4 x 25 Segment LCD Driver Flash – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator –Four PWM Channels ATmega169P – 8-channel, 10-bit ADC – Programmable Serial USART ATmega169PV – Master/Slave SPI Serial Interface – Universal Serial Interface with Start Condition Detector – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change Preliminary • Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby • I/O and Packages – 54 Programmable I/O Lines – 64-lead TQFP, 64-pad QFN/MLF and 64-pad DRQFN • Speed Grade: – ATmega169PV: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V – ATmega169P: 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V • Temperature range: –-40°C to 85°C Industrial • Ultra-Low Power Consumption – Active Mode: 1 MHz, 1.8V: 330 µA 32 kHz, 1.8V: 10 µA (including Oscillator) 32 kHz, 1.8V: 25 µA (including Oscillator and LCD) – Power-down Mode: 0.1 µA at 1.8V – Power-save Mode: 0.6 µA at 1.8V(Including 32 kHz RTC) Rev. 8018N–AVR–08/09 ATmega169P 1. Pin Configurations 1.1 Pinout - TQFP/QFN/MLF Figure 1-1. 64A (TQFP)and 64M1 (QFN/MLF) Pinout ATmega169P AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (COM0) PA1 (COM1) PA2 (COM2) 61 60 59 58 57 56 55 54 53 52 51 50 49 64 63 62 LCDCAP 1 48 PA3 (COM3) (RXD/PCINT0) PE0 2 47 PA4 (SEG0) INDEX CORNER (TXD/PCINT1) PE1 3 46 PA5 (SEG1) (XCK/AIN0/PCINT2) PE2 4 45 PA6 (SEG2) (AIN1/PCINT3) PE3 5 44 PA7 (SEG3) (USCK/SCL/PCINT4) PE4 6 43 PG2 (SEG4) (DI/SDA/PCINT5) PE5 7 42 PC7 (SEG5) (DO/PCINT6) PE6 8 41 PC6 (SEG6) (CLKO/PCINT7) PE7 9 40 PC5 (SEG7) (SS/PCINT8) PB0 10 39 PC4 (SEG8) (SCK/PCINT9) PB1 11 38 PC3 (SEG9) (MOSI/PCINT10) PB2 12 37 PC2 (SEG10) (MISO/PCINT11) PB3 13 36 PC1 (SEG11) (OC0A/PCINT12) PB4 14 35 PC0 (SEG12) (OC1A/PCINT13) PB5 15 34 PG1 (SEG13) (OC1B/PCINT14) PB6 16 33 PG0 (SEG14) 22 23 24 25 26 27 28 29 18 19 20 21 17 30 31 32 VCC GND RESET/PG5 (SEG17) PD5 (SEG16) PD6 (SEG15) PD7 (SEG20) PD2 (SEG19) PD3 (SEG18) PD4 (TOSC2) XTAL2 (TOSC1) XTAL1 (T1/SEG24) PG3 (T0/SEG23) PG4 (INT0/SEG21) PD1 (ICP1/SEG22) PD0 (OC2A/PCINT15) PB7 Note: The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be sol- dered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. 2 8018N–AVR–08/09 ATmega169P 1.2 Pinout - DRQFN Figure 1-2. 64MC (DRQFN) Pinout ATmega169P Top view Bottom view A26 B23 A27 B24 A28 B25 A29 B26 A30 B27 A31 B28 A32 B29 A33 B30 A34 A34 B30 A33 B29 A32 B28 A31 B27 A30 B26 A29 B25 A28 B24 A27 B23 A26 A1 A25 A25 A1 B1 B22 B22 B1 A2 A24 A24 A2 B2 B21 B21 B2 A3 A23 A23 A3 B3 B20 B20 B3 A4 A22 A22 A4 B4 B19 B19 B4 A5 A21 A21 A5 B5 B18 B18 B5 A6 A20 A20 A6 B6 B17 B17 B6 A7 A19 A19 A7 B7 B16 B16 B7 A8 A18 A18 A8 A17 B15 A16 B14 A15 B13 A14 B12 A13 B11 A12 B10 A11 B9 A10 B8 A9 A9 B8 A10 B9 A11 B10 A12 B11 A13 B12 A14 B13 A15 B14 A16 B15 A17 Table 1-1. DRQFN-64 Pinout ATmega169P. A1 PE0 A9 PB7 A18 PG1 (SEG13) A26 PA2 (COM2) B1 VLCDCAP B8 PB6 B16 PG0 (SEG14) B23 PA3 (COM3) A2 PE1 A10 PG3 A19 PC0 (SEG12) A27 PA1 (COM1) B2 PE2 B9 PG4 B17 PC1 (SEG11) B24 PA0 (COM0) A3 PE3 A11 RESET A20 PC2 (SEG10) A28 VCC B3 PE4 B10 VCC B18 PC3 (SEG9) B25 GND A4 PE5 A12 GND A21 PC4 (SEG8) A29 PF7 B4 PE6 B11 XTAL2 (TOSC2) B19 PC5 (SEG7) B26 PF6 A5 PE7 A13 XTAL1 (TOSC1) A22 PC6 (SEG6) A30 PF5 B5 PB0 B12 PD0 (SEG22) B20 PC7 (SEG5) B27 PF4 A6 PB1 A14 PD1 (SEG21) A23 PG2 (SEG4) A31 PF3 B6 PB2 B13 PD2 (SEG20) B21 PA7 (SEG3) B28 PF2 A7 PB3 A15 PD3 (SEG19) A24 PA6 (SEG2) A32 PF1 B7 PB5 B14 PD4 (SEG18) B22 PA4 (SEG0) B29 PF0 A8 PB4 A16 PD5 (SEG17) A25 PA5 (SEG1) A33 AREF B15 PD7 (SEG15) B30 AVCC A17 PD6 (SEG16) A34 GND 3 8018N–AVR–08/09 ATmega169P 2. Overview The ATmega169P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By execut- ing powerful instructions in a single clock cycle, the ATmega169P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram PF0 - PF7 PA0 - PA7 PC0 - PC7 XTAL2 XTAL1 VCC GND PORTF DRIVERS PORTA DRIVERS PORTC DRIVERS DATA REGISTER DATA DIR. DATA REGISTER DATA DIR. DATA REGISTER DATA DIR. PORTF REG. PORTF PORTA REG. PORTA PORTC REG. PORTC 8-BIT DATA BUS AVCC CALIB. OSC ADC INTERNAL OSCILLATOR AREF OSCILLATOR PROGRAM STACK WATCHDOG JTAG TAP COUNTER POINTER TIMER TIMING AND CONTROL LCD PROGRAM SRAM MCU CONTROL CONTROLLER/ ON-CHIP DEBUG FLASH REGISTER DRIVER BOUNDARY- INSTRUCTION TIMER/ GENERAL SCAN REGISTER COUNTERS PURPOSE REGISTERS X PROGRAMMING INSTRUCTION Y INTERRUPT LOGIC DECODER Z UNIT CONTROL LINES ALU EEPROM RESET STATUS AVR CPU REGISTER USART UNIVERSAL SPI SERIAL INTERFACE DATA REGISTER DATA DIR. DATA REGISTER DATA DIR. DATA REGISTER DATA DIR. DATA REG. DATA DIR. + - PORTE REG. PORTE PORTB REG. PORTB PORTD REG. PORTD PORTG REG. PORTG ANALOG COMPARATOR PORTE DRIVERS PORTB DRIVERS PORTD DRIVERS PORTG DRIVERS PE0 - PE7 PB0 - PB7 PD0 - PD7 PG0 - PG4 4 8018N–AVR–08/09 ATmega169P The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. The ATmega169P provides the following features: 16K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1K byte SRAM, 53 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, a complete On-chip LCD controller with internal step-up voltage, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8- channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer and the LCD controller continues to run, allowing the user to maintain a timer base and operate the LCD display while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer, LCD controller and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up com- bined with low-power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro- gram running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega169P is a powerful microcontroller that provides a highly flex- ible and cost effective solution to many embedded control applications.
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