An Open-Source Concolic Execution Engine for X86 Binaries
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A Scalable Concolic Testing Tool for Reliable Embedded Software
SCORE: a Scalable Concolic Testing Tool for Reliable Embedded Software Yunho Kim and Moonzoo Kim Computer Science Department Korea Advanced Institute of Science and Technology Daejeon, South Korea [email protected], [email protected] ABSTRACT cases to explore execution paths of a program, to achieve full path Current industrial testing practices often generate test cases in a coverage (or at least, coverage of paths up to some bound). manual manner, which degrades both the effectiveness and effi- A concolic testing tool extracts symbolic information from a ciency of testing. To alleviate this problem, concolic testing gen- concrete execution of a target program at runtime. In other words, erates test cases that can achieve high coverage in an automated to build a corresponding symbolic path formula, a concolic testing fashion. One main task of concolic testing is to extract symbolic in- tool monitors every update of symbolic variables and branching de- formation from a concrete execution of a target program at runtime. cisions in an execution of a target program. Thus, a design decision Thus, a design decision on how to extract symbolic information af- on how to extract symbolic information affects efficiency, effective- fects efficiency, effectiveness, and applicability of concolic testing. ness, and applicability of concolic testing. We have developed a Scalable COncolic testing tool for REliable We have developed a Scalable COncolic testing tool for REli- embedded software (SCORE) that targets embedded C programs. abile embedded software (SCORE) that targets sequential embed- SCORE instruments a target C program to extract symbolic infor- ded C programs. SCORE instruments a target C source code by mation and applies concolic testing to a target program in a scal- inserting probes to extract symbolic information at runtime. -
Automated Concolic Testing of Smartphone Apps
Automated Concolic Testing of Smartphone Apps Saswat Anand Mayur Naik Hongseok Yang Georgia Tech Georgia Tech University of Oxford [email protected] [email protected] [email protected] Mary Jean Harrold Georgia Tech [email protected] ABSTRACT tap on the device’s touch screen, a key press on the device’s We present an algorithm and a system for generating in- keyboard, and an 0,0 message are all instances of events. put events to exercise smartphone apps. Our approach is This paper presents an algorithm and a system for gener- based on concolic testing and generates sequences of events ating input events to exercise apps. pps can have inputs automatically and systematically. It alleviates the path- besides events! such as files on disk and secure web content. explosion problem by checking a condition on program exe- Our work is orthogonal and complementary to approaches cutions that identifies subsumption between different event that provide such inputs. sequences. We also describe our implementation of the ap- Apps are instances of a class of programs we call event- proach for Android, the most popular smartphone app plat- driven programs' programs embodying computation that form! and the results of an evaluation that demonstrates its is architected to react to a possibly unbounded sequence effectiveness on five ndroid apps. of events. 7vent-driven programs are ubiquitous and, be- sides apps! include stream-processing programs, web servers! GUIs, and embedded systems. 8ormally! we address the fol- Categories and Subject Descriptors lowing problem in the setting of event-driven programs in D.2.$ %Software Engineering&' (esting and Debugging) general, and apps in particular. -
Vax 6135 Car Vax Uk - Service Parts List
VAX 6135 CAR VAX UK - SERVICE PARTS LIST Item Vax Part No. Description Price Code Service Item Item Vax Part No. Description Price Code Service Item 2 1-2-31-01-006 FILTER-FOAM-EXHAUST S1 CS 34 1-2-30-01-015 SEAL-FILTER/RESERVOIR K1 S 5 1-2-11-04-007 CABLE CLAMP L1 CS 35 1-3-15-03-007 FILTER HSG ASSY-UNIV-BLACK T3 S 29 1-2-31-01-002 FILTER DISC-BONDINI A1 CS 39 1-2-14-02-001 BALL VALVE N1 S 32 1-2-31-01-007 FILTER -FIBRE-MOULDED X1 CS 40 1-3-09-06-007 RESERVOIR ASSY-UNIV-BLACK W3 S 44 1-3-13-02-001 UPHOLSTERY TOOL Y1 CS 41 1-2-30-02-002 SEAL-CONICAL DUCT D2 S 47 1-2-39-01-010 CREVICE TOOL Y1 CS 42 1-2-30-02-003 SEAL-EXHAUST D2 S 48 1-3-13-01-001 DUSTBRUSH H2 CS 43 1-2-124731-12 RECOVERY BUCKET/SPIDER ASSY Z3 S 50 1-2-13-02-002 TUBE-EXTN-STAINLESS B3 CS 45 1-2-32-01-002 CASTOR-TWO WHEEL X1 S 52 1-3-18-01-022 HOSE & GRIP ASSY W3 CS 60 1-9-124423-00 TUBE-PUMP TO QRV A1 S 53 1-9-124962-00 WASH HEAD J3 CS 62 1-1-06-01-073 FEMALE QRV ASSY S2 S 54 1-9-124961-00 FLOOR BRUSH F3 CS 63 1-3-124422-00 ELBOW-QRV-ET408 C2 S 64 1-2-11-03-007 RETAINER CLIP-SPRING H1 CS 65 1-2-13-04-008 INLET TUBE-PVC A1 S 74 1-2-124594-00 UPHOLSTERY WASH TOOL K3 CS 66 1-3-124424-00 FIXING STRAP-ET408 L1 S 75 1-9-125226-00 TURBO TOOL-100mm R3 CS 67 1-7-124677-00 FILTER-WATER-INLET E2 S 77 1-9-125549-00 CREVICE TOOL-EXTRA LONG G2 CS 68 1-5-124419-00 PUMP-ET408 S3 S 101 1-2-124805-00 WATER TUBE ASSY-STRAIGHT Z2 CS 69 1-6-124425-00 SEAL-PUMP ET408 L1 S 3 1-3-124588-03 COVER-ACCESS-B R GREEN X1 NS 99 1-2-07-03-001 DUCT-CONICAL X1 S 6 1-2-36-04-004 CORD PROTECTOR A1 NS 102 -
CS 6290 Chapter 1
Spring 2011 Prof. Hyesoon Kim Xbox 360 System Architecture, „Anderews, Baker • 3 CPU cores – 4-way SIMD vector units – 8-way 1MB L2 cache (3.2 GHz) – 2 way SMT • 48 unified shaders • 3D graphics units • 512-Mbyte DRAM main memory • FSB (Front-side bus): 5.4 Gbps/pin/s (16 pins) • 10.8 Gbyte/s read and write • Xbox 360: Big endian • Windows: Little endian http://msdn.microsoft.com/en-us/library/cc308005(VS.85).aspx • L2 cache : – Greedy allocation algorithm – Different workloads have different working set sizes • 2-way 32 Kbyte L1 I-cache • 4-way 32 Kbyte L1 data cache • Write through, no write allocation • Cache block size :128B (high spatial locality) • 2-way SMT, • 2 insts/cycle, • In-order issue • Separate vector/scalar issue queue (VIQ) Vector Vector Execution Unit Instructions Scalar Scalar Execution Unit • First game console by Microsoft, released in 2001, $299 Glorified PC – 733 Mhz x86 Intel CPU, 64MB DRAM, NVIDIA GPU (graphics) – Ran modified version of Windows OS – ~25 million sold • XBox 360 – Second generation, released in 2005, $299-$399 – All-new custom hardware – 3.2 Ghz PowerPC IBM processor (custom design for XBox 360) – ATI graphics chip (custom design for XBox 360) – 34+ million sold (as of 2009) • Design principles of XBox 360 [Andrews & Baker] - Value for 5-7 years -!ig performance increase over last generation - Support anti-aliased high-definition video (720*1280*4 @ 30+ fps) - extremely high pixel fill rate (goal: 100+ million pixels/s) - Flexible to suit dynamic range of games - balance hardware, homogenous resources - Programmability (easy to program) Slide is from http://www.cis.upenn.edu/~cis501/lectures/12_xbox.pdf • Code name of Xbox 360‟s core • Shared cell (playstation processor) ‟s design philosophy. -
Concolic Testing
DART and CUTE: Concolic Testing Koushik Sen University of California, Berkeley Joint work with Gul Agha, Patrice Godefroid, Nils Klarlund, Rupak Majumdar, Darko Marinov Used and adapted by Jonathan Aldrich, with permission, for 17-355/17-655 Program Analysis 3/28/2017 1 Today, QA is mostly testing “50% of my company employees are testers, and the rest spends 50% of their time testing!” Bill Gates 1995 2 Software Reliability Importance Software is pervading every aspects of life Software everywhere Software failures were estimated to cost the US economy about $60 billion annually [NIST 2002] Improvements in software testing infrastructure may save one- third of this cost Testing accounts for an estimated 50%-80% of the cost of software development [Beizer 1990] 3 Big Picture Safe Programming Languages and Type systems Model Testing Checking Runtime Static Program and Monitoring Analysis Theorem Proving Dynamic Program Analysis Model Based Software Development and Analysis 4 Big Picture Safe Programming Languages and Type systems Model Testing Checking Runtime Static Program and Monitoring Analysis Theorem Proving Dynamic Program Analysis Model Based Software Development and Analysis 5 A Familiar Program: QuickSort void quicksort (int[] a, int lo, int hi) { int i=lo, j=hi, h; int x=a[(lo+hi)/2]; // partition do { while (a[i]<x) i++; while (a[j]>x) j--; if (i<=j) { h=a[i]; a[i]=a[j]; a[j]=h; i++; j--; } } while (i<=j); // recursion if (lo<j) quicksort(a, lo, j); if (i<hi) quicksort(a, i, hi); } 6 A Familiar Program: QuickSort void quicksort -
MPC5634M Microcontroller Data Sheet, Rev
Freescale Semiconductor MPC5634M Rev. 9.2, 01/2015 MPC5634M Microcontroller Datasheet This is the MPC5634M Datasheet set consisting of the following files: • MPC5634M Datasheet Addendum (MPC5634M_AD), Rev. 1 • MPC5634M Datasheet (MPC5634M), Rev. 9 © Freescale Semiconductor, Inc., 2015. All rights reserved. Freescale Semiconductor MPC5634M_AD Datasheet Addendum Rev. 1.0, 01/2015 MPC5634M Microcontroller Datasheet Addendum This addendum describes corrections to the MPC5634M Table of Contents Microcontroller Datasheet, order number MPC5634M. 1 Addendum List for Revision 9 . 2 For convenience, the addenda items are grouped by 2 Revision History . 2 revision. Please check our website at http://www.freescale.com/powerarchitecture for the latest updates. The current version available of the MPC5634M Microcontroller Datasheet is Revision 9. © Freescale Semiconductor, Inc., 2015. All rights reserved. 1 Addendum List for Revision 9 4 Table 1. MPC5634M Rev 9 Addendum Location Description Section 4.11, “Temperature In “Temperature Sensor Electrical Characteristics” table, update the Min and Max value of Sensor Electrical “Accuracy” parameter to -20oC and +20oC, respectively. Characteristics”, Page 81 2 Revision History Table 2 provides a revision history for this datasheet addendum document. Table 2. Revision History Table Rev. Number Substantive Changes Date of Release 1.0 Initial release. 12/2014 MPC5634M_AD, Rev. 1.0 2 Freescale Semiconductor How to Reach Us: Information in this document is provided solely to enable system and software Home Page: implementers to use Freescale products. There are no express or implied copyright freescale.com licenses granted hereunder to design or fabricate any integrated circuits based on the Web Support: information in this document. freescale.com/support Freescale reserves the right to make changes without further notice to any products herein. -
Automated Synthesis of Symbolic Instruction Encodings from I/O Samples
Automated Synthesis of Symbolic Instruction Encodings from I/O Samples Patrice Godefroid Ankur Taly Microsoft Research Stanford University PLDI’2012 Page 1 June 2012 Need for Symbolic Instruction Encodings Symbolic Execution is a key l 1 : m o v eax, i n p 1 component of precise binary m o v c l , i n p 2 program analysis tools s h l eax, c l j n z l2 j m p l3 - SAGE, BitBlaze, BAP, etc. l 2 : d i v ebx, eax // Is this safe ? - Static analysis tools / / I s e a x ! = 0 ? l 3 : … PLDI’2012 Page 2 June 2012 Problem: Symbolic Instruction Encoding Bit Vector[X] Instruction Bit Vector[Y] Inp 1 ? Op1 Inpn Opm Problem: Given a processor and an instruction name, symbolically describe the input-output function for the instruction • Express the encoding as bit-vector constraints (ex: SMT-Lib format) PLDI’2012 Page 3 June 2012 So far, only manual solutions… • From the instruction architecture manual (X86, ARM, …) implemented by the processor Limitations: • Tedious, expensive - X86 has more than 300 unique instructions, each with ~10 OPCodes, 2000 pages • Error-prone - Written in English, many corner cases • Imprecise - Spec is often under-specified • Partial - Not all instructions are covered X86 spec for SHLD • Can we trust the spec ? PLDI’2012 Page 4 June 2012 Here: Automated Synthesis Approach Searches for a function f that respects truth table Partial Truth- table S Sample inputs Synthesis Function (C with in-lined engine f assembly) Goals: • As automated as possible so that we can boot-strap a symbolic execution engine on an arbitrary instruction -
Toshiba 32-Bit Arm Core-Based Microcontroller Product Guide
SUBSIDIARIES AND AFFILIATES (As of July 1, 2017) Toshiba America Toshiba Electronics Europe GmbH Toshiba Electronics Asia, Ltd. Nov. 2017 Semiconductor Catalog Nov. 2017 Electronic Components, Inc. • Düsseldorf Head Office Tel: 2375-6111 Fax: 2375-0969 • Irvine, Headquarters Tel: (0211)5296-0 Fax: (0211)5296-400 Toshiba Electronics (China) Co., Ltd. BCE0085H Tel: (949)462-7700 Fax: (949)462-2200 • France Branch • Shanghai Head Office • Buffalo Grove (Chicago) Tel: (1)47282181 Tel: (021)6139-3888 Fax: (021)6190-8288 Tel: (847)484-2400 Fax: (847)541-7287 • Italy Branch • Beijing Branch • Duluth/Atlanta Tel: (039)68701 Fax:(039)6870205 Tel: (010)6590-8796 Fax: (010)6590-8791 Tel: (404)639-9520 Fax: (404)634-4434 • Munich Office • Chengdu Branch • El Paso Tel: (089)20302030 Fax: (089)203020310 Tel: (028)8675-1773 Fax: (028)8675-1065 Tel: (915)533-4242 • Spain Branch • Hangzhou Office • Marlborough Tel: (91)660-6794 Tel: (0571)8717-5004 Fax: (0571)8717-5013 Tel: (508)481-0034 Fax: (508)481-8828 • Sweden Branch • Nanjing Office • Parsippany Tel: (08)704-0900 Fax: (08)80-8459 Tel: (025)8689-0070 Fax: (025)5266-5106 Tel: (973)541-4715 Fax: (973)541-4716 • U.K. Branch • Qingdao Branch 32-Bit Microcontrollers 32-Bit Microcontrollers • San Jose Tel: (1932)841600 Tel: (532)8579-3328 Fax: (532)8579-3329 Tel: (408)526-2400 Fax: (408)526-2410 Toshiba Electronics Asia (Singapore) Pte. Ltd. • Shenzhen Branch • Wixom (Detroit) Tel: (65)6278-5252 Fax: (65)6271-5155 Tel: (0755)3686-0880 Fax: (0755)3686-0816 Tel: (248)347-2607 Fax: (248)347-2602 Toshiba Electronics Service (Thailand) Co., Ltd. -
Advanced Software Testing and Debugging (CS598) Symbolic Execution
Advanced Software Testing and Debugging (CS598) Symbolic Execution Fall 2020 Lingming Zhang Brief history • 1976: A system to generate test data and symbolically execute programs (Lori Clarke) • 1976: Symbolic execution and program testing (James King) • 2005-present: practical symbolic execution • Using SMT solvers • Heuristics to control exponential explosion • Heap modeling and reasoning about pointers • Environment modeling • Dealing with solver limitations 2 Program execution paths if (a) • Program can be viewed as binary … tree with possibly infinite depth if (b) … • Each node represents the execution of a conditional statement if(a) • Each edge represents the F T execution of a sequence of non- if(b) if(b) conditional statements F T F T • Each path in the tree represents an equivalence class of inputs 3 Example a==null F T Code under test a.Length>0 void CoverMe(int[] a) { T a==null if (a == null) F return; a[0]==123… if (a.Length > 0) a!=null && F T if (a[0] == 1234567890) a.Length<=0 throw new Exception("bug"); } a!=null && a!=null && a.Length>0 && a.Length>0 && a[0]!=1234567890 a[0]==1234567890 4 Random testing? • Random Testing Code under test • Generate random inputs void CoverMe(int[] a) { if (a == null) • Execute the program on return; those (concrete) inputs if (a.Length > 0) if (a[0] == 1234567890) • Problem: throw new Exception("bug"); • Probability of reaching error could } be astronomically small Probability of ERROR for the gray branch: 1/232 ≈ 0.000000023% 5 The spectrum of program testing/verification Verification -
Z3/EV Z3/EV Is One of the Experiment Boards That Constitute the Interactive Practical Electronics System – I.P.E.S
INTRODUCTION Z3/EV Z3/EV is one of the experiment boards that constitute the Interactive Practical Electronics System – I.P.E.S. It consists of a set of components and circuits for performing BE (32 BIT experiments. The lessons included in this module can be developed in: MICROPROCESSORS) - Standard mode: using the switches of the equipment and consulting the handbook; -Computerized mode: the interactive software version of the handbook - SW-D-Z3/EV - interfaced to the module via Control Unit SIS3-U/EV, is used. This software inserts circuit variations and faults automatically enabling the development of lessons even without teacher’s assistance. Z3/EV The Z3/EV 32-bit microprocessor board is a system developed for studying the most advanced microprocessors, and their most important applications. It contains all typical components of microprocessor systems: the microprocessor, RAM, EPROM, digital and analog I/O devices, etc. The choice of the microprocessor used also on Personal Computers makes it a necessary educational equipment for studying the hardware and software structure of the Personal Computer. The instructions of the program to be carried out are usually entered from the keyboard and displayed on the module TRAINING PROGRAM: display. • Programming of 32-bit microprocessor systems: ELECTRONICS AND SYSTEMS When the complexity of the applications to be developed programming introduction, machine code and assembler increases, the system can be connected to a Personal Computer language programming, advanced programming; creating -
Problem Solving and Troubleshooting in AIX 5L
Front cover Problem Solving and Troubleshooting in AIX 5L Introduction of new problem solving tools and changes in AIX 5L Step by step troubleshooting in real environments Complete guide to the problem determination process HyunGoo Kim JaeYong An John Harrison Tony Abruzzesse KyeongWon Jeong ibm.com/redbooks International Technical Support Organization Problem Solving and Troubleshooting in AIX 5L January 2002 SG24-5496-01 Take Note! Before using this information and the product it supports, be sure to read the general information in “Special notices” on page 439. Second Edition (January 2002) This edition applies to IBM ^ pSeries and RS/6000 Systems for use with the AIX 5L Operating System Version 5.1 and is based on information available in August, 2001. Comments may be addressed to: IBM Corporation, International Technical Support Organization Dept. JN9B Building 003 Internal Zip 2834 11400 Burnet Road Austin, Texas 78758-3493 When you send information to IBM, you grant IBM a non-exclusive right to use or distribute the information in any way it believes appropriate without incurring any obligation to you. © Copyright International Business Machines Corporation 1999-2002. All rights reserved. Note to U.S Government Users – Documentation related to restricted rights – Use, duplication or disclosure is subject to restrictions set forth in GSA ADP Schedule Contract with IBM Corp. Contents Figures . xiii Tables . xv Preface . xvii The team that wrote this redbook. xvii Special notice . xix IBM trademarks . xix Comments welcome. xix Chapter 1. Problem determination introduction. 1 1.1 Problem determination process . 3 1.1.1 Defining the problem . 3 1.1.2 Gathering information from the user . -
8-Bit Microcontroller with 16K Bytes In-System
Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-Chip 2-cycle Multiplier • High Endurance Non-volatile Memory segments – 16K Bytes of In-System Self-programmable Flash program memory – 512 Bytes EEPROM – 1K Bytes Internal SRAM 8-bit – Write/Erase cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C(1) – Optional Boot Code Section with Independent Lock Bits Microcontroller In-System Programming by On-chip Boot Program True Read-While-Write Operation with 16K Bytes – Programming Lock for Software Security • JTAG (IEEE std. 1149.1 compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard In-System – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Programmable • Peripheral Features – 4 x 25 Segment LCD Driver Flash – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator –Four PWM Channels ATmega169P – 8-channel, 10-bit ADC – Programmable Serial USART ATmega169PV – Master/Slave SPI Serial Interface – Universal Serial Interface with Start Condition Detector – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up