<<

Let's Make an Circuit

Goal. x + y = z for 4- .

 We build 4-bit adder: 9 inppputs, 4 outputs.

 Same idea scales to 128-bit adder.

 Key component. 1 1 1 0 Unit (ALU) 2 4 8 7 + 3 5 7 9

6 0 6 6 Introduction to Computer Yung-Yu Chuang

with slides by Sedgewick & Wayne (introcs.cs.princeton.edu), Nisan & Schocken (www.nand2tetris.org) and Harris & Harris (DDCA) 2

Binary Representing negative numbers (4-bit system)

0 0000  The codes of all positive numbers begin with a “0” Assuming a 4-bit system: 1 0001 1111 -1 2 0010 1110 -2  The codes of all negative numbers 3 0011 1101 -3 begin with a “1“ 0 0 0 1 1 1 1 1 4 0100 1100 -4  To convert a number: 1 0 0 1 + 1 0 1 1 + 0 1 0 1 0 1 1 1 5 0101 1011 -5 leave all trailing 0’s and first 1 intact, 6 0110 1010 -6 and flip all the remaining 0 1 1 1 0 1 0 0 1 0 7 0111 1001 -7 1000 -8 no overflow overflow

Example: 2 - 5 = 2 + (-5) = 0 0 1 0  : exactly the same as in addition + 1 0 1 1  Overflow (MSB ) has to be dealt with. 11011 1 0 1 = -3

Elements of Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 3 Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 4 Let's Make an Adder Circuit Let's Make an Adder Circuit

c Step 1. Represent input and output in binary. Goal. x + y = z for 4-bit integers. out in x3 x2 x1 x0 Step 2. [first attempt] + y3 y2 y1 y0 1 1 0 0 z0  Build truth table. 0 0 1 0 4-Bit Adder Truth Table + 0 1 1 1 c0 x3 x2 x1 x0 y3 y2 y1 y0 z3 z2 z1 z0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0

x3 x2 x1 x0 0 0 0 0 0 0 0 1 1 0 0 1 1 28+1 = 512 rows! 0 0 0 0 0 0 1 0 0 0 1 0 0 + y3 y2 y1 y0 ...... z3 z2 z1 z0 1 1 1 1 1 1 1 1 1 1 1 1 1 Q. Why is this a bad idea? A. 128-bit adder: 2256+1 rows >> # electrons in universe! 5 6

1-bit half adder 1-bit full adder

We add numbers one bit at a time. x y x y Cin Cout s x c ADD Cin y s ADD Cout s x y sc

7 8 8-bit adder Let's Make an Adder Circuit

Goal. x + y = z for 4-bit integers.cout c3 c2 c1 c0 = 0

x3 x2 x1 x0 Step 2. [do one bit at a time] + y3 y2 y1 y0 z3 z2 z1 z0  Build truth table for carry bit.

 Build truth table for summand bit.

Carry Bit Summand Bit

xi yi ci ci+1 xi yi ci zi 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 1 0 1 1 0 1 0 0 0 1 0 0 1 1 0 1 1 1 0 1 0 1 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1

9 10

Let's Make an Adder Circuit Let's Make an Adder Circuit

Goal. x + y = z for 4-bit integers. Goal. x + y = z for 4-bit integers.

Step 3. Step 4.

 Derive (simplified) Boolean expression.  Transform Boolean expression into circuit.

 Chain together 1-bit adders.

Carry Bit Summand Bit

xi yi ci ci+1 MAJ xi yi ci zi ODD 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 1 1 0 1 1 0 0 1 0 0 0 0 1 0 0 1 1 1 0 1 1 1 1 0 1 0 0 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1

11 12 Adder: Adder: Component Level View

13 14

Adder: Level View

Subtractor circuit: z = x – y.

 One approach: desig n like adder circuit

15 Subtractor Subtractor

Subtractor circuit: z = x – y. Subtractor circuit: z = x – y.

 One approach: desig n like adder circuit  One approach: desig n like adder circuit

 Better idea: reuse adder circuit  Better idea: reuse adder circuit – 2’s complement: to negate an , flip bits, then add 1 – 2’s complement: to negate an integer, flip bits, then add 1

17 18

Shifter Shifter

Only one of them will be on at a time.

s0 s1 s2 s3 z0 z1 z2 z3 s x0 0 s1 x1 s SHIFT 2 x2 s3

x3

z0 z1 z2 z3

4-bit Shifter

19 20 Shifter Shifter

z0 z1 z2 z3 s0 x0 x1 x2 x3 s1 0 x0 x1 x2 s2 00x0 x1 s3 0 0 0 x0

z0 = s0‧x0 + s1‧0 + s2‧0 + s3‧0 z0 = s0‧x0 + s1‧0 + s2‧0 + s3‧0 z1 = s0‧x1 + s1‧x0 + s2‧0 + s3‧0 z1 = s0‧x1 + s1‧x0 + s2‧0 + s3‧0 z2 = s0‧x2 + s1‧x1 + s2‧x0 + s3‧0 z2 = s0‧x2 + s1‧x1 + s2‧x0 + s3‧0 z3 = s0‧x3 + s1‧x2 + s2‧x1 + s3‧x0 z3 = s0‧x3 + s1‧x2 + s2‧x1 + s3‧x0

21 22

N-bit Decoder N-bit Decoder

N-bit decoder N-bit decoder N N  N address inputs, 2 outputs  N address inputs, 2 data outputs

 Addresses output bit is 1;  Addresses output bit is 1; all others are 0 all others are 0

23 24 2-Bit Decoder Controlling 4-Bit Shifter

Ex. Put in a binary amount r 0 r 1 to shift. Arithmetic logic unit (ALU). Computes all oppperations in .

 Add and subtract.

 Xor.

 AdAnd.

 Shift left or right.

Q. How to select desired answer?

25 26

1 Hot OR 1 Hot OR . 1 hot OR. adder x 1 = x x.0 = 0  All devices compute their answer; adder we pick one.

 Exactly one select line is on. x + 0 = x xor  Implies exactly one output line is relevant. xor decoder

x.1 = x . shifter x 0 = 0 shift x + 0 = x

27 28 Bitwise AND, XOR, NOT

16-bit bus Bitwise logical operations

  Buufwndle of 16 wires Inppyuts x and y: n bits each

  Memory transfer Output z: n bits Register transfer  Apply logical operation to each corresponding pair of bits

8-bit bus

 Bundle of 8 wires

 TOY

4-bit bus

 Bundle of 4 wires

 TOY register address

29 30

TOY ALU Device Interface Using Buses

16-bit words for TOY memory TOY ALU Device. Processes a word at a time.  Biggg Input bus. Wires on top.  16-bit bus Output bus. Wires on bottom.  Add, subtract, and, xor, shift left, shift right, Control. Individual wires on side. copy input 2

31 32 ALU

Arithmetic logic unit.

 Add and subtract.

 Xor.

 And.

 Shift left or right.

Arithmetic logic unit.

 Computes all operations in parallel.

 Uses 1-hot OR to pick each bit answer.

How to convert to 1-hot OR ?

33 34

Hack ALU

16 x 16-bit 16 16 adde r out y

zx nx zy ny f no out(x, y, control bits) = x+y, x-y, y–x, 0, 1, -1, x 16 bits x, y, -x, -y, ALU out y 16 bits x!, y!, 16 bits x+1, y+1, x-1y1, y-1, x&y, x|y zr ng

35 Hack ALU The ALU in the CPU context (a sneak preview of the Hack platform)

c1,c2, … ,c6

D D register

a ALU out A A register

M A/M ux

RAM M

(selected register)

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 38

Perspective

 Combinational logic

 Our adder design is very : no parallelism

 It pays to optimize adders

 Our ALU is also very basic: no , no division

 Where is the seat of more ad van ced math op erati ons? a typical hardware/ tradeoff.

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 39