Computer Architecture and Implementation
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Vcf Pnw 2019
VCF PNW 2019 http://vcfed.org/vcf-pnw/ Schedule Saturday 10:00 AM Museum opens and VCF PNW 2019 starts 11:00 AM Erik Klein, opening comments from VCFed.org Stephen M. Jones, opening comments from Living Computers:Museum+Labs 1:00 PM Joe Decuir, IEEE Fellow, Three generations of animation machines: Atari and Amiga 2:30 PM Geoff Pool, From Minix to GNU/Linux - A Retrospective 4:00 PM Chris Rutkowski, The birth of the Business PC - How volatile markets evolve 5:00 PM Museum closes - come back tomorrow! Sunday 10:00 AM Day two of VCF PNW 2019 begins 11:00 AM John Durno, The Lost Art of Telidon 1:00 PM Lars Brinkhoff, ITS: Incompatible Timesharing System 2:30 PM Steve Jamieson, A Brief History of British Computing 4:00 PM Presentation of show awards and wrap-up Exhibitors One of the defining attributes of a Vintage Computer Festival is that exhibits are interactive; VCF exhibitors put in an amazing amount of effort to not only bring their favorite pieces of computing history, but to make them come alive. Be sure to visit all of them, ask questions, play, learn, take pictures, etc. And consider coming back one day as an exhibitor yourself! Rick Bensene, Wang Laboratories’ Electronic Calculators, An exhibit of Wang Labs electronic calculators from their first mass-market calculator, the Wang LOCI-2, through the last of their calculators, the C-Series. The exhibit includes examples of nearly every series of electronic calculator that Wang Laboratories sold, unusual and rare peripheral devices, documentation, and ephemera relating to Wang Labs calculator business. -
Chapter 1 a Mistake.” Wang Qishan, Mayor of Beijing Introduction
c01:chapter-01 10/6/2010 10:43 PM Page 3 ““No one can avoid making a mistake, but one should not repeat Chapter 1 a mistake.” Wang Qishan, Mayor of Beijing Introduction The quotation that opens this chapter, which appeared in a popular Beijing newspaper, is very telling about life in China today. Years ago, one would not admit to having made a mistake, as there could be serious consequences. Today, as Chinese thinking merges more and more with that of the West, it is becoming more common to admit to one’s mistakes. But the long-held fear of being wrong continues, as the second part of the quotation indicates. It is okay to be wrong about something once, but not twice. In China, one works very hard to be right. Sometimes, to avoid being wrong, a Chinese person will choose not to act. This topic takes us to the subject of business leadership. What does it take to be a great leader in China? What is different about leadership in China compared to elsewhere in the world? Leadership is a huge issue for businesses in China, especially today. This book is intended to provide answers to those questions, as well as to outline what companies in China—both foreign and local firms—canCOPYRIGHTED do now to improve the abilitiesMATERIAL of their leaders. Thousands of books have been written on business leadership. Many of these have been translated into Chinese and have been read by Chinese business people. China has an enormous need to improve the quality of its leadership, and its current and future leaders have a craving for information that will help them get to the top. -
Wang Laboratories 2200 Series
C21-908-101 Programmable Terminals Wang Laboratories 2200 Series MANAGEMENT SUMMARY A series of five minicomputer systems that Wang Laboratories' 2200 Series product line currently offer both batch and interactive communica consists of the 2200VP, 2200MVP, 2200LVP and tions capabilities. 2200SVP processors, all of which are multi-user or multi user upgradeable systems. The 2200 Series product line Emulation packages are provided for standard also includes the 2200 PCS-I1I, a packaged system which Teletype communications; IBM 2741 emula is single-user oriented. tion; IBM 2780, 3780, and 3741 batch terminal communications; and IBM 3270 The CPU and floppy disk drive are packaged together interactive communications. with appropriate cables and a cabinet to produce an integrated system. The 2200 PCS-I1I includes the CPU, A basic 2200PCS-1II with 32K bytes of user CRT, keyboard and single-sided double density memory, a CRT display, and a minidiskette minidiskette drive in a standard CRT-size enclosure as drive is priced at $6,500. Prices range well as an optional disk multiplexer controller. The upward to $21,000 for a 2200MVP proc number of peripherals that can be attached to a given essor with 256K bytes of user memory, system depends on the number of I/O slots that are excluding peripherals. Leases and rental plans available, with most peripherals requiring one slot. In all are also available. 2200 Series CPUs, highly efficient use of memory is achieved through the use of separate control memory to store the BASIC-2 interpreter and operating system. CHARACTERISTICS Wang began marketing the original 2200 Series in the VENDOR: Wang Laboratories,lnc., One Industrial Avenue, Spring of 1973. -
Computer Architectures
Computer Architectures Central Processing Unit (CPU) Pavel Píša, Michal Štepanovský, Miroslav Šnorek The lecture is based on A0B36APO lecture. Some parts are inspired by the book Paterson, D., Henessy, V.: Computer Organization and Design, The HW/SW Interface. Elsevier, ISBN: 978-0-12-370606-5 and it is used with authors' permission. Czech Technical University in Prague, Faculty of Electrical Engineering English version partially supported by: European Social Fund Prague & EU: We invests in your future. AE0B36APO Computer Architectures Ver.1.10 1 Computer based on von Neumann's concept ● Control unit Processor/microprocessor ● ALU von Neumann architecture uses common ● Memory memory, whereas Harvard architecture uses separate program and data memories ● Input ● Output Input/output subsystem The control unit is responsible for control of the operation processing and sequencing. It consists of: ● registers – they hold intermediate and programmer visible state ● control logic circuits which represents core of the control unit (CU) AE0B36APO Computer Architectures 2 The most important registers of the control unit ● PC (Program Counter) holds address of a recent or next instruction to be processed ● IR (Instruction Register) holds the machine instruction read from memory ● Another usually present registers ● General purpose registers (GPRs) may be divided to address and data or (partially) specialized registers ● SP (Stack Pointer) – points to the top of the stack; (The stack is usually used to store local variables and subroutine return addresses) ● PSW (Program Status Word) ● IM (Interrupt Mask) ● Optional Floating point (FPRs) and vector/multimedia regs. AE0B36APO Computer Architectures 3 The main instruction cycle of the CPU 1. Initial setup/reset – set initial PC value, PSW, etc. -
Microprocessor Architecture
EECE416 Microcomputer Fundamentals Microprocessor Architecture Dr. Charles Kim Howard University 1 Computer Architecture Computer System CPU (with PC, Register, SR) + Memory 2 Computer Architecture •ALU (Arithmetic Logic Unit) •Binary Full Adder 3 Microprocessor Bus 4 Architecture by CPU+MEM organization Princeton (or von Neumann) Architecture MEM contains both Instruction and Data Harvard Architecture Data MEM and Instruction MEM Higher Performance Better for DSP Higher MEM Bandwidth 5 Princeton Architecture 1.Step (A): The address for the instruction to be next executed is applied (Step (B): The controller "decodes" the instruction 3.Step (C): Following completion of the instruction, the controller provides the address, to the memory unit, at which the data result generated by the operation will be stored. 6 Harvard Architecture 7 Internal Memory (“register”) External memory access is Very slow For quicker retrieval and storage Internal registers 8 Architecture by Instructions and their Executions CISC (Complex Instruction Set Computer) Variety of instructions for complex tasks Instructions of varying length RISC (Reduced Instruction Set Computer) Fewer and simpler instructions High performance microprocessors Pipelined instruction execution (several instructions are executed in parallel) 9 CISC Architecture of prior to mid-1980’s IBM390, Motorola 680x0, Intel80x86 Basic Fetch-Execute sequence to support a large number of complex instructions Complex decoding procedures Complex control unit One instruction achieves a complex task 10 -
What Do We Mean by Architecture?
Embedded programming: Comparing the performance and development workflows for architectures Embedded programming week FABLAB BRIGHTON 2018 What do we mean by architecture? The architecture of microprocessors and microcontrollers are classified based on the way memory is allocated (memory architecture). There are two main ways of doing this: Von Neumann architecture (also known as Princeton) Von Neumann uses a single unified cache (i.e. the same memory) for both the code (instructions) and the data itself, Under pure von Neumann architecture the CPU can be either reading an instruction or reading/writing data from/to the memory. Both cannot occur at the same time since the instructions and data use the same bus system. Harvard architecture Harvard architecture uses different memory allocations for the code (instructions) and the data, allowing it to be able to read instructions and perform data memory access simultaneously. The best performance is achieved when both instructions and data are supplied by their own caches, with no need to access external memory at all. How does this relate to microcontrollers/microprocessors? We found this page to be a good introduction to the topic of microcontrollers and microprocessors, the architectures they use and the difference between some of the common types. First though, it’s worth looking at the difference between a microprocessor and a microcontroller. Microprocessors (e.g. ARM) generally consist of just the Central Processing Unit (CPU), which performs all the instructions in a computer program, including arithmetic, logic, control and input/output operations. Microcontrollers (e.g. AVR, PIC or 8051) contain one or more CPUs with RAM, ROM and programmable input/output peripherals. -
Computer Organization and Architecture Designing for Performance Ninth Edition
COMPUTER ORGANIZATION AND ARCHITECTURE DESIGNING FOR PERFORMANCE NINTH EDITION William Stallings Boston Columbus Indianapolis New York San Francisco Upper Saddle River Amsterdam Cape Town Dubai London Madrid Milan Munich Paris Montréal Toronto Delhi Mexico City São Paulo Sydney Hong Kong Seoul Singapore Taipei Tokyo Editorial Director: Marcia Horton Designer: Bruce Kenselaar Executive Editor: Tracy Dunkelberger Manager, Visual Research: Karen Sanatar Associate Editor: Carole Snyder Manager, Rights and Permissions: Mike Joyce Director of Marketing: Patrice Jones Text Permission Coordinator: Jen Roach Marketing Manager: Yez Alayan Cover Art: Charles Bowman/Robert Harding Marketing Coordinator: Kathryn Ferranti Lead Media Project Manager: Daniel Sandin Marketing Assistant: Emma Snider Full-Service Project Management: Shiny Rajesh/ Director of Production: Vince O’Brien Integra Software Services Pvt. Ltd. Managing Editor: Jeff Holcomb Composition: Integra Software Services Pvt. Ltd. Production Project Manager: Kayla Smith-Tarbox Printer/Binder: Edward Brothers Production Editor: Pat Brown Cover Printer: Lehigh-Phoenix Color/Hagerstown Manufacturing Buyer: Pat Brown Text Font: Times Ten-Roman Creative Director: Jayne Conte Credits: Figure 2.14: reprinted with permission from The Computer Language Company, Inc. Figure 17.10: Buyya, Rajkumar, High-Performance Cluster Computing: Architectures and Systems, Vol I, 1st edition, ©1999. Reprinted and Electronically reproduced by permission of Pearson Education, Inc. Upper Saddle River, New Jersey, Figure 17.11: Reprinted with permission from Ethernet Alliance. Credits and acknowledgments borrowed from other sources and reproduced, with permission, in this textbook appear on the appropriate page within text. Copyright © 2013, 2010, 2006 by Pearson Education, Inc., publishing as Prentice Hall. All rights reserved. Manufactured in the United States of America. -
Three-Dimensional Integrated Circuit Design: EDA, Design And
Integrated Circuits and Systems Series Editor Anantha Chandrakasan, Massachusetts Institute of Technology Cambridge, Massachusetts For other titles published in this series, go to http://www.springer.com/series/7236 Yuan Xie · Jason Cong · Sachin Sapatnekar Editors Three-Dimensional Integrated Circuit Design EDA, Design and Microarchitectures 123 Editors Yuan Xie Jason Cong Department of Computer Science and Department of Computer Science Engineering University of California, Los Angeles Pennsylvania State University [email protected] [email protected] Sachin Sapatnekar Department of Electrical and Computer Engineering University of Minnesota [email protected] ISBN 978-1-4419-0783-7 e-ISBN 978-1-4419-0784-4 DOI 10.1007/978-1-4419-0784-4 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2009939282 © Springer Science+Business Media, LLC 2010 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) Foreword We live in a time of great change. -
CMPS 161 – Algorithm Design and Implementation I Current Course Description
CMPS 161 – Algorithm Design and Implementation I Current Course Description: Credit 3 hours. Prerequisite: Mathematics 161 or 165 or permission of the Department Head. Basic concepts of computer programming, problem solving, algorithm development, and program coding using a high-level, block structured language. Credit may be given for both Computer Science 110 and 161. Minimum Topics: • Fundamental programming constructs: Syntax and semantics of a higher-level language; variables, types, expressions, and assignment; simple I/O; conditional and iterative control structures; functions and parameter passing; structured decomposition • Algorithms and problem-solving: Problem-solving strategies; the role of algorithms in the problem- solving process; implementation strategies for algorithms; debugging strategies; the concept and properties of algorithms • Fundamental data structures: Primitive types; single-dimension and multiple-dimension arrays; strings and string processing • Machine level representation of data: Bits, bytes and words; numeric data representation; representation of character data • Human-computer interaction: Introduction to design issues • Software development methodology: Fundamental design concepts and principles; structured design; testing and debugging strategies; test-case design; programming environments; testing and debugging tools Learning Objectives: Students will be able to: • Analyze and explain the behavior of simple programs involving the fundamental programming constructs covered by this unit. • Modify and expand short programs that use standard conditional and iterative control structures and functions. • Design, implement, test, and debug a program that uses each of the following fundamental programming constructs: basic computation, simple I/O, standard conditional and iterative structures, and the definition of functions. • Choose appropriate conditional and iteration constructs for a given programming task. • Apply the techniques of structured (functional) decomposition to break a program into smaller pieces. -
Skepu 2: Flexible and Type-Safe Skeleton Programming for Heterogeneous Parallel Systems
Int J Parallel Prog DOI 10.1007/s10766-017-0490-5 SkePU 2: Flexible and Type-Safe Skeleton Programming for Heterogeneous Parallel Systems August Ernstsson1 · Lu Li1 · Christoph Kessler1 Received: 30 September 2016 / Accepted: 10 January 2017 © The Author(s) 2017. This article is published with open access at Springerlink.com Abstract In this article we present SkePU 2, the next generation of the SkePU C++ skeleton programming framework for heterogeneous parallel systems. We critically examine the design and limitations of the SkePU 1 programming interface. We present a new, flexible and type-safe, interface for skeleton programming in SkePU 2, and a source-to-source transformation tool which knows about SkePU 2 constructs such as skeletons and user functions. We demonstrate how the source-to-source compiler transforms programs to enable efficient execution on parallel heterogeneous systems. We show how SkePU 2 enables new use-cases and applications by increasing the flexibility from SkePU 1, and how programming errors can be caught earlier and easier thanks to improved type safety. We propose a new skeleton, Call, unique in the sense that it does not impose any predefined skeleton structure and can encapsulate arbitrary user-defined multi-backend computations. We also discuss how the source- to-source compiler can enable a new optimization opportunity by selecting among multiple user function specializations when building a parallel program. Finally, we show that the performance of our prototype SkePU 2 implementation closely matches that of -
Software Requirements Implementation and Management
Software Requirements Implementation and Management Juho Jäälinoja¹ and Markku Oivo² 1 VTT Technical Research Centre of Finland P.O. Box 1100, 90571 Oulu, Finland [email protected] tel. +358-40-8415550 2 University of Oulu P.O. Box 3000, 90014 University of Oulu, Finland [email protected] tel. +358-8-553 1900 Abstract. Proper elicitation, analysis, and documentation of requirements at the beginning of a software development project are considered important preconditions for successful software development. Furthermore, successful development requires that the requirements be correctly implemented and managed throughout the rest of the development. This latter success criterion is discussed in this paper. The paper presents a taxonomy for requirements implementation and management (RIM) and provides insights into the current state of these practices in the software industry. Based on the taxonomy and the industrial observations, a model for RIM is elaborated. The model describes the essential elements needed for successful implementation and management of requirements. In addition, three critical elements of the model with which the practitioners are currently struggling are discussed. These elements were identified as (1) involvement of software developers in system level requirements allocation, (2) work product verification with reviews, and (3) requirements traceability. Keywords: Requirements engineering, software requirements, requirements implementation, requirements management 1/9 1. INTRODUCTION Among the key concepts of efficient software development are proper elicitation, analysis, and documentation of requirements at the beginning of a project and correct implementation and management of these requirements in the later stages of the project. In this paper, the latter issue related to the life of software requirements beyond their initial development is discussed. -
Please Replace the Following Pages in the Book. 26 Microcontroller Theory and Applications with the PIC18F
Please replace the following pages in the book. 26 Microcontroller Theory and Applications with the PIC18F Before Push After Push Stack Stack 16-bit Register 0120 143E 20C2 16-bit Register 0120 SP 20CA SP 20C8 143E 20C2 0703 20C4 0703 20C4 F601 20C6 F601 20C6 0706 20C8 0706 20C8 0120 20CA 20CA 20CC 20CC 20CE 20CE Bottom of Stack FIGURE 2.12 PUSH operation when accessing a stack from the bottom Before POP After POP Stack 16-bit Register A286 16-bit Register 0360 Stack 143E 20C2 SP 20C8 SP 20CA 143E 20C2 0705 20C4 0705 20C4 F208 20C6 F208 20C6 0107 20C8 0107 20C8 A286 20CA A286 20CA 20CC 20CC Bottom of Stack FIGURE 2.13 POP operation when accessing a stack from the bottom Note that the stack is a LIFO (last in, first out) memory. As mentioned earlier, a stack is typically used during subroutine CALLs. The CPU automatically PUSHes the return address onto a stack after executing a subroutine CALL instruction in the main program. After executing a RETURN from a subroutine instruction (placed by the programmer as the last instruction of the subroutine), the CPU automatically POPs the return address from the stack (previously PUSHed) and then returns control to the main program. Note that the PIC18F accesses the stack from the top. This means that the stack pointer in the PIC18F holds the address of the bottom of the stack. Hence, in the PIC18F, the stack pointer is incremented after a PUSH, and decremented after a POP. 2.3.2 Control Unit The main purpose of the control unit is to read and decode instructions from the program memory.