Arithmetic Building Blocks

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Digital Integrated Circuits Arithmetic © Prentice Hall 1995 Administrivia

Midterm2: To be graded today » Some discussion today Remember: project phase 2! No lab this week.

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 Last Lecture

Sequential Design » Multivibrartors Arithmetic » Adder design – basic concepts

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 Today’s Lecture

Alternative adder structures Multipliers

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 Minimize Critical Path by Reducing Inverting Stages

Even Cell Odd Cell

A1 B1 A3 B3 A0 B0 A2 B2

Ci,0 Co,0 Co,1 Co,2 Co,3 FA’ FA’ FA’ FA’

S0 S2 S1 S3

Exploit Inversion Property

Note: need 2 different types of cells

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 The better structure: the Mirror Adder

VDD

VDD VDD A

A A B B B Ci B Kill "0"-Propagate A Ci Co Ci S

A Ci "1"-Propagate Generate

A B B AB Ci A

24 transistors

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 The Mirror Adder

• The NMOS and PMOS chains are completely symmetrical. This guarantees identical rising and falling transitions if the NMOS and PMOS devices are properly sized. A maximum of two series transistors can be observed in the carry- generation circuitry. • When laying out the cell, the most critical issue is the minimization of the

capacitance at node Co. The reduction of the diffusion capacitances is particularly important.

• The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell .

• The transistors connected to Ci are placed closest to the output. • Onlythetransistorsinthecarrystagehavetobeoptimizedforoptimalspeed.All transistors in the sum stage can be minimal size.

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 Quasi-Clocked Adder

VDD VDD P B B

B P P S A P A Ci Ci Co VDD P B P VDD A P P

Signal Setup Carry Generation Sum Generation

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 NMOS-Only Pass Transistor Logic

BBA C C A A

A B A B

C A C A

Sum Sum Cout Cout Transistor count (CPL) : 28

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 Manchester Carry Chain

VDD

P0 P1 P2 P3 P4

Ci,0 G0 G1 G2 G3 G4

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 Sizing Manchester Carry Chain

Discharge Transistor R R R R R R 121 2 33 44 55 66 Out

MC M0 M1 M2 M3 M4 C1 C2 C3 C4 C5 C6

N i t = 0.69∑ C ∑ R p ij i1= j1= 25 400

20 300

15 200 Speed Area 10 100

5 0 1 1.5 2.0 2.5 3.0 1 1.5 2.0 2.5 3.0 k k Speed (normalized by 0.69RC) Area (in minimum size devices)

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 Carry-Bypass Adder

P0 G1 P0 G1 P2 G2 P3 G3

Ci,0 Co,0 Co,1 Co,2 Co,3 FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3 BP=PoP1P2P3

Ci,0 Co,0 Co,1 Co,2 FA FA FA FA Co,3 Multiplexer

Idea: If (P0 and P1 and P2 and P3 = 1) then Co3 =C0, else “kill” or “generate”.

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 Manchester-Carry Implementation

P0 P1 P2 P3 BP Co,3 Ci,0 G0 G1 G2 G3

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 Carry-Bypass Adder (cont.)

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

Setup Setup Setup Setup

Carry Carry Carry Carry Ci,0 Propagation Propagation Propagation Propagation

Sum Sum Sum Sum

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 Carry Ripple versus Carry Bypass

ripple adder

bypass adder

4..8 N

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 Carry-Select Adder

Setup

P,G

"0" "0" Carry Propagation

"1" "1" Carry Propagation

C o,k-1 Multiplexer Co,k+3

Carry Vector Sum Generation

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 Carry Select Adder: Critical Path

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

Setup Setup Setup Setup

"0" Carry "0" Carry "0" Carry "0" Carry "0" "0" "0" "0"

"1" Carry "1" Carry "1" Carry "1" Carry "1" "1" "1" "1"

Multiplexer Multiplexer Multiplexer Multiplexer Ci,0 Co,3 Co,7 Co,11 Co,15

Sum Generation Sum Generation Sum Generation Sum Generation

S0-3 S4-7 S8-11 S12-15

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 Linear Carry Select

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

Setup Setup Setup Setup

(1)

"0"Carry "0" Carry "0" Carry "0" Carry "0" "0" "0" "0" (1)

"1" Carry "1" Carry "1" Carry "1" Carry "1" "1" "1" "1" (5) (5) (5) (5) (5) (6) (7) (8) Multiplexer Multiplexer Multiplexer Multiplexer Ci,0 (9)

Sum Generation Sum Generation Sum Generation Sum Generation

S0-3 S4-7 S8-11 S12-15 (10)

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 Square Root Carry Select

Bit0-1 Bit2-4 Bit5-8 Bit 9-13 Bit 14-19

Setup Setup Setup Setup (1)

"0" Carry "0" Carry "0" Carry "0" Carry "0" "0" "0" "0" (1)

"1" Carry "1" Carry "1" Carry "1" Carry "1" "1" "1" "1" (3)(3) (4) (5) (6) (7) (4) (5) (6) (7) Multiplexer Multiplexer Multiplexer Multiplexer Mux Ci, 0 (8)

Sum Generation Sum Generation Sum Generation Sum Generation Sum

S (9) S0-1 S2-4 S5-8 S9-13 14-19

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 Adder Delays - Comparison

50.0

ripple adder 40.0

30.0

tp linear select 20.0

10.0 square root select

0.0 0.0 20.0 40.0 60.0 N

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 LookAhead - Basic Idea

A0,B 0 A1,B 1 AN-1,BN-1 ...

Ci,0 P0 Ci,1 P1 Ci,N-1 PN-1

...

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 Look-Ahead: Topology

VDD

Ci,0

Co,3

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 Logarithmic Look-Ahead Adder

A0 F

A1 A2 A3 A4 A5 A6 A7 t ∼ N A0 p A1

A2 A3 F A4 A5 A ∼ 6 tp log2(N) A7

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 Brent-Kung Adder

Co,0 (G0,P0) Co,2 Co,4 Co,1 (G1,P1)

Co,3 (G2,P2) Co,5 (G3,P3)

(G4,P4) Co,6 (G5,P5)

(G6,P6) Co,7

(G7,P7)

∼ tadd log2(N)

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 The Binary Multiplication

MN1+ – ·· k ==X × Y ∑ Zk2 k0= M1– N1– i j = X 2 Y 2 ∑ i ∑ j i0= j0= M1– N1– ij+ = ∑ ∑ X Y 2 i j i0= j0= with

M1– i = ∑ Xi2 i0= N1– j YY= ∑ j2 j0= Digital Integrated Circuits Arithmetic © Prentice Hall 1995 The Binary Multiplication

101010

× 1011

AND operation 101010

101010 Partial Products

000000

+ 101010

111001110

Digital Integrated Circuits Arithmetic © Prentice Hall 1995 The Array Multiplier

Z0 X3 X2 X1 X0 Y1

HA FA FA HA

Z1 X3 X2 X1 X0 Y2

FA FA FA HA

Z X3 X2 X1 X0 Y3 2

FA FA FA HA

Z7 Z6 Z5 Z4 Z3 Digital Integrated Circuits Arithmetic © Prentice Hall 1995 The MxN Array Multiplier —CriticalPath

HA FA FA HA

FA FA FA HA Critical Path 1 Critical Path 2 Critical Path 1 & 2

FAFA FA HA

HA HA HA HA

HA FA FA FA

HAFA FA FA

HAFA FA HA

Vector Merging Adder

P V V DD DD A Ci

A P S A P

Ci A B B P VDD VDD P A

P Co Ci Ci C A i

Identical Delays for Carry and Sum

X3 X2 X1 X0

Y0 Y HA Multiplier Cell 1 C S C S C S C S Z0 FA Multiplier Cell

Y2 C S C S C S C S Z1 Vector Merging Cell

Y 3 C S C S C S C S X and Y signals are broadcasted Z2 through the complete array. ()

C C C C S S S S

y0 y1 y2

y y y y y y C 0 1 2 3 4 5 FA i-1

y3 FA FA C C Ci i i-1 Ci-1 FA Ci Ci-1

y4 FA Ci C i-1 Ci Ci-1 FA

FA Ci FA

• Optimization Goals Different Vs Binary Adder

• Once Again: Identify Critical Path

• Other possible techniques - Logarithmic versus Linear (Wallace Tree Mult) - Data encoding (Booth) - Pipelining FIRST GLIMPSE AT SYSTEM LEVEL OPTIMIZATION

Right nop Left

Ai Bi

Ai-1 Bi-1

Bit-Slice i

...

A3 B3

Sh1 A2 B2

Sh2 :DataWire A1 :ControlWire B1

Sh3

A 1

A 0

Sh0 Sh1 Sh2 Sh3 Buffer

Widthbarrel ~2pm M

Sh1 Sh1 Sh2 Sh2 Sh4 Sh4

A3 B3

B A2 2

A1 B1

A 0 B0

A 3 Out3

A 2 Out2

A 1 Out1

A 0 Out0

80.0 static mirror look-ahead manchester select 60.0 bypass 0.4 ) 2 static 40.0 select (mm

(nsec) bypass p t Area 0.2 mirror look-ahead 20.0 manchester

0.0010200.0 N 01020 N