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Let’s build a computer! Designing a CPU CPU: “central processing unit” computer: CPU + display + optical disk + metal case + power supply + ... the difference between your computer Last lecture: circuit that implements an adder and a TV set This lecture: circuit that implements a CPU Introduction to Computer Science • Robert Sedgewick and Kevin Wayne • Copyright © 2008 • http://www.cs.Princeton.EDU/IntroCS 2 TOY Lite Primary Components of Toy-Lite CPU TOY machine. • 256 16-bit words of memory. opcode Rs Rd1 Rd2 Arithmetic and Logic Unit (ALU) • 16 16-bit registers. 1 8-bit program counter. 4 bits to specify • opcode Rs addr one of 16 registers 2 instruction types • Memory 16 instructions. • 8 bits to specify one of 256 memory words TOY-Lite machine. Toy-Lite Registers • 16 10-bit words of memory. opcode Rs Rd1 Rd2 4 10-bit registers. • 2 bits to specify • 1 4-bit program counter. opcode Rs addr one of 4 registers • 2 instruction types Processor Registers: Program Counter and Instruction Register 16 instructions. 4 bits to specify • one of 16 memory words “Control” Goal: CPU circuit for TOY-Lite (same design extends to TOY, your computer) 3 4 Review of Combinational Circuits Useful Combinational Circuits Controlled switch. Adder Gates. Incrementer (easy, add 0001) Sum-of products implementation of Boolean functions Bitwise AND, XOR (easy) Decoder Adder Shifter (clever, but we’ll skip details) Multiplexer 5 6 Decoder Decoder application: ALU! Decoder. [n-bit] TOY arithmetic • n address inputs, 2n data outputs. 1: add input buses Addressed output bit is 1; others are 0. 2: subtract • TOY opcode bits • Implements n Boolean functions 3: and 4: xor sub 5: shift left 6: shift right add x0 x1 x2 z0 z1 z2 z3 z4 z5 z6 z7 and 0 0 0 1 0 0 0 0 0 0 0 xor 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 Details: shift 0 1 1 0 0 0 1 0 0 0 0 • All circuits compute their result. Decoder lines AND all results. 1 0 0 0 0 0 0 1 0 0 0 • • “one-hot” OR collects answer. right 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 output bus 3-bit Decoder 7 8 Primary Components of Toy-Lite CPU Nuts and Bolts: Buses and Multiplexers Bus. Parallel wires connecting major component. ! Arithmetic and Logic Unit (ALU) • Ex. Carry register bits to ALU. • Ex. Carry register bits to memory Memory Multiplexer. Combinational circuit that selects among input buses. • Exactly one select line i is activated. • Copies bits from input bus i to output bus. Toy-Lite Registers Processor Registers: Program Counter and Instruction Register “Control” CPU is a circuit: everything is “connected” but wires that can be “on” can be selected by other wires. 9 10 Nuts and Bolts: Buses and Multiplexers A New Ingredient: Circuits With Memory Bus. Parallel wires connecting major component. Combinational circuits. • Ex. Carry register bits to ALU. • Output determined solely by inputs. • Ex. Carry register bits to memory • Ex: majority, adder, decoder, MUX, ALU. Multiplexer (MUX). Combinational circuit that selects among input buses. Sequential circuits. • Exactly one select line i is activated. • Output determined by inputs and current “state”. • Copies bits from input bus i to output bus. • Ex: memory, program counter, CPU. Ex. Simplest feedback loop. • Two controlled switches A and B, both connected to power, each blocked by the other. B • State determined by whichever switches first. Stable. • A Aside. Feedback with an odd number of switches is a buzzer (not stable). Doorbell: buzzer made with relays. CPU is a circuit: everything is “connected” but wires that can be “on” can be selected by other wires. 11 12 SR Flip-Flop Memory Overview x y x y SR Flip-flop. OR NOR Computers and TOY have several memory components. • Two cross-coupled NOR gates x + y ( x + y )! • Program counter and other processor registers. OR gate NOR gate A way to control the feedback loop. TOY registers (4 10-bit words in Toy-Lite). • write 0 write 1 • • Abstraction that "remembers" one bit. • Main memory (16 10-bit words in Toy-Lite). write 0 write 1 • Basic building block for memory and registers. memory bit Implementation. memory bit Use one flip-flop for each bit of memory. • read • Use buses and multiplexers to group bits into words. Access mechanism: when are contents available? • Processor registers: enable write. • Main memory: select and enable write. • TOY register: dual select and enable write need to be able to read two registers at once Caveat. Timing, switching delay. 13 14 Processor register Bit Memory Bit Interface Processor register bit. Extend a flip-flop to allow easy access to values. Memory and TOY register bits: Add selection mechanism. [ TOY PC, IR ] [ TOY main memory ] [ TOY registers ] 15 16 Memory Bit: Switch Level Implementation Processor Register Memory and TOY register bits: Add selection mechanism. Processor register. don't confuse with TOY register • Stores k bits. • Register contents always available on output bus. • If enable write is asserted, k input bits get copied into register. Ex 1. TOY-Lite program counter (PC) holds 4-bit address. Ex 2. TOY-Lite instruction register (IR) holds 10-bit current instruction. (4-bit) [ TOY PC, IR ] [ TOY main memory ] [ TOY registers ] 17 18 Processor Register Processor Register Processor register. don't confuse with TOY register Processor register. don't confuse with TOY register • Stores k bits. • Stores k bits. • Register contents always available on output bus. • Register contents always available on output bus. • If enable write is asserted, k input bits get copied into register. • If enable write is asserted, k input bits get copied into register. Ex 1. TOY program counter (PC) holds 8-bit address. Ex 1. TOY program counter (PC) holds 8-bit address. Ex 2. TOY instruction register (IR) holds 16-bit current instruction. Ex 2. TOY instruction register (IR) holds 16-bit current instruction. (4-bit) 19 20 Memory Bank Memory: Interface Memory bank. Bank of n registers; each stores k bits. (four 6-bit words) • 6-bit • Read and write information to one of n registers. Address inputs specify which one. • log2n address bits needed • Addressed bits always appear on output. • If write enabled, k input bits are copied into addressed register. Ex 0 (for lecture). 4-by-6 (four 6-bit words) Ex 1. Main memory bank. • TOY: 256-by-16 • TOY-Lite: 16-by-10 Ex 2. Registers. 2-bit • TOY: 16-by-16 6-bit • TOY Lite: 4-by-10 Two output buses. • 21 22 Memory: Component Level Implementation Memory: Switch Level Implementation Decoder plus memory selection: connect only to addressed word. (four 6-bit words) 23 24 TOY-Lite Memory Toy-Lite Registers 16 10-bit words 4 10-bit words • input connected to registers for “store” • Dual-ported to support connecting two different registers to ALU • output connected to registers for “load” • Input MUX to support input connection to ALU, memory, IR, PC addr connect to processor Instruction Register (IR) to ALU (in) to ALU (out) • MUX select to registers (in) to registers (out) to IR to memory, IR to PC 25 26 Primary Components of Toy-Lite CPU How To Design a Digital Device How to design a digital device. • Design interface: input buses, output buses, control wires. ! ALU • Determine components. • Determine datapath requirements: "flow" of bits. • Establish control sequence. ! Memory Warmup. Design a program counter (3 devices, 3 control wires). ! Registers Goal. Design TOY-Lite computer (10 devices, 27 control wires). ! Processor Registers: Program Counter and Instruction Register Not quite done. Need to be able to increment. “Control” 27 28 Program Counter: Interface Program Counter: Components Counter. Holds value that represents a binary number. Components. • Load: set value from input bus. • Register. • Increment: add one to value. • Incrementer. • Enable Write: make value available on output bus. • Multiplexer (to provide connections for both load and increment). Ex. TOY-Lite program counter (4-bit). 29 30 Program Counter: Datapath and Control Program Counter: Datapath and Control Datapath. Datapath. • Layout and interconnection of components. • Layout and interconnection of components. • Connect input and output buses. • Connect input and output buses. Control. Choreographs the "flow" of information on the datapath. Control. Choreographs the "flow" of information on the datapath. 31 32 Program Counter: Datapath and Control Program Counter: Datapath and Control Datapath. • Layout and interconnection of components. • Connect input and output buses. Control. Choreographs the "flow" of information on the datapath. 1. load: 3. increment: copy input to register output plus 1 available in MUX copy to register 2. enable write: 4. enable write: register contents available on output register contents available on output 33 34 Primary Components of Toy-Lite CPU How To Design a Digital Device How to design a digital device. • Design interface: input buses, output buses, control wires. ! ALU • Determine components. • Determine datapath requirements: "flow" of bits. • Establish control sequence. ! Memory Warmup. Design a program counter (3 devices, 3 control wires). ! Toy-Lite Registers Next. Design TOY-Lite computer (10 devices, 27 control wires). ! Processor Registers: Program Counter and Instruction Register “Control” 35 36 TOY-Lite: Interface TOY-Lite: Components CPU is a circuit. Interface: switches and lights. • set memory contents • set PC value • press RUN • [details of connection to circuit omitted] 37 38 TOY-Lite: Layout TOY-Lite Datapath Requirements: Fetch Basic machine operation is a cycle. • Fetch Fetch • Execute Fetch. • Memory[PC] to IR Execute • Increment PC Execute.
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  • Automated Synthesis of Symbolic Instruction Encodings from I/O Samples

    Automated Synthesis of Symbolic Instruction Encodings from I/O Samples

    Automated Synthesis of Symbolic Instruction Encodings from I/O Samples Patrice Godefroid Ankur Taly Microsoft Research Stanford University PLDI’2012 Page 1 June 2012 Need for Symbolic Instruction Encodings Symbolic Execution is a key l 1 : m o v eax, i n p 1 component of precise binary m o v c l , i n p 2 program analysis tools s h l eax, c l j n z l2 j m p l3 - SAGE, BitBlaze, BAP, etc. l 2 : d i v ebx, eax // Is this safe ? - Static analysis tools / / I s e a x ! = 0 ? l 3 : … PLDI’2012 Page 2 June 2012 Problem: Symbolic Instruction Encoding Bit Vector[X] Instruction Bit Vector[Y] Inp 1 ? Op1 Inpn Opm Problem: Given a processor and an instruction name, symbolically describe the input-output function for the instruction • Express the encoding as bit-vector constraints (ex: SMT-Lib format) PLDI’2012 Page 3 June 2012 So far, only manual solutions… • From the instruction architecture manual (X86, ARM, …) implemented by the processor Limitations: • Tedious, expensive - X86 has more than 300 unique instructions, each with ~10 OPCodes, 2000 pages • Error-prone - Written in English, many corner cases • Imprecise - Spec is often under-specified • Partial - Not all instructions are covered X86 spec for SHLD • Can we trust the spec ? PLDI’2012 Page 4 June 2012 Here: Automated Synthesis Approach Searches for a function f that respects truth table Partial Truth- table S Sample inputs Synthesis Function (C with in-lined engine f assembly) Goals: • As automated as possible so that we can boot-strap a symbolic execution engine on an arbitrary instruction