Random Access Memory
data_in 0 address 1 2 data_out How Memory Works enable 3 read/write . . .
Logically, a random access memory contains an array of numbered storage locations, called words » when read/write is high, data_out is equal to the value stored in word specified by address inputs Static RAM operation and timing » when read/write is low, the value on data_in replaces the Implementation of SRAM array value in word specified by address inputs Construction of larger RAMs from smaller ones » separate enable signal also usually provided Dynamic RAM implementation Simplest RAMs are asynchronous - no clock input » circuits using RAMs must make sure that RAM timing requirements are satisfied to ensure correct operation
» synchronous SRAMs handle timing issues internally ‹#›
Static RAM Array (4x4) Timing of Async RAM Operations data_in Read cycle Read cycle » access time: time from address address valid r/w’ . . . column driver “last” address change until enable access time . . . output data is valid r/w . . . . data valid d_out Write cycle
» t1 is min time from address Write cycle stable and enable asserted address address valid address until r/w is lowered enable t1 t2 t3 » t2 is min time that input
row decoder r/w data must remain stable before r/w can be raised data_in data valid
» t3 is min time that address Circuits using RAM must storage stays valid after r/w is sense location raised ensure timing conditions amplifier data_out » cycle time is t +t +t are met ‹#› 1 2 3 ‹#›
Review Questions Question
1. Suppose we had a static RAM, similar to the one on slide 3, but with 8 words of 8 1. Suppose that the three timing parameters for a memory write are t1 = 2 ns, bits each. How many storage locations does this memory have? How many address t2 = 12 ns and t3 = 3 ns respectively. What is the minimum amount of time bits does it require? How many sense amplifiers? How many column drivers? needed to write 100 words to memory? 2. Suppose a memory has an access time of 15 ns. What is the minimum amount of time required to read 100 words from such a memory? Write cycle address address valid enable t1 t2 t3 r/w
data_in data valid
A: 200 ns B: 300 ns C: 1200 ns D: 1400 ns E: 1700 ns
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1 Functional Simulation Static RAM Array (8x2) column data_in . . decoder/demux read write read address . . . . . cycles cycles cycles . . . r/w’ ......
. row decoder
column decoder/mux
details of write data_out ‹#› ‹#›
Building Larger RAMs The SRAM Storage Cell
Systems often require larger RAMs than can be Computers and other digital systems generally use constructed using a single SRAM component large amounts of memory Specialized memory cells have been developed to pack The use of an external decoder and the enable more memory in given amount of space input allows larger RAMs to be constructed Typical static RAM uses 6 transistor cell using pair of SRAM SRAM SRAM SRAM inverters and pair of pass transistors 16Kx16 16Kx16 16Kx16 16Kx16 64Kx16 RAM Word line asserted to data_in ’ ’ ’ ’ read or write the cell column R/W R/W EN ADDR DATA EN ADDR DATA R/W R/W EN ADDR DATA ADDR DATA EN drivers word read/write’ Complementary bit lines SRAM cell 24 used for input and output line address Column drivers enabled when writing data » powerful transistors Alternative design uses 64Kx4 RAM chips allows them to force cell sense amplifier data_out » no external decoder needed in this case ‹#› to desired state ‹#›
Dynamic RAMs Dynamic RAM Layout
Dynamic RAMs use simpler memory cell to enable more bits to be stored in a single chip (4-8x) bit line » each storage cell consists of a pass transistor and a capacitor select storage word line » reading contents, destroys value capacitor • need to write back after reading data » stored charge leaks from capacitor after 10-100 ms • requires periodic refresh of memory contents DRAM cells are organized in 2D arrays, much like those for SRAM » single bit line rather than complementary pair sense amps » requires sensitive sense amplifiers to detect stored charge » takes more time (10x) to read values than with SRAM ‹#› ‹#›
2 Addressing in Dynamic RAMs Exercises Large memory chips require lots of address pins Many DRAM chips reduce number of address pins 1. The diagram at right shows a memory array by dividing address into two parts containing 32 words of » row address determines which row in 2D array is selected 2 bits each. Label each » column address selects one or more bits in the row memory cell in the third row from the top, Column address can be provided after row address identifying the bit stored in that word without slowing down memory access (for example, bit 1 of » so, same address pins can be used to supply both row and word 23). Label each column addresses memory cell in the fifth column similarly. Circle » Row Address Strobe (RAS), Column Address Strobe (CAS) the memory cells that used to load row and column addresses into on-chip contain word 17. registers Refresh circuitry periodically reads each row in memory array and writes it back » refresh circuits now commonly built into memory chips ‹#› ‹#›
2. Consider a 512 KByte SRAM. 4. The block RAMS on the FPGA used on Assuming that the device reads and the S3 board have 16,384 bits and can Solutions writes data in the form of 16 bit be configured in a variety of ways. The words, how many words can the configurations include 512x32, device store? How many address bits 1024x16, 2048x8, 4096x4, 8192x2, 1. The labels in the diagram are needed to address these words? 16384x1. Draw a diagram showing how at right identify each word Assuming that the central memory you can implement a 6144x12 bit and the bit in the word. array has the same number of rows as memory using 5 block RAMs. You may The cells containing word it has columns, how many rows are use more than one distinct 17 are circled. there? How many of the address bits configuration, but make sure that you 2. The memory will store are used by the row decoder? How label each block RAM you use and show 256K words, or more many by the column decoder? how the address and data lines of the precisely 218=262,144, different block RAMs are connected to 3. Explain why a DRAM must be so 18 address bits are implement the overall memory. Assume refreshed periodically, but an SRAM needed. The memory that each block RAM has an enable need not be. How does the sense stores a total of 4 Mbits input, a read/write input, a data input amplifier in a memory make memory or 222 bits, so it will have and a data output. You may assume reads faster? 211=2048 rows and 2048 that the data outputs have internal tri- columns. This means that state buffers that are turned off when 11 of the 18 address bits the enable input is low. If you need to will be used by the row decoder use any external decoders, make sure to select one of the 2048 rows and that the that you show how they connect to the remaining 7 bits will be used by the column decoder. address inputs and the address lines of The memory stores 16 bit words, so each row the individual block RAMs. contains 128 words (12816=2048). ‹#› ‹#›
3. In an SRAM, there is a pair of inverters that are supplied with power, allowing them to maintain charge within a storage cell and to drive current onto the output lines leading to the sense amplifier, when a memory read is taking place. In a DRAM, there are no power connections. Charge is stored on the capacitance within the cell and this stored charge eventually “leaks” away. When a memory cell is being read out, the voltage of the output lines changes slowly, since the output lines constitute a large capacitance. The sense amplifier magnifies the initial small voltage difference, yielding a valid logic 0 or 1 at the sense amp output, long before the internal wires are fully charged. 4. The solution appears at right.
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