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Biasing LDMOS FET Devices in RF Power Amplifiers

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Biasing LDMOS FET Devices in RF Power Amplifiers Biasing LDMOS FET devices in RF power amplifi ers by Terry Millward, Maxim Integrated Products, USA LDMOS technology for fi eld-effect transistors (FETs) has emerged as the leading technology for high-power RF applications, and especially for the power amplifi ers found in cellular-system base stations. Breakdown voltages of 65 V and higher Rds(on) goes down. These effects are usually New devices allow LDMOS FETs to retain ruggedness shown in the data sheet as a plot in which the A number of bias-control devices for LDMOS and reliability while operating with 28 V gate bias values are normalised to 1 V at 25°C, FETs in RF power amplifiers have been power supplies. This article outlines the and different curves show the bias change developed. They provide temperature characteristics of such FET devices, and needed to maintain given drain currents over describes various methods of biasing to obtain temperature (Fig. 3). LDMOS FETs have a compensation for class A and class AB best performance. positive coeffi cient at low drain currents, but at power-amplifier configurations, and also more useful operating currents the coeffi cient provide automatic power control, by setting LDMOS characteristics the V level to optimise the drain current vs. becomes negative, giving protection against gs The laterally diffused metal-oxide- thermal runaway. The FET’s performance in a variations in RF power and drain voltage. semiconductor (LDMOS) FET structure power amplifi er is a tradeoff between linearity, New devices that provide continuous control (Fig. 1) provides a 3-terminal device whose effi ciency, and gain, leading to an optimum include the following: n+ source and drain regions are formed in drain-current setting that must be maintained • High-side current-sense amplifier for a p-type semiconductor substrate. A laterally over temperature, supply-voltage variation, sensing drain current diffused, low-resistance p+ “sinker” connects bias-point shifts, and aging. the source region to the p+ substrate and • ADC for digitising drain current (Idq) during source terminal. That confi guration allows Traditional bias methods calibration and over temperature the substrate to be soldered directly to RF Fig. 4 shows two analogue methods for • DAC for setting the gate bias voltage ground, thereby minimising the effect of controlling gate bias. The simpler circuit • Non-volatile look-up table (temperature wiring parasitics. Fig. 4(a), using a divider and diode (whose vs. gate voltage) The gate region is isolated from the conducting forward voltage changes -2 mV/°C) to reduce the variation of quiescent current over • Integrated alarm functions with gate- channel by a thin layer of SiO2. Applying a positive voltage to the gate with respect to the temperature, is handicapped by the diffi culty voltage clamping. source allows current to fl ow between drain in matching the compensation to the LDMOS The continuous-control approach offers and source by forming an inversion layer (or FET and diode. advantages: it reduces manufacturing cost channel) between the two n-type regions. Circuit Fig. 4(b) introduces a trimmed by allowing automatic set up of the PA to LDMOS FETs operate in “enhancement mode,” temperature sensor to eliminate the diode improve set point accuracy, reduces the meaning the drain-source current cannot fl ow variation. The op amp provides gain that margins required in device selection, allows until an applied positive gate voltage enhances matches the slope of temperature to the nonlinear compensation, and allows dynamic a channel across the p-well. LDMOS device, and a manual potentiometer biasing when the PA output power is reduced When the FET is used as an amplifi er, the or EEPOT sets the starting point or offset. during quiet periods. The overall scheme is channel current is modulated by an AC signal Circuit Fig. 4(b) is better than circuit shown in Fig. 5. mixed with the positive gate-bias voltage. Fig. 4(a), but both assume that a simple linear Fig. 2 shows the typical relationships between compensation of gate voltage vs. temperature The front-end device is a dual LDMOS high- drain current and gate voltage at various is suffi cient for maintaining a constant drain side sense amplifi er and gate-driver amplifi er. temperatures. In contrast, note that RF devices voltage. That is not necessarily so, especially The high-side sense amplifi er monitors the such as GaAs FETs and MESFETs require a for power amplifi er designs. More accurate LDMOS FET’s drain current over the range negative gate-bias voltage with respect to compensation requires a nonlinear adjustment. 20 mA to 5A, using an external sense resistor the source. Moreover, such compensation schemes do scaled for different current levels. The chip not allow for changes in drain voltage to provides a gain setting of 2 or 10, with a Bias issues improve effi ciency. The best approach for typical input-referred offset voltage of 0 V or As the temperature of an LDMOS FET increases, compensation combines analogue and digital 3 mV. (The 3 mV option is for applications with mixed-signal techniques. that require offset nulling.) its gate threshold shifts, its gm drops, and its 26 Elektron November 2005 Word address Confi guration Confi guration Confi guration Confi guration 1 (example) 2 (example) 3 (example) 4 (example) 0x00 Dedicated user message 0x10 Confi guration data 0x40 APC LUT1 32 x Unifi ed Unifi ed APC 16-bit Temperature LUT 64 x 0x60 APC LUT2 32 x LUT 64 x 16-bit 16-bit Fig. 1: LDMOS structure. 16-bit Unifi ed APC 0x80 Temperature Temperature LUT 192 x 0xA0 LUT1 64 x LUT1 64 x 16-bit The sense-amplifier output is referred to 16-bit 16-bit Unifi ed APC ground, with a maximum output voltage of LUT 128 x 0xC0 Temperature Temperature 5 V. The drive amplifi er is current limited and 16-bit provided with a logic-controlled fast clamp 0xE0 LUT2 64 x LUT2 64 x 16-bit 16-bit to zero. The clamp is independent of the 0xFF serial interface, in case the system controller Table 1: Memory confi gurations. detects a fault. That arrangement allows “fast” over temperature to determine (as a calibration protection of the LDMOS FET. The amplifi er fast clamp to zero, independent of the serial curve) a set of gate-voltage values (from the is confi gured for a gain of either 2 or 4, to interface for LDMOS protection. The ADC data, DAC setting, and control registers are all DAC) that maintains a constant drain current. accommodate various LDMOS gate-voltage accessed by the host processor via a serial SPI One assumes that the curve is fairly consistent requirements. Output transients are limited or I2C interface (according to the connection from part to part. A group of parts at a given to ±100 mV during power up and power at the interface select pin). drain current may exhibit shifts in offset, but down. The most common application is a Class AB no dramatic changes in slope. The values are With application of power the gate-driver LDMOS amplifi er with open-loop control. stored in a non-volatile lookup table (LUT) amplifi er starts in a shutdown state, so the The processor, using a customer-defined in the users system. Additional LUTs can outputs from the sense and drive amplifi ers lookup table and algorithm, sets the DACs to make adjustments for other purposes, such as are tied to ground through resistor networks. implement a digital control loop for controlling reducing drain voltage with output power. The devices draw only about 100 µA of supply the LDMOS gate bias voltage. This approach Calibration current in that state. Toggling the external is implemented in three stages: /SHDN\ input from low to high turns the part During production, the PA’s quiescent Characterisation ON, which allows a controlled start-up and drain current is measured at a calibration protects the LDMOS devices. A sample of LDMOS parts are characterised temperature (usually room temp), and the The dual RF LDMOS bias controller is a dual IC containing comprehensive circuitry for setting and controlling the bias for a dual RF LDMOS power device. It contains the current sense and gate-drive functions of the gate- driver amplifi er (discussed above). Gain for the current-sense function is augmented by a programmable-gain amplifi er (PGA) featuring auto calibration that is transparent to the user, allowing accuracy to be guaranteed over time and temperature. Two external, current driven, diode-connected transistors can be used to monitor the temperature of the power devices, and an internal diode monitors the local die temperature. These temperatures, along with the drain currents and two spare inputs (which can be used for measuring drain voltage, RF power, or monitoring any other PA parameters) are multiplexed into the 12-bit ADC. The available options let you read an individual channel or scan all channels under internal or external control, and store the results in an internal FIFO. On the control side, an 8-bit coarse DAC and 10-bit fi ne DAC generate a positive bias voltage for the gate drivers. The gate-voltage buffer is current limited, and (as for the gate- driver amplifi er) includes a logic-controlled Elektron November 2005 27 correction for gain by multiplying every value in the look-up table by the slope coeffi cient. Operation Periodically, the temperature of the LDMOS device is measured and compared with the previous reading. If it has changed, the host processor reads the LUT, obtains characterisation data, and updates the DAC to correct the drain current. Using a host processor to correct for changing temperature and other factors allows scope for more sophisticated corrections.
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