A Thesis

entitled

NiO x Based Resistive Random Access Memories

by

Madhumita Chowdhury

Submitted to the Graduate Faculty as partial fulfillment of the requirements for the

Master of Science Degree in Electrical Engineering

______Dr. Rashmi Jha, Committee Chair

______Dr. Vijay Devabhaktuni, Committee Member

______Dr. Mansoor Alam, Committee Member

______Dr. Christopher Melkonian, Committee Member

______Dr. Patricia R. Komuniecki, Dean College of Graduate Studies

The University of Toledo

May 2012

Copyright 2012, Madhumita Chowdhury

This document is copyrighted material. Under copyright law, no parts of this document may be reproduced without the expressed permission of the author.

An Abstract of NiO x Based Resistive Random Access Memories

by

Madhumita Chowdhury

Submitted to the Graduate Faculty as partial fulfillment of the requirements for the Master of Science Degree in Electrical Engineering

The University of Toledo May 2012

In present flash memory devices, data is stored by injecting hot electrons or charge through tunnel oxide. This will result into degradation of oxide and the problem would amplify with the scaling of the dielectric. According to International Technology

Roadmap for Semiconductors (ITRS) the continuous scaling of the oxide thickness beyond 16 nm node technology may result into unwanted data loss and high leakage current. Hence, new ways of data storage are being explored, resistive random access memory (RRAM) being one of them. A RRAM device is a two-terminal metal insulator metal (MIM) structure having the potential to scale up to 8 nm generation technology. It is non-volatile and can store data in form of both low resistance state (LRS) and high resistance state (HRS). The other incentives are its low operating voltage, high endurance and integration in crossbar arrays. NiO x promises to be a strong candidate for future non- volatile memory devices and it still needs a better understanding of the physical mechanism behind the ability to switch between two resistive states. This thesis is focused to study the impact of different metal electrode on NiOx based RRAM devices with high percentage (20%) of O 2.RRAM device performance with Al and Ru electrodes was studied. Switching characteristics indicated that Al based electrodes lead to the

iii device failure due to formation Al 2O3 on NiO x. On the other hand, devices with Ru electrodes demonstrated switching with SET/RESET voltages of less than ±2 V.

Moreover, the conduction mechanism responsible for switching mechanism is also reported.

iv To my parents, sisters and best friend Raju.

Acknowledgements

This thesis would not have been possible without the help of several individuals and I would like to take this opportunity to thank them all for guiding me with their expertise and support.

First and foremost, my utmost gratitude goes out to Dr. Vijay Devabhaktuni and

Dr. Rashmi Jha for giving me the opportunity to work under their guidance. Their timely advice and encouragement was essential towards the completion of this thesis. I would like to thank Dr. Alam for being a part of my thesis committee member. I also want to thank Dr. Christopher Melkonian for giving me the opportunity to work at Midwest

Micro Devices (MMD) and to earn an experience which was priceless.

Next, I would like to thank my colleagues, Branden Long, Laxman Anishetty,

Saptarshi Mondal and Yibo Li in the UT Nanotechnology Lab. Their contribution was essential towards speeding up the completion of my thesis. I would also like to thank all my friends for their constant help and moral support throughout this journey and making my study at The University of Toledo a truly memorable experience. I am indebted to my family for their immense love and support. Finally, I want to thank God for answering my prayers and for giving me the strength to face the many challenges over years .

vi Contents

Abstract iii

Acknowledgements vi

Contents vii

List of Table x

List of Figures xi

1 Introduction to Memory Technology 1

1.1 Overview of Nonvolatile Memories ...... 1

1.2 Flash Memory ...... 2

1.2.1 Working Principle of Flash Memory ...... 3

1.2.2 Write and Erase Operation ...... 4

1.2.3 Reliability Issues of Flash Memory ...... 5

1.2.3.1 Scalability Issue of the Oxide ...... 5

1.2.3.2 High Operational Voltage ...... 6

1.2.3.3 Endurance of Flash Memory Cell ...... 6

1.2.3.4 Access Time Limitation ...... 7

2 Research Motivation 11

2.1 Resistive Random Access Memory...... 11

3 Fabrication Process of RRAM 14 vii 3.1 Process Flow in Details ...... 15

4 Device Characterizations and Switching of Ni/NiO x/Al RRAMs 20

4.1 Overview ...... 21

4.2 Analysis of Ni/NiOx/Al RRAM ...... 22

5 Device Characterizations and Switching of Ru/NiOx/Ru/W RRAMs 30

5.1 Ru/NiOx/Ru Based RRAMs ...... 30

5.1.1 Motivation ...... 30

5.1.2 Fabrication Challenges ...... 31

5.2 Analysis of Ru/NiOx/Ru/W RRAMs ...... 32

6 Mechanism of Conduction in NiOx RRAMs 42

6.1 Background ...... 42

6.2 Conduction Mechanism in Ru/NiOx/Ru RRAMs ...... 43

7 Conclusions and Future Work 49

7.1 Conclusions ...... 49

7.2 Future Work ...... 50

References 51

A Statistics of Ni/NiO x/Al devices failure 60

B Repeatable Devices for Ru/NiO x/Ru Switching 62

C Charge Transport Mechanism in High-k Dielectric Based MOS Capacitors 64

C.1 Introduction ...... 64

C.2 Background ...... 65

C.3 Experimental ...... 67

C.4 Results and Discussions ...... 69

viii C.5 Conclusions ...... 77

D Fabrication of Graphene 79

E Simulation of GaSb Based MOSFET 83

ix List of Tables

1. 1 Comparison of performance parameters for fully scaled RRAM with flash...... 8

3. 1 List of samples and fabrication parameters...... 14

3. 2 Deposition parameters for BE...... 16

3. 3 Deposition parameters for TE...... 17

6. 1 Summary of Conduction Mechanism dominant at different resistive states...... 48

A. 1 Switching analysis for For 200 µm devices...... 60

A. 2 Switching analysis for 100 µm devices...... 60

A. 3 Switching analysis for 50 µm devices...... 61

E. 1 Current per unit length for Si, Ge and GaSb for two different models...... 86

x List of Figures

1- 1 Current Market for Memory Technology, DRAM and Flash dominates ...... 2

1- 2 Structure and I D-VG characteristic of Flash memory...... 3

1- 3 Physical mechanism of (a) write by hot carrier injection and (b) tunneling...... 4

1- 4 Trap-assisted tunneling shown by percolation model...... 6

1- 5 Latency in write and erase cycles after several iterations of tunneling through the oxide...... 7

2- 1 A typical RRAM showing formation of filament by movement of ions...... 12

2- 2 (a) Bistable switching with 3% O 2 and (b) Monostable switching with high (~20%)

O2...... 13

3- 1 Sputtering tool at University of Toledo clean room for thin film depositions...... 17

3- 2 Mask Aligner used for photolithography in University of Toledo clean room...... 18

4- 1 (a) Probe Station at UT Nano-laboratory for device characterization, (b) Stack of Al

(TE)/NiO x/ Ni (BE) RRAM...... 21

4- 2 Current density vs. voltage characteristics of virgin devices of 200 µm and 100 µm devices. The inset shows the forming current density vs. voltage characteristic. Both the device sizes, i.e. 200 µm and 100 µm need a high voltage of 20 V to form...... 23

4- 3 The capacitance per unit area (F/cm 2) versus voltage (V) curve shows a p-type C-V profile for a voltage range of -10 V to 10 V at 1 MHz for all the device sizes...... 24 xi 4- 4 Shows 1/C 2 (F -2) vs. voltage (V) plot in depletion...... 25

4- 5 shows doping density vs. voltage plot that was extracted from these 1/C 2-V plots using a dielectric constant of 10 for NiO x...... 26

4- 6 Shows the switching pattern of a 200 µm device after forming. A SET voltage -3 V and RESET voltage of 3 V was achieved...... 27

4- 7 A reduction in the capacitance density can be observed in failed device as compared to the virgin device...... 28

4- 8 Illustrates the switching mechanism of a Al/NiO x/Ni. Thermally generated electrons

2+ are trapped by the Vo . (b) Illustrates the failure mechanism of the Al/NiO x/Ni structure due to formation of Al 2O3 layer...... 29

5- 1 Stack of Ru (TE)/ NiO x/ Ru (BE) with W used as hard mask...... 31

5- 2 Initial I-V curves for Ru/NiO x/Ru of 200 µm x 200 µm area...... 33

5- 3 Repetitive switching cycles for Ru/NiO x/Ru of 200 µm x 200 µm and inset shows the forming of device...... 33

5- 4 Switching mechanism using filament based model of NiO x based RRAM for [(a) and

(b)] Ru/NiO x/Ru structure and (c) Pt/NiO x/Pt structure. Positive bias applied to TE of [(a) and (c)]...... 34

5- 5 For Ru/NiO x/Ru of 500 µm x 500 µm area (a) Initial I-V curves and (b) switching with 30 mA, 20 mA and 10 mA compliance level. The device with 10 mA compliance while electroforming showed repeatable switching ...... 36

5- 6 A stable Ron /R off ratio of Ru/NiO x/Ru stack...... 37

5- 7 Conducting filament model for Pt/ NiO x/Pt structure ...... 38

xii 5- 8 (a) HRS current density for 200 µm x 200 µm and 500 µm x 500 µm device for

Ru/NiO x/Ru...... 39

6- 1 Conduction Mechanism at LRS with ionic conduction fit...... 44

6- 2 Conduction Mechanism at LRS with ohmic conduction fit...... 45

6- 3 Conduction Mechanism at HRS with thermionic field emission conduction fit...... 47

6- 4 Voltage dependent conduction mechanism for F-P emission fitting at VRS...... 47

6- 6 VRS voltage dependent conduction mechanism for thermionic mechanism...... 48

C- 1 (a) I-V measurements for HfO 2/W, HfO 2/Ti, Al 2O3/ W, and Al 2O3/Ti at room temperature...... 69

2 1/2 1/2 C- 2 (a) Schottky emission curve fit for Al 2O3/Ti samples [–ln(J/(AT )) vs E (V/cm)

] for Al 2O3/Ti at high field at temperatures of 300 K, 350 K and 400 K...... 72

C- 3 (a) Curve fitting for F-P emission [–ln(J/E) (A/Vcm) Vs E 1/2 (V/cm) 1/2 ] and

2 tunnelling [ –ln(J/E ) Vs 1/E] for HfO 2/W at high field at temperatures of 300 K, 350 K and 400 K...... 73

2 1/2 1/2 C-4 Curve fitting for Schottky emission [ –ln(J/(AT )) Vs E (V/cm) ] for HfO 2/W at low field at temperatures of 300 K, 350 K and 400 K...... 75

D- 1 Steps for fabrication of graphene...... 80

D- 2 Temperature vs. Time characteristics for fabrication of graphene in MOCVD...... 81

D- 3 Image of Graphene on Ni...... 82

E- 1 Structure of p-MOS, Channel length= 100nm, Source/drain depth= 30 nm, tox=

10nm...... 84

E- 2 Drain Current (I d) vs. (V d) Drain Voltage for SHI Model for Si/HfO 2...... 84

E- 3 Drain Current (I d) vs. Drain Voltage (V d) for Watt Model for Si/HfO 2...... 85

xiii E- 4 Current (I d) vs. Drain Voltage (V d) for GaSb SHI model...... 85

xiv Chapter 1

Introduction to Memory Technology

Today’s semiconductor memory market can be broadly classified into two main groups: Volatile memories and Nonvolatile memories.

Volatile memories are divided in to Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). DRAM stores data in the presence or absence of charge in the capacitor. The charge stored in the capacitor decays with time and hence, the DRAM needs to be refreshed periodically. However they are dense and have low cost. On the other hand, the SRAM does not need to be refreshed and has higher speed but comes with a low density. Furthermore, the major disadvantage of

DRAM and SRAM is their inability to retain data when the power is turned off and this brings nonvolatile memories into the picture [1].

1.1 Overview of Nonvolatile Memories

The nonvolatile memories like Erasable Programmable Read Only Memory

(EPROM), Electrically Erasable PROM (EEPROM) or Flash have the capability to retain the data even without power supply. The data retention time is around 100 ms in DRAM

1 while it is 10 years for a flash memory .The Fig 1-1 indicates market share for different memory technologies (both volatile and non-volatile), “Flash memory” being one of the dominant players.

Figure 1- 1 Current Market for Memory Technology, DRAM and Flash dominates [2].

1.2 Flash Memory

Flash memory is a combination of both EPROM and EEPROM. Flash memory’s ability of erasing a large portion of memory at a given time is what leads to its name. In

EEPROM each byte is erased one at a time and hence it is different from flash. A flash memory cell constitutes of a transistor with a floating gate, analogous to an EPROM cell.

However, there are some differences in technology and geometry between flash memory cells and EPROMs. In particular, the thinner gate oxide between the silicon and the floating gate and also the source and drain diffusions for flash memory technology [3].

2 1.2.1 Working Principle of Flash Memory

When a conventional MOSFET’s gate is modified such that temporary storage of charge inside the gate is possible, the new structure becomes a nonvolatile memory. A typical structure of a Flash memory cell is shown in Fig. 1-2 where the top gate is called the “control gate” (CG) and the isolated gate between the oxides is called the “floating gate” (FG). This FG is sandwiched between CG and MOS channel [4] where the I D-VG

(Drain Current-Gate Voltage) characteristic changes with the amount of charge stored in the FG as shown in Fig. 1-3 [5]. The change in the VT can be denoted by simple electrical analysis given by

VT = V T0 - Q/C 2 (1)

Where VT0 is the threshold voltage with no charge trapped in the FG, Q is the charge trapped in FG and C2 is the FG/CG capacitance.

Figure 1- 2 Structure and I D-VG characteristic of Flash memory.

3 1.2.2 Write and Erase Operation

The Flash memory cell’s default logic equivalent is binary state of “1”. It can be

SET or programmed to “0” by a phenomenon commonly known as tunneling or hot electron injection. The electrons traveling from source to drain are forced to tunnel through the oxide by applying a high voltage at CG and consequently trapped by the FG.

The programming steps are illustrated in Fig.1-3 (a). When a high bias of ~ 10 V is applied to the CG, the electrons in the channel gain high energy and they are injected through tunnel oxide to the FG as illustrated in Fig. 1-3 (a). The Flash memory cell is then said to be SET or programmed to the binary state “0” [5]. The electrons trapped in the FG are tunneled out by applying high a negative bias to CG. In this way, the memory cell can be again RESET back to “1”. The erase mechanism is illustrated in Fig. 1-3 (b) where V G is gate voltage, VS is source voltage and V D is drain voltage.

Figure 1- 3 Physical mechanism of (a) write by hot carrier injection and (b) tunneling.

4 1.2.3 Reliability Issues of Flash Memory

Even after having features like high mass storage, portability, non-volatility and small cell size there are some issues which makes it difficult to go further in future.

Hence there is a need for a universal memory device to have features like non volatility with long retention time, high speed of operation, low power consumption, high chip density, and scalable beyond 16 nm without any data loss. This section deals with the reliability issues which limit the progress of this technology [6].

1.2.3.1 Scalability Issue of the Oxide

Technology node starting from 45 nm and beyond, the flash memory is expected to face serious scaling issues [7]. In principle it is impossible to fabricate oxides with no defects because at given temperature there is an equilibrium amount of point defects.

When there is a defect in the tunnel oxide, electrons stored in the FG can leak out through trap assisted tunneling mechanism [8]. The tunnel oxide should be thick enough to avoid electrons tunneling through disconnected defects as shown in Fig. 1-4 a and 1-4 b. A single defect in the oxide is inadequate to provide a leakage path in a thick oxide. Even several defects may not cause tunneling if they are not within reach of one another but oxide thickness less than 8 nm is prone to trap-assisted leakage as depicted by percolation model [8].

5

Figure 1- 4 Trap-assisted tunneling shown by percolation model. (a) Single defect in a thin tunnel oxide can cause leakage. The red circle represents the typical distance an electron may tunnel. (b) For a thick oxide a single defect is inadequate to cause tunneling.

The efficiency of writing/erasing via tunneling or hot carrier injection is degraded by the interface traps generated in the tunnel oxide, so the scaling of dielectric thickness at the same reliability is possible only if the defect density is accordingly reduced. [D. Ielmini et al].

1.2.3.2 High Operational Voltage

A flash memory requires very high voltage for its unique features like able to write, erase and read data (especially write and erase). However, this may lead to unintentional data loss from the cell [9].

1.2.3.3 Endurance of Flash Memory Cell

Another major issue related with flash memory technology is the tunneling mechanism required for programming and erasing data from the flash memory cell. The most significant aspect governing the reliability of flash memory is the quality of tunnel oxide, both in terms of intrinsic properties and defect density [10]. The tunneling of the

6 hot electrons from the channel to the FG through the tunnel oxide layer leads to damage of the oxide. This in turn reduces the number of write/erase cycle of the memory cell.

1.2.3.4 Access Time Limitation

One important short-coming of the flash memory is that, even though it can read and program each byte individually in a random access manner, it can only erase one block at a time. This usually sets all bits in the block to logic “1”. To erase a block of memory it takes on the order of 1–2 ms per block, and programming an erased flash needs around 200–300 µs [11]. Additionally, flash memory (specifically NOR flash) can only provide random-access read and programming operations, but not random rewrite or erase operations [12]. In Fig. 1-5 it shows the time required to program decreases with number of times write cycles while the erase time increases with number of cycles of erase operations.

Figure 1- 5 Latency in write and erase cycles after several iterations of tunneling through the oxide.

Hence, tremendous amount of research is going on in search of a universal memory, which merges the high-speed performance of existing DRAM with the non-

7 volatility of Flash. The memory must be able to overcome the issues which present memory technology is facing (scalability, endurance, high operating voltage) to become the next alternative memory [13]. One of the emerging memories which have the potential to replace FLASH is Resistive Random Access Memory (RRAM). The table below from ITRS shows the comparison of Flash with projected potential of a fully scaled RRAM. According to the data projected for RRAM, it has the ability to scale beyond 10 nm technology node and has extremely high write/erase speed unlike flash memory with many more incentives like high endurance, low operating voltage are few to mention.

Table 1. 1 Comparison of performance parameters for fully scaled RRAM with flash.

NAND FLASH RRAM

Minimum F-Scaling 16 nm 5-10 nm

Multi-level 3-bits/cell Yes

Write/Erase Voltage 18-20 V < 0.5 V

Read Voltage 0.1-0.5 V < 0.2 V

Write/Erase Time > 10 µs < 5 ns

Read Speed 15-50 ms < 10 ns

Retention Time 10 years 10 years

Endurance Cycles 10 4-10 5 10 16

8 Chapter 2

Research Motivation

The universal nonvolatile memory must exhibit features like high density, low cost, high performance, low power, greater endurance and retention [14]. The contemporary Si-based flash memories are among the most popular nonvolatile memories because of their high density and low cost of fabrication. However, it suffers from serious reliability issues like future scaling, i.e. the continuous escalation in the density is anticipated to run into physical limitations (beyond 16 nm node). In addition, it suffers from low endurance, low write/erase speed and high operating voltages. To overcome these challenges numerous alternative memory technologies are being explored.

“Resistive Random Access Memory” (RRAM) has sought most attention out of many emerging memory devices. The ITRS has projected that it has potential to scale up to 8 nm, has higher speed for read/write operations (~5 ns), and higher number of write cycles

(>10 16 ). In this thesis, two of the major problems encountered in flash memory and its solution by RRAM to overcome these problems have been brought into focus.

• High Operational Voltage.

• Scaling Limitation.

11 Furthermore, switching characteristics at very low voltages (~ 1.5 V) are reported with higher percentage of O 2 in NiO x. Higher percentage of O 2 would make

NiO x less leaky and would allow for further scaling of the dielectric. Also, the switching behavior, mechanisms of failure, and conduction mechanism in NiO x based RRAM devices are discussed.

2.1 Resistive Random Access Memory

A RRAM is a 2-terminal metal-insulator-metal capacitor with the ability to store data in the form of resistance across the insulator layer. The insulator layer is composed of transition metal oxides (TMO) sandwiched between two metal (possibly different and inert) electrodes. RRAM can be categorized on the basis of switching mechanisms responsible to alter the resistance of the insulator layer from a low resistance state (LRS) to a high resistance state (HRS) and vice-versa. Primarily, the physical mechanism can be broadly divided into “thermal, electrical or ion-migration-based” switching mechanisms.

The ion-migration based mechanisms are related to redox processes which cause the change in the resistance of the insulator layer. The ion-migration can be further sub- divided into cation migration and anion migration induced switching. In TMO, generally oxygen vacancies (Vo 2+ ) are more mobile than cations and hence, most ion-migrated based switching is induced by anion migration. Ionic-migration based switching is mostly results in bipolar switching [15]. Various TMOs have been investigated for resistive switching capability [16]-[21]. Of the several TMOs studied so far, NiO x promises to be a strong candidate for future. NiO x based RRAMs show switching due to presence of Ni

2- 2- vacancies (V Ni ) or O anions. [22]. The p-type doping in NiO x has been widely 11 explained due to the presence of Ni vacancies, as governed by the following relation [23]

[24].

2Ni + 2O → 2NiO + 2V 2− (2) 2 Ni

Fig. 2-1 shows the formation of conducting filament across the NiO x insulator

2- layer due to migration of VNi , on application of positive bias to the Pt (TE) [H. D. Lee and Y. Nishi]. The switching to the LRS state is typically reported as a limited, filamentary effect instead of uniformly dispersed across the entire NiO x layer. This leads to the resistance of the device at LRS independent of the area of the device.

Figure 2- 1 A typical RRAM showing formation of filament by movement of ions.

On the other hand, the thermal effect shows a unipolar characteristic. An initial voltage-induced breakdown of the insulator layer is done (electroforming), to generate a conductive filament across the layer, where the material in the filament is modified due to joule heating [15]. The material of the filament can either be metals diffused from the electrodes or decomposed insulator material like sub-oxides [25]. The filament is ruptured thermally due to high power density hence switching the device back to HRS. It has also been reported that by increasing the compliance current a bipolar switching mechanism can be converted into unipolar mechanism [26]. 12 Although numerous studies have been reported for switching on NiO x based

RRAM, its repeatability, durability, and mechanisms of failure still needs to be understood. From previous studies it has been demonstrated that high percentage of O 2

(in Ar/O 2 gas mixture) in NiO x layer would lead to a monostable switching and hence a low O 2 percentage is required for bistable switching [27], [28] as shown in Fig. 2-2.

According to their studies the current at LRS is from the “electrons mediated by the

2+ 2- 2+ empty states of metallic Ni defects”. More VNi leads to reduction in metallic Ni defects which in turn reduces the number of trapping sites and hence makes the ON state

2- unstable. In other words, the empty states are filled by more number of VNi and hence do not contribute to conduction.

Figure 2- 2 (a) Bistable switching with 3% O 2 and (b) Monostable switching with high (~20%) O 2.

13 Chapter 3

Fabrication Process of RRAM

The first half of this chapter deals with a detailed process flow adopted for the method of fabrication of the NiO x based RRAMs. The second half of the chapter will deal with the typical measurement techniques and characterization process of the devices. In general, a sample (MIM capacitor) will constitute of more than 100 devices. The table below demonstrates the number of experiments runs and samples fabricated. Out of all the samples fabricated, only two samples showed resistive switching, namely Ni/NiO/ Al

1 and Ru/NiO/Ru /W 2.

Table 3 1 List of samples and fabrication parameters.

SAMPLE ID TE BE O2/Ar T OX COMMENTS

(sccm) (Å)

W/NiO/W 1 W W 2.4:9.6 9252 No switching due to too thick of dielectric to

electroform the NiOx.

W/NiO/W 2 W W 2.4:9.6 250 Dielectric too leaky, current not scaling with

area.

14 Ni/NiO/Al 1 Al Ni 2.4:9.6 1200 Showed resistive switching. Failed after few

switching cycles due to oxidation of Al.

Ru/NiO/Ru 1 Ru Ru 2.4:9.6 1200 Failed in fabrication due to problem in Ru

etching.

Ru/NiO/Ru/W Ru Ru 2.4:9.6 1200 Showed resistive switching, W helped in

2 adhesion of Ru to photoresist.

Ru/NiO/Ru/W Ru Ru 1.2:10.8 1200 Showed volatile memory switching, due to

3 oxidation of W. Here, photoresist was removed

before etching Ru.

Ni/G/NiO/Ru Ru G 2.4:9.6 1200 Testing showed that metal was not etched

uniformly throughout the sample causing short

circuit.

*Al: Aluminum, *Ru: Ruthenium, W*: Tungsten, *NiO: Nickel Oxide, *G: Graphene

3.1 Process Flow in Details

Step 1: Wafer Labeling

First a p-type Si substrate was taken and the name of the sample was scribed at the back (non-shining part). Generally, the naming was done as metal (BE)/ metal oxide/metal (TE) followed by a number to represent the sample number.

Step 2: Cleaning and Surface Treatment

. The wafer was cleaned by dipping it in 2% of HF (Hydrofluoric) acid for 10s then followed by 2 minutes de-ionized (DI) water rinse.

Step 3: Deposition of BE

15 The deposition of BE depends on the type of metal chosen. The experiments performed dealt with different types of metals. The deposition parameters for BE are shown in Table 3.1:

Table 3 2 Deposition parameters for BE.

Sample ID BE Tox (nm) Deposition Adhesion layer

Method/Temp

W/NiO/W 1 W 100 Sputtering/ RT NA

W/NiO/W 2 W 100 Sputtering/ RT NA

Ni/NiO/Al 1 Ni 100 Sputtering/ RT NA

Ru/NiO/Ru 1 Ru 100 Sputtering/ RT Titanium

Ru/NiO/Ru/W 2 Ru 100 Sputtering/ RT Titanium

Ru/NiO/Ru/W 3 Ru 100 Sputtering/ RT Titanium

Ni/G/NiO/Ru/W G Unknown *MOCVD/ ~900ºC G deposited on

Ni

*MOCVD: Metal Organic Chemical Vapor Deposition. The entire fabrication process of Graphen is discussed in Appendix D.

Step 4: Deposition of NiO x

A shadow mask was put on top of BE before depositing the oxide layer. It partially covered the BE and hence helped in probing. NiO x was deposited by reactive RF magnetron sputtering on Ni in an O 2 environment. A mixture of O 2 and Ar gas was flown at 5 mTorr working pressure. The deposition rate for NiO x at a power of 200 W and a temperature of 300 ºC, was found to be 77 A/min.

16

Figure 3- 1 Sputtering tool at University of Toledo clean room for thin film depositions.

Step 5: Deposition of TE

TE was deposited using sputtering metal, generally at room temperature. The thickness to be sputtered varied from experiment to experiment.

Table 3 3 Deposition parameters for TE.

Sample ID TE Tox (nm) Hardmasks

W/NiO/W 1 W 100 NA

W/NiO/W 2 W 100 NA

Ni/NiO/Al 1 Al 100 NA

Ru/NiO/Ru 1 Ru 10 No

Ru/NiO/Ru/W 2 Ru 10 W

Ru/NiO/Ru/W 3 Ru 10 W

Ni/G/NiO/Ru/W Ru 10 W

17 Step 6: Prebake

The sample was then heated on a hot plate for 5 minutes at 115 ºC. Then it was left to cool down for 5 minutes before proceeding to the next step. This step ensured that there was no moisture left on the sample before it was ready to be spin coated.

Step 7: Spin coating Photoresist

The sample was placed on the chuck of a spinner and a chemical (primer) was put on it. The primer was spread at the speed of 300 rpm for 5 s and then spun for 30 s at a spin speed of 3000 rpm. Thereafter, photoresist was applied. The photoresist was first spread at 500 rpm for 10 s and then the spin speed was increased to 4000 rpm for 60 s.

Both primer and photoresist were first spread slowly such that they uniformly cover the entire wafer.

Step 8: Soft Bake

After the sample was spin-coated, it was heated for 1 minute on the hot plate at

115 ºC and was allowed to cool for 5 minutes.

Figure 3- 2 Mask Aligner used for photolithography in University of Toledo clean room.

18 Step 9: Photolithography to Pattern Electrodes

The sample was placed on the mask aligner with a mask on it and then it was exposed to UV rays for 15 s. The intensity of the exposed UV ray was 20 mW/cm 2. The part of photoresist which was exposed to UV rays changes its composition, such that it becomes soluble in the developer.

Step 10: Develop Photoresist

The sample was then dipped into the developer. The developer removed all the soluble photoresist leaving behind the unexposed photoresist as it was. Thereafter, the device pattern was well defined.

The patterning of electrode can be classified in to two:

(a) Lift off Technique

The lift off technique was used when the TE was deposited after completing Steps

6 through 9. After that, Step 5 was conducted, followed by Step 10.

(b) Etching Technique

The etching technique was used after all the Steps from 5 through 10 were completed. After etching was successfully completed, the remaining photoresist (on the

TE) was removed by dipping the sample into the PG remover.

19 Chapter 4

Device Characterizations and Switching of Ni/NiO x/Al

RRAMs

In this chapter the device characterization of Ni/NiOx/Al samples are discussed.

The first half deals with the measurement techniques to characterize Ni/NiO/Al samples.

The second half deals with results and discussion of the data obtained from measurement.

All the I-V characteristics of the virgin devices, switching mechanism of the devices, failure mechanisms are discussed in detail. Various parameters including the content of

O2 in NiO x films, applied voltage bias, frequency of the applied bias, work function of the metal electrodes, and free energy for oxidation of the electrodes were analysed for understanding the possible reasons of failure and unpredictability. C-V curve analyses were performed to gain a better understanding of the physics behind this mechanism.

20 4.1 Overview

The samples were probed in a Lakeshore cryogenic probe station and all of the electrical measurements were obtained by using a Keithley 4200 semiconductor characterization system as shown in Fig. 4-1 (a). The voltage bias was applied on the TE electrode while the BE electrode was grounded in all our measurements as shown in Fig.

4-1 (b). The initial J-V curves in positive and negative bias indicated symmetric behavior in spite of a significant difference in the vacuum work functions of Al and Ni. The

Capacitance-Voltage (C-V) characterizations indicated NiO x to be a p-type semiconductor with acceptor doping density between 6 x10 18 cm -3 ~ 5x10 20 cm -3.

Switching behavior was observed after electroforming the devices. The devices failed after multiple switching cycles by switching into a relatively low conductive state. The mechanism of failure was attributed to the formation of Al 2O3 due to a slow oxidation of

Al electrodes with repeated cycles.

Figure 4- 1 (a) Probe Station at UT Nano-laboratory for device characterization, (b) Stack of Al (TE)/NiO x/ Ni (BE) RRAM.

21 4.2 Analysis of Ni/NiOx/Al RRAM

In this section the switching behaviour and mechanisms of failure in NiO x based

RRAM devices are discussed. In the analysis, various parameters including the content of

O2 in NiO x films, applied voltage bias, frequency of the applied bias, work function of the metal electrodes, and free energy for oxidation of the electrodes were analysed for understanding the possible reasons of failure and unpredictability. C-V curve analyses were performed to gain a better understanding of the interface between the TE and NiO x layer.

The current density-voltage (J-V) curves of as-fabricated virgin devices of 100

µm x 100 µm and 200 µm x 200 µm are shown in Fig. 4-2. The J showed an excellent scaling with the area of the devices and was repeatable across the wafer. In spite of a considerable difference in the vacuum work functions of Al and Ni, the J-V characteristics showed symmetric behavior. The barrier heights were extracted from I-V curves of the virgin devices by J-V extrapolation method and were found to be approximately 0.65 eV for all devices. This implied that voltage bias was needed to change the interface contacts from Schottky to Ohmic, such that most of the voltage drop would be across the dielectric and not at the interface. Also, the conductivity of the devices was found to be low from these curves.

22 0.01

0.001 ) 2 0.0001

10 -5

10 -6

) 100 2 -7 10 200um_1 1 200um_2 0.01 200um_3 10 -8 100um _1 0.0001 Current Density(A/cm Forming J (200um) 100um_ 2 10 -6 Forming J (100um) -9 10 100um _3 Current(A/cm Density 10 -8 0 5 10 15 20 25 Voltage (V) 10 -10 -3 -2 -1 0 1 2 3 Voltage (V)

Figure 4- 2 Current density vs. voltage characteristics of virgin devices of 200 µm and 100 µm devices. The inset shows the forming current density vs. voltage characteristic. Both the device sizes, i.e. 200 µm and 100 µm need a high voltage of 20 V to form.

To gain a better understanding of the Al/NiO x interface, C-V measurements were carried out on virgin devices. Fig. 4-3 shows C-V sweeps between -10 V to 10 V on various devices across the wafer. All C-Vs were performed at an a.c. frequency of 1MHz at room temperature. A typical n/p junction characteristic can be observed where Al serves as n-type electrode and NiO x serves the p-type semiconductor. In positive bias sweep (0 to ~6.7 V) when the diode is reverse biased, decrease in the capacitance can be observed due to an increase in the depletion width in NiO x. At around 6.8 V, a slight increase in the capacitance can be observed which could be due to the generation of electrons in depleted NiO x through thermal excitation.

23 7.1 1 0 -8 (a)

7 10 -8 ) 2

6.9 1 0 -8

6.8 1 0 -8

200um_-10to10_1 Capacitance(F/cm 200um_-10to10_2 -8 6.7 1 0 200um_-10to10_3 100um_-10to10_1 100um_-10to10_2 100um_-10to10_3 6.6 1 0 -8 -15 -10 -5 0 5 10 15 Voltage (V)

Figure 4- 3 The capacitance per unit area (F/cm 2) versus voltage (V) curve shows a p- type C-V profile for a voltage range of -10 V to 10 V at 1 MHz for all the device sizes.

Fig. 4- 4 shows 1/C 2 vs. V plot in depletion. Four distinct regions can be clearly defined based on the slope of the curve. The region-1 corresponds to 0 to ~1.3 V with a positive slope of 5 x10 18 F-2 V-1, region-2 corresponds to 1.4 to 2.3 V with positive slope of 8 x10 18 F-2 V-1 , and region-3 corresponds to 2.4 V~6.0 V with a positive slope of 4 x10 18 F-2 V-1. The slope becomes negative in region-4 indicating a change in the type of carriers which was attributed to the generation of thermal electrons in the depletion region of NiO x.

24 1.235 10 21 (b) 1.23 10 21

1.225 10 21

1.22 10 21 ) -2 21 (F

2 1.215 10

1/C 1.21 10 21

1.205 10 21

1.2 10 21

1.195 10 21 0 2 4 6 8 10 12 Voltage (V)

Figure 4- 4 Shows 1/C 2 (F -2) vs. voltage (V) plot in depletion.

Fig. 4- 5 shows doping density vs. voltage plot that was extracted from these

2 1/C -V plots using a dielectric constant of 10 for NiO x [29]. A relatively low dielectric constant was used due to a high O2 content in our films that was expected from the deposition condition [30]. An acceptor doping density between 6 x10 18 cm -3 to 5x10 20 cm -3 was observed. At voltages lower than 0 V (i.e. negative bias) the capacitance value starts to increase. This increase can be attributed to the reduction in the depletion width due to a gradual accumulation of holes at Al/NiO x interface. The C-V characteristics clearly indicated the p-type doping in NiO x.

25 10 22 (c) Doping Density (cm-3)

21 ) 10 -3

10 20

10 19 DopingDensity (cm

10 18 1.0000 2.0500 3.1000 4.1500 5.2000 Voltage (V)

Figure 4- 5 shows doping density vs. voltage plot that was extracted from these 1/C 2-V plots using a dielectric constant of 10 for NiO x.

After the devices were formed, testing was done by applying voltage sweeps from

0 V up to ± 5 V. Fig. 4- 6 illustrates the switching of a 200 µm device where the numbers indicate the sequence of switching and arrows indicate the direction of bias applied. The device started to switch with a SET voltage in the -3 V to -3.5 V range and a RESET voltage of 3 V. Ron/R off ratio of order 10 was achievable. However the device then experienced a sudden drop in conductance. The device then remained in low conductance state even after applying higher bias of 4.5 V and -5 V.

26 0.1 2, 6 3, 7

0.01 4

0.001 1, 5

8 9 0.0001 0 to -3

0 to 3 Current(A) 10 -5 0 to -3.5

10 -6 0 to 3.5

0 to -5 10 -7 -6 -4 -2 0 2 4 6 Voltage (V)

Figure 4- 6 Shows the switching pattern of a 200 µm device after forming. A SET voltage -3 V and RESET voltage of 3 V was achieved.

To investigate the cause of failure, C-V measurement was conducted on the failed devices and it was found that the capacitance of the failed device was less than the capacitance of virgin device as shown in Fig. 4-7. This reduction in the capacitance was attributed to the formation of a thin layer of Al 2O3 at NiO x/Al 2O3 interface. Assuming a continuous layer of Al 2O3, the capacitance of the failed device can be modeled using

Eq.’s (3) and (4).

1 1 1 (3) = + C C C failed NiO Al2O3

C = ξoξrA/ t (4) Al2O3 ox

27 where Cfailed = capacitance of the failed device in low conductive state, CNiO =

capacitance of the virgin device , CAl 2O3 = capacitance of the Al 2O3 layer formed, ξo =

-14 2 dielectric constant of Al 2O3 ~ 10 [31], ξr = 8.854 x 10 F/cm , A= area of Al 2O3 layer (

200 µm x 200 µm ), tox = thickness of Al 2O3 layer. Using these equations, the thickness of

Al 2O3 was calculated to be 38.2 nm. However, we believe that this layer could be discontinuous and may appear only at the certain regions of the interface.

1 10 -7 Virgin Device Failed Device ) 2 9 10 -8

8 10 -8

7 10 -8

6 10 -8 Capacitance(F/cm Density

5 10 -8 -1.5 -1 -0.5 0 0.5 1 1.5 Voltage (V)

Figure 4- 7 A reduction in the capacitance density can be observed in failed device as compared to the virgin device.

This phenomenon was explained by formation of Al 2O3 layer due to oxidation of the TE (Al). When a negative bias is applied, the holes are pushed back and the thermally

2+ generated electrons are trapped in V o . When a positive bias is applied to Al (TE), the holes are accumulating near Al/NiO x interface hence lowering the depletion width, which

28 sets the device however due to low free energy formation of oxide of Al [32], Al 2O3 is getting formed and that leads to failure of the device as illustrated in Fig. 4-8 (a) and (b) respectively.

Al Al O - a)e b) 2 e V 2+ e o

Ni Ni

Figure 4- 8 Illustrates the switching mechanism of a Al/NiO x/Ni. Thermally generated 2+ electrons are trapped by the Vo . (b) Illustrates the failure mechanism of the Al/NiO x/Ni structure due to formation of Al 2O3 layer.

29 Chapter 5

Device Characterizations and Switching of

Ru/NiOx/Ru/W RRAMs

5.1 Ru/NiOx/Ru Based RRAMs

In this chapter the results obtained from the characterization of the successfully fabricated Ru/NiOx/Ru/W devices are discussed. The first half deals with motivation of fabricating this sample and challenges faced during its fabrication. The second half deals with results and discussion after the characterization of Ru/NiOx/Ru/W devices. All the I-

V characteristics of the virgin devices, switching mechanism of the devices, are discussed in detail.

5.1.1 Motivation

Failure of Ni/NiO x/Al RRAM motivated for trying another metal electrode on

NiO x. The reasons and analysis of failure will be discussed in details in the next section.

Fundamentally, Al which has low free energy of oxidation tends to get oxidized and hence reul hence results in failure of the device. In this experiment bipolar switching and

30 hence results in failure of the device. In Ru/NiOx/Ru/W sample bipolar and bistable characteristics with high percentage (20%) of O 2 in NiO x were studied. Switching character istics indicated higher number of SET/RESET cycles without failing unlike

Ni/NiO x/Al sample . Furthermore, the SET or RESET voltages less than ±2 V were achieved. Higher percentage of O 2 in NiO x would make NiO x less leaky and would allow further scaling of the dielectric.

5.1.2 Fabrication Challenges

Ru deposited as TE of 200 µm x 200 µm area was patterned using etching. W was used as a hard mask on top of Ru (TE), which eased the etching of Ru . The samples were probed in a Lakeshore cryogenic probe station and all of the electrical measurements were obtained by using a Keithley 4200 semiconductor characterization system. All the electrical measurements were done by applying posi tive bias to the TE as shown in Fig.

5-1.

Figure 5- 1 Stack of Ru (TE)/ NiO x/ Ru (BE) with W used as hard mask .

31 Etching of Ru was not successful for the first few devices fabricated. The etchant for Ru was ceric ammonium nitric acid which would also slowly etch Ni. Moreover, Ru has known to have adhesion issues. Hence, an extra layer of (W) was added on top of Ru, such that the photoresist sticks well to the stack. After depositing all the layers, the stack was ready for the photolithography and then eventually W and Ru were etched. This lead to successful fabrication of devices using Ru electrodes. However, ceric ammonium nitric acid can also slowly oxidize the photoresist and hence for some of the devices PG remover could not do an excellent job of removing photoresist from the TEs.

5.2 Analysis of Ru/NiOx/Ru/W RRAMs

The dielectric (NiO x) can be scaled further only if dielectric is less conductive, which can be done by increasing the O 2 content in NiO x as it reduces the amount of metallic Ni. Consequently, the roles of metal electrodes on NiO x based RRAM becomes more important as they would decide the switching at low voltages, repeatability, high

Ron / R off ratios. In this section, repeatable switching for Ru (TE)/NiO x/Ru (BE) structure at a voltage ~ (±1.0 V to ±1.5 V) with high percentage of O 2 (20% of O 2/Ar mixture) was observed.

The initial I-V curves of the virgin devices were repeatable as shown in Fig. 5-2.

The barrier heights were extracted from the I-V curves and found out to be 0.5 eV for

Ru/NiO x/Ru. This implied that voltage bias was needed to change the interface contacts from Schottky to Ohmic, such that most of the voltage drop would be across the dielectric

32 and not at the interface. This indicated that the work function of the metal does not dominate the choice of the TE but the free energy of oxidation of metal does.

0.001 (a) 0.0001

10 -5

10 -6

10 -7 Current (A) Current 10 -8 I 200um 1 I 200um 2 10 -9 I 200um 3 I 200um 4 10 -10 -1.5 -1 -0.5 0 0.5 1 1.5 Voltage (V)

Figure 5- 2 Initial I-V curves for Ru/NiO x/Ru of 200 µm x 200 µm area.

0.01 1 4 0.001

0.0001 2 3 10 -5 0.01

0.001

0.0001

Current (A) Current -6 10 10 -5

10 -6

10 -7 -7 (A) Current 10 10 -8

10 -9 0 0.5 1 1.5 2 2.5 3 3.5 Voltage (V) 10 -8 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Voltage (V)

Figure 5- 3 Repetitive switching cycles for Ru/NiO x/Ru of 200 µm x 200 µm and inset shows the forming of device. 33 However, the BE seems to be more conductive than the TE. The potential reason

2- behind it could be trapping of some of the O atoms from NiO x by Ru (BE) electrode while depositing NiO x layer at 300 ºC to form a very thin layer of RuO 2. Moreover, RuO 2 is considered to be a conducting MO x by ITRS [33]. The devices were electroformed by applying a positive bias on TE with a compliance limit SET at 5 mA. After the device hits compliance, 5 mA current started to flow across the device even at low voltage (~1.5

V) as shown in the inset of Fig. 5-3. Repetitive switching cycles (~20 cycles) were observed in the region of ±1.5 V for Ru/NiO x/Ru even with high percentage of O 2 flown in NiO x layer, as evident from Fig. 5-3 where the numbers indicate the sequence of switching and the arrows indicate the direction.

Figure 5- 4 Switching mechanism using filament based model of NiO x based RRAM for [(a) and (b)] Ru/NiO x/Ru structure and (c) Pt/NiO x/Pt structure. Positive bias applied to TE of [(a) and (c)].

Fig. 5-4 illustrates the switching mechanism of Ru/NiO x/Ru structure with high

O2- content. In Fig. 5-4 (a) when a positive bias was applied to the TE, the extra O 2-

2- 2+ atoms or the V Ni got attracted towards the TE creating oxygen vacancies (Vo ).

However, the O 2- atoms which were trapped by the BE could not be moved. This created 34 a smaller size cone shaped conducting filament giving a distinct state of conductance

LRS. The device was switched back to HRS by applying a negative bias which pushed the O 2- atoms back and hence ruptured the filament as shown in Fig. 5-4 (b). Since, free energy of oxide formation for RuO 2 is more negative than free energy of oxide formation for PtO, so oxide formation for Ru will be more favorable than oxide formation of Pt

2- [37], [38]. Hence less/no O atoms would be trapped to the BE (at 300 ºC) for Pt/NiO x/Pt structure as illustrated in Fig. 5-4 (c). Either there will be no place to move the O 2- atoms

2+ to create V o or there can be a slight movement but it cannot be distinguished between two different states of conductance. Moreover, the TE of Pt will attract less O 2- atoms compared to Ru as TE, which will add on to a lesser amount of movement of O 2- atoms in

Pt/NiO x/Pt. Consequently, giving rise to a monostable type of switching. Hence, NiO x with high percentage of O 2- cannot give a bistable switching with Pt as its BE where as

Ru/NiO x/Ru can.

The compliance limit of the current played a vital role in the formation of filament area in Ru/NiO x/Ru structure. To prove this, switching tests were performed on 500 µm x

500 µm device areas by electroforming the devices using different compliance levels. The initial I-Vs showed excellent scaling with area for 200 µm x 200 µm and 500 µm x 500

µm as shown in Fig. 5-5 (a). As the initial current for larger area devices has higher current, the compliance limit for electroforming was raised from 5 mA. The compliance limit was first SET to 30 mA for electroforming. Then the conductance of the device was increased; however, it could not be RESET back due to formation of large area filament.

The same case was observed with a compliance limit of 20 mA. Finally, a compliance

35 level of 10 mA showed repeatable switching as it was observed for 200 µm x 200 µm area size devices as evident from Fig. 5-5 (b)

1

0.1 (a) ) 2 0.01

0.001

0.0001 500um 1 500um 2 500um 3 -5 500um 4 10 200um 1 200um 2

Current Density (A/cm Density Current -6 200um 3 10 200um 4

10 -7 -1.5 -1 -0.5 0 0.5 1 1.5 Voltage (V)

0.1 1 (b) 2 0.01

0.001 3 0.0001

10 -5 1. Compliance: 30mA

Current (A) Current 2. Compliance: 20mA -6 10 3. Compliance: 10mA 10 -7

10 -8 -4 -3 -2 -1 0 1 2 3 Voltage (V)

Figure 5- 5 For Ru/NiO x/Ru of 500 µm x 500 µm area (a) Initial I-V curves and (b) switching with 30 mA, 20 mA and 10 mA compliance level. The device with 10 mA compliance while electroforming showed repeatable switching

. Also, the Ru/NiO x/Ru structure also showed a stable Ron /R off ratio as evident from Fig. 5-6. For Pt/NiO x/Pt, a sacrificial layer of Ni on top of Pt (BE) can reduce the size of the conducting filament as shown in Fig. 5-7 and consequently reduce the RESET

36 current. However, in our case (Ru/NiO x/Ru), the size of the filament is reduced by the BE itself and can be controlled by changing the compliance limit. In the illustration it shows that in Fig. 5-7 (a) larger filament is formed as compared to the Fig. 5-7 (b) Pt/NiO x/Pt with the Ni interfacial layer. However, in Fig. 5-7 (a) very large filament is formed due to low free energy of oxidation of (Al, Ta and Ni) TE.

10 4

Ron_0.5V Roff_-0.5V 1000 Resistance (Ohm) Resistance

100 0 2 4 6 8 10 12 No. of Cycles

Figure 5- 6 A stable Ron /R off ratio of Ru/NiO x/Ru stack.

37

Figure 5- 7 Conducting filament model for Pt/ NiO x/Pt structure (a) with Al as interfacial layer resulting in high RESET current. (b) Ni as interfacial layer to reduce the RESET current [39].

However, in case of (Ru/NiO x/Ru), the size of the filament is reduced by the BE itself and can be controlled by changing the forming current. Moreover, the SET current was dependent on area of the device whereas the RESET current was independent as shown in Fig. 5-8 (a) and 5-8 (b). The SET current for our devices were higher as compared to the SET current for devices reported in literature due to their smaller area devices. The RESET current was observed to depend on the area of the filament formed and which in turn was dependent on the current at which the device was formed as evident from Fig. 5-8 (c).

38 10 (a) ) 2 1

0.1

0.01 HRS_500um1 0.001 HRS_200um1 HRS_500um 2

HRS Current Density (A/cm Density Current HRS HRS_200um 2 0.0001 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Voltage (V)

Figure 5- 8 (a) HRS current density for 200 µm x 200 µm and 500 µm x 500 µm device for Ru/NiO x/Ru.

100 (b) ) 2 10

1

0.1

0.01 Reset Current Density 100um Reset Current Density 200um LRS Current Density (A/cm Density Current LRS Reset Current Density 500um 0.001 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Voltage (V)

Figure 5- 8 (b) LRS current density for 200 µm x 200 µm and 500 µm x 500 µm device for Ru/NiO x/Ru.

39 5 (c) 4 0 /A 3 LRS =A

LRS 2

/R R0/R_LRS_100um 0

R R0/R_LRS_200um Ro/R_LRS_500um 1 Ro/R_LRS_500um Ro/R_LRS_500um

0 0 5 10 15 20 25 Forming Current (mA)

Figure 5- 8 (c) Filament area ( ALRS ) increases with increase in forming current. R0 and A0 are the resistance and area of 100 μm x 100 µm device at 5 mA forming current respectively.

The resistive state of the device in the LRS was modeled by the resistance (R) of the conductive filament in the LRS using the Eq. (5). This model assumes that only one filament is responsible for switching the device from the HRS to the LRS and the filament extends from the BE to the TE.

R = ρl / A (5)

where ρ is the resistivity, l is the thickness of the dielectric and A is the area of the filament. If Ro and Ao are considered as the resistance and area of the filament in a 100

µm x 100 µm device area with a 5 mA forming current, then the other LRS of the device

(RLRS ) obtained with different forming currents can be correlated with the corresponding filament area ( ALRS ) using Eq. (6).

40 R0 / RLRS = ALRS / A0 (6)

Using this relation, the ALRS /A o ratio is plotted in Fig. 5-8 (c). It is evident from

Fig. 5-8 (c) that the area of the filament increased with increasing forming current, decreasing its resistance ( RLRS ). Furthermore, ALRS is independent of the size of the device and depends primarily on the forming current through the device. In light of these observations, it is possible to achieve a better LRS/HRS ratio in deep submicron devices where the LRS current will be governed by the dimension and morphology of the filament while HRS current can be significantly scaled down due to the reduced dimensions of the device.

41 Chapter 6

Mechanism of Conduction in NiOx RRAMs

6.1 Background

In this section, the conduction mechanism at different resistive states has been reported, most importantly at LRS and HRS. As from previous chapters it has been shown that conduction of NiO is filamentary in nature and hence it becomes extremely critical to have full control over its formation and dissolution. One of the major hurdles for scalability of RRAM devices is the “high RESET current”. In order to reduce the

RESET current, the size of the filament formed at LRS is being reduced. However, reduction in the size of the filament at LRS decreases the stability of the filament [40]. To address all such problems it has become very vital to know the mechanism of conduction in NiO x RRAMs especially through filament (LRS). The mechanism of charge conduction in NiO x based RRAM is highly debatable and widely in research. According to present studies it has been shown that NiO x with bipolar switching (Pt as TE and

SrRuO 3 as BE) at LRS tends to fit “ohmic” conduction mechanism. Ohmic contacts were observed between Pt/NiO x and NiO x/SrRuO 3 interfaces [41]. However for HRS it fitted

42 the thermionic emission conduction mechanism. The potential reason given for this was lowering of acceptor density which resulted in an increase in schottky barrier.

6.2 Conduction Mechanism in Ru/NiOx/Ru RRAMs

Temperature dependent measurements have been performed for 200 µm x 200 µm area devices for Ru/NiO x/Ru at temperatures ranging from 100 K-335 K. The data collected were fitted to different transport mechanisms like F-P emission, thermionic- field emission, ohmic, ionic, and trap-assisted-tunneling to determine the dominant conduction mechanism. At LRS, the I-V at different temperatures fitted the “ionic conduction mechanism” very well as shown in Fig. 6-1. The equation used for ionic conduction mechanism for the curve fitting is as follows:

Ionic mechanism for LRS:

I ∞ 1/T exp(-Ea/KT) (7)

43 Temperature (K)

333 250 200 166.6 142.8 125 111 100 2.5

(a) y = 4.6373 * e^(-0.35417x) R 2= 0.93504

2

Ionic_LRS

1.5

1

0.5 Current*Temperature(AK)

0 3 4 5 6 7 8 9 10 11 1000/T (1/K)

Figure 6- 1 Conduction Mechanism at LRS with ionic conduction fit.

The most important factor which decides ionic conduction is the ease with which it can jump or travel to neighboring site. This is termed as the activation energy. The activation energy (Ea) was calculated to be 0.03 eV which is quite low for ion-migration to take place. According to the data obtained through cryogenic measurement, the nature of the filament is semiconductor-like as the resistance is decreasing with increase in temperature. From the C-V analysis the acceptor doping density in as-deposited NiO x was calculated to be of order 10 20 cm -3. It can be inferred that O 2- ion migration through

Ni filament falls in the category of type II ionic conductors, which are generally good ionic conductors at room temperature and fast ionic conductors at high temperatures [42].

Also, lower Ea of 0.03 eV supports that ionic conduction should be fast enough.

However, the resistance will start to increase with temperature beyond the critical temperature of 355 K (the maximum point ionic-conduction curve). The data was also

44 analysed by Ohmic conduction mechanism fitting as shown in Fig. 6-2. As evident from

R2 values of the fitting, ionic conduction shows better fitting than Ohmic conduction.

Therefore, the dominant conduction mechanism through Ni filament was attributed to be ionic over ohmic, which is in contrast with some literature where ohmic conduction was observed. However, those reports are with Pt (TE), SrRuO 3 (BE) and with different composition of NiO x.while my data is with Ru electrodes. Therefore, an open question lies in the understanding if the as-deposited composition of NiOx or the choice of electrodes plays any role in governing the mechanism of conduction in LRS after the filament is formed. Following equation was used for ohmic fitting:

I ∞ exp(1/T) (8)

Temperature (K)

333 250 200 166 142.8 125 111 100 0.007 (b) y = 0.0092591 * e^(-0.18187x) R 2= 0.86571 0.006

0.005

0.004

Ohmic_LRS

Current(A) 0.003

0.002

0.001 3 4 5 6 7 8 9 10 11 1000/T (1/K)

Figure 6- 2 Conduction Mechanism at LRS with ohmic conduction fit at 0.3 V.

45 On the other hand, in HRS, the I-V at different temperatures displayed excellent fitting for “thermionic field emission” mechanism as shown in Fig. 6-4. During the

RESET of the device, the O 2- atoms (holes in this case) will be pushed away from the TE creating a Schottky barrier. Considering Ru workfunction (4.6 eV), electron affinity of

NiO (1.4 eV) and Fermi level of NiO at 5 eV [43], the barrier height was found to be 0.4 eV. Moreover, the barrier height extracted from the curve fitting was found to be 0.24 eV at HRS. I-V for virgin device fitted for voltage dependent conduction mechanism at room temperature displayed excellent fitting for F-P and thermionic emission, as shown in Fig.

6-3. The extracted barrier height was found to be 0.5 eV from the curve fitting .

Thermionic field emission mechanism for HRS:

I ∞ T 2 exp(1/T) (9)

F-P emission for VRS at room temperature:

I ∞ V exp(sqrt(V)) (10)

46 Temperature (K)

333 250 250 166 143 125 111 100 1.4 10 -9 y = 9.5592e-11 * e^(0.27207x) R 2= 0.98535 ) 2 1.2 10 -9 (A/K 2 1 10 -9

8 10 -10

6 10 -10 Current/Temperature

4 10 -10 Thermionic_HRS

2 10 -10 3 4 5 6 7 8 9 10 11

1000/T (1/K)

Figure 6- 3 Conduction Mechanism at HRS with thermionic field emission conduction fit.

0.0001 (a)

y = 6.1616e-6 * e^(2.2172x) R 2= 0.99342 ) -1 I/V (AV I/V

VRS

10 -5 0.2 0.4 0.6 0.8 1 1.2

1/2 V (V)

Figure 6- 4 Voltage dependent conduction mechanism for F-P emission fitting at VRS.

47 0.0001 (b)

10 -5 I(A)

Thermionic VRS 10 -6

y = 2.3251e-7 * e^(5.6957x) R 2= 0.99477

10 -7 0.2 0.4 0.6 0.8 1 1.2

1/2 V

Figure 6- 5 VRS voltage dependent conduction mechanism for thermionic mechanism.

The following table 6.1 summarizes the dominant mechanism of conduction at various resistive states (VRS, LRS and HRS) along with respective parameters being extracted.

Table 6. 1 Summary of Conduction Mechanism dominant at different resistive states.

Resistance States Dominant Conduction Extracted Parameters

Mechanism

VRS Thermionic and F-P Φb = 0.5 eV

emission

LRS Ionic conduction Ea = 0.03 eV

HRS Thermionic Field Emission Φb = 0.24 eV

*Φb is barrier height, * Ea is activation energy

48 Chapter 7

Conclusions and Future Work

7.1 Conclusions

The fundamental properties of NiO x based RRAM devices with Al, Ru as TE and

Ni and Ru as BE were studied respectively. The NiO x deposition was performed in a relatively high oxygen (20% oxygen in Ar by flow rate) environment.

For Ni/NiO x/Al the initial J-V curves in positive and negative bias indicated symmetric behavior in spite of a significant difference in the vacuum work functions of

Al and Ni. The C-V characterizations indicated NiO x to be a p-type semiconductor with acceptor doping density between 6 x10 18 cm -3 to 5x10 20 cm -3. Switching behavior was observed after electroforming the devices. The devices failed after multiple switching cycles by switching into a relatively low conductive state. The mechanism of failure was attributed to the formation of Al 2O3 due to a slow oxidation of Al electrodes with repeated cycles. So TE with low affinity for O 2 was chosen i.e Ru.

To conclude for Ru/NiO x/Ru stack, NiO x based resistive RAMs with higher percentage of O2- atoms can show bistable and repetitive switching with Ru as its BE.

49 2- NiO x with high O atoms make it less leaky and hence would allow further scaling of the dielectric thickness. Also by optimizing the compliance level, the size of conducting filament can be controlled. The area of the filament was shown to be dependent primarily on the compliance current during the forming process and independent of the device area.

Conversely, HRS current density was shown to be uniform across the device indicating that it can be reduced by scaling down the size of the device. In light of these observations, we believe that a better LRS/HRS ratio can be achieved as the device dimension is scaled down into the deep submicron regime.

7.2 Future Work

There is no end in improvising any research output, so it is with this. The Ron /R off can be improved by experimenting with different electrode at the bottom after knowing that bistable switching is possible with Ru as TE. Switching speed analysis, durability test needs to be performed in these devices for comparison with other emerging memory devices. The routes to reduce the reset current needs to be investigate. Also, the role of electrodes and composition of NiO x in switching performance needs further understanding.

A Ru/NiO x/Graphene stack was prepared whose process flow is described in the

Appendix. D Graphene electrode has the potential to reduce the switching voltage [43] and hence reduce the power consumption. Moreover, it is transparent [44] and flexible

[45] material too. Its tremendous mobility [46] can also benefit the RRAM technology with high speed switching possibly by providing low sheet resistance electrodes.

50 References

[1] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to Flash

Memory,” Proceedings of IEEE , vol. 91 no. 4, pp. 489-501, 2003.

[2] H.S. Philip Wong, “Emerging Memories,” 2008, [Online]: asia.stanford.edu/events/spring08/slides402S/0403-Wong.pdf.

[3] “Flash Memory Technology,” [Online]: http://smithsonianchips.si.edu/ice/cd/MEMORY97/SEC10.PDF.

[4] Wikipedia, “Flash Memory,” April, 2008, [Online]: http://en.wikipedia.org/wiki/Flash_memory.

[5] D. Ielmini, A. Spinelli, and A. Lacaita, “Recent developments on Flash memory reliability,” Microelectronic Engineering, vol. 80, pp. 321-328, 2005.

[6] S. Verma, “Tunnel Barrier Engineering for Flash Memory Technology,” dissertation

Standford University, May, 2010.

[7] K. Kinam, “Technology for sub-50nm DRAM and NAND flash manufacturing,” in

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., pp. 323-

326.

[8] C.-Y. Lu, K.-Y. Hsieh, and R. Liu, Future challenges of flash memory technologies , vol. 86, no. 3. 2009, pp. 283 - 286.

51 [9] S. Aritome, R. Shirota, G. Hemink, T. Endoh, and F. Masuoka, “Reliability issues of flash memory cells,” Proceedings of the IEEE, vol. 81, no. 5, pp. 776-788, May 1993.

[10] P. Cappelletti, “Flash memory reliability,” Microelectronics Reliability, vol. 38, no.

2, pp. 185-188, Feb. 1998.

[11] A. Leventhal, “Can flash memory become the foundation for a new tier in the storage hierarchy?” Communications- ACM, 2008, vol 51; no. 7, pp. 47-51

[12] D. Myers, “On the Use of NAND Flash Memory in High-Performance Relational

Databases” Thesis , Massachusetts Institute of Technology, 2008.

[13] S.-E. Ahn et al., “Write Current Reduction in Transition Metal Oxide Based

Resistance Change Memory,” Communications , vol. 20, no. 5. 2008, pp. 924 - 928.

[14] R. Waser, R. Dittmann, G. Staikov, and Kristof Szot, “Redox-Based Resistive

Switching Memories –Nanoionic Mechanisms, Prospects, and Challenges,” Advacned

Materials , vol. 21, no.25-26, 2009, pp 2632-2663.

[15] R. Waser and M. Aono, “Nanoionics-based resistive switching memories,” Nature materials , vol. 6, no. 11, pp. 833-40, Nov. 2007.

[16] M.D. Pickett, D.B. Strukov, J.L. Borghetti, J.J. Yang, G.G. Snider, D.R. Stewart, and R.S. Williams, “Switching dynamics in titanium dioxide memristive devices,”

Journal of Applied Physics , vol. 106, pp. 1-6, 2009.

[17] B.J. Choi, D.S. Jeong, S.K. Kim, C. Rhode, S. Choi, J.H. Oh, J. Kim C.S. Hwang, K.

Szot, R. Waser, B. Reichenberg, and S. Tiedke, “Resistive switching mechanism of TiO 2 52 thin films grown by atomic-layer deposition,” Journal of Applied Physics , vol. 98, pp. 1-

10, 2005.

[18] S. Seo, M.J. Lee, D.C. Kim, S.E. Ahn, B.–H Park, Y.S. Kim, I.K. Yoo, I.S. Byun,

I.R. Hwang, S.H. Kim, J.-S. Kim, J.S. Choi, J.H. Lee, and S.H. Jeon, “Electrode dependence of resistance switching in polycrystalline NiO films,” Applied Physics

Letters , vol. 87, 1-3, 2005.

[19] G.-H. Buh, I. Hwang, and B.H. Park, “Time-dependent electroforming in NiO resistive switching devices,” Applied Physics Letters , vol. 95, pp. 1-3, 2009.

[20] M.Y. Chan, T. Zhang, V. Ho, and P.S. Lee, “Resistive switching effects of HfO 2 high-k dielectric,” Microelectronic Engineering Journal , vol. 85, pp. 2420-2424, 2008.

[21] L. Goux, P. Czarnecki, Y.Y. Chen, L. Panstisano, X.P. Wang, R. Degraeve, B.

Govoreanu, M. Jurczak, D.J. Wouters, and L. Altimime, “Evidences of oxygen-mediated resistive-switching mechanism in TiN\HfO 2\Pt cells,” Applied Physics Letters , vol. 97, pp. 1-3, 2010.

[25] A. Beck, J. G. Bednorz, Ch. Gerber, C. Rossel, and D. Widmer, “Reproducible switching effect in thin oxide films for memory applications,” Applied Physics Letters , vol. 77, no. 1, pp. 1-3, 2008.

[26] D.Seok Jeong, H. Schroeder, and R. Waser, “Coexistence of Bipolar and Unipolar

Resistive Switching Behaviors in a Pt/TiO2/Pt Stack,” Electrochemical and Solid States

Letter” ,vol 10,no 8, pp. G51-G53 2007.

[27] W.-B. Zhang, N. Yu, W.-Y. Yu, and B.-Y. Tang, “Stability and magnetism of vacancy in NiO: A GGA+U study,” European Physical Journal B, vol. 64, pp. 153-158,

2008.

53 [28] K. Jung, J. Choi, Y. Kim, H. Im, S. Seo, R. Jung, D.C. Kim, J.-S. Kim, B.H. Park, and J.P. Hong, “Resistance Switching Characteristics in Li- doped NiO,” Journal of

Applied Physics , vol. 103, pp. 1-4, 2008.

[29] S. Seo, M.J. Lee, H. Seo, E.J. Jeoung, D.-S. Suh, Y.S. Joung, I.K. Yoo, I.R. Hwang,

S.H. Kim, I.S. Byun, J.-S. Kim, J.S. Choi, and B.H. Park, “Reproducible resistance switching in polycrystalline NiO films,” Applied Physics Letters , vol. 85, no. 23, pp.

5655-5657, 2004.

[30] Z.K. Wei, L. Qi, L.H. Bing, L.Y. Tao, W. Yan, W. Tai, W. Ming, Z. Sen, and L.

Ming, “Progress in rectifying-based RRAM passive crossbar array,” Science in China.

Series E , Technological Sciences , vol. 54, pp. 811-818, 2011.

[32] Research Projects [Online] http://www.eng.utoledo.edu/eecs/faculty_web/~rjha/research_projectsNew.html.

[32] D. Schroder, Semiconductor Material and Device Characterization , Third Ed.,

Wiley, New Jersey, 2006.

[33] M.-D. Lee, C.-H. Ho, C.-K. Lo, T.-Y. Peng, and Y.-D. Yao, “Effect of Oxygen

Concentration on Characteristics of NiO x-Based Resistance Random Access Memory,”

IEEE Transactions on Magnetization , vol. 43, no. 2, pp. 939-942, 2007.

[34] S. Lany, J. Osorio-Guillén, A. Zunger, “Origins of the doping asymmetry in oxides:

Hole doping in NiO versus electron doping in ZnO,” Physical Review B, vol . 75, no. 24, pp. 1- 4, 2007.

[35] C.B. Lee, B.S. Kang, A. Benayad, M.J. Lee, S.-E. Ahn, K.H. Kim, G. Stefanovich, and Y. Park, “Effects of metal electrodes on the resistive memory switching property of

NiO thin films,” Applied Physics Letters , vol. 93, pp. 1-3, 2008.

54 [36] K. Fröhlich, K. Husekova, D. Machajdik, J.C. Hooker, N. Perez, M. Fanciulli, S.

Ferrari, C. Wiemer, A. Dimoulas, G. Vellianitis, and F. Roozeboom, “Ru and RuO 2 gate electrodes for advanced CMOS technology,” Material Science Engineering B, vol. 109, pp. 117-121, 2004.

[37] The PGM Database- Platinum Metals Review [Online] http://www.platinummetalsreview.com/jmpgm/index.jsp.

[38] L. Brewer, “The Thermodynamic Properties of the oxides and their Vaporization process,” Chemical Review , vol. 52, no. 1, pp. 1-75, 1953.

[39] H.D. Lee and Y. Nishi, “Reduction in reset current of unipolar NiO-based resistive switching through nickel interfacial layer,” Applied Physics Letters , vol. 97, no. 25, pp.

252107-1-252107-3, 2010.

[40] U. Russo, D. Ielmini, C. Cagli, and A.L. Lacaita, “Filament Conduction and Reset

Mechanism in NiO-Based Resistive-Switching Memory (RRAM) Devices”, vol. 56, no.

2, pp. 186-191, 2009.

[41] F. Kurnia, C. Jung, C. Liu, S.B. Lee, S.M. Yang, H.W. Park, S.J. Song and C.S.

Hwang, “Effect of NiO Growth Conditions on the Bipolar Resistance Memory Switching of Pt/NiO/SRO Structure,” Journal of the Korean Physical Society, vol. 57, no. 6, pp

1856-1861, 2010.

[42] P. Kumar and Y. Yashonath, “Ionic conduction in the solid state”, Journal of

Chemical Science , vol. 118, no. 1, pp. 135-154, 2006.

[43] C.M. Garner, G. Kloster, G. Atwood, L. Mosley, and A. C. Palanduz, “Challenges for dielectric materials in future integrated circuit technologies,” Microelectronic

Reliability , vol. 45, pp. 919-924, 2004.

55 [44] A. Tataroglu, S. Altındal, and M.M. Bulbul, “Temperature and frequency dependent electrical and dielectric properties of Al/SiO 2/p-Si (MOS) structure,” Microelectronic

Engineering Journal, vol. 81, no. 1, pp. 140-149, 2005.

[45] R. Chau, S. Datta, M. Doczy, J. Kavalieros, and M. Metz, “Gate dielectric scaling for high-performance CMOS: from SiO 2 to high-k”, [Online] http://www.intel.com/technology/silicon/ieee/IWGI2003.pdf .

[47] T.P Ma, W. He, and M. Wang, “Defects in High-k Gate Dielectrics,” E. Gusev , ed.,

Springer, vol. 220, pp. 61-72, 2006.

[48] R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, and M. Metz, “High-k/metal- gate stack and its MOSFET characteristics,” IEEE Electron Device Lettters , vol. 25, no.6, pp. 408-410, 2004.

[49] R. Jung, “Fermi-Level Pinning at the Poly-Si/HfO 2 Interface,” Journal of Korean

Physical Society , vol. 55, no. 6, pp. 2501-2504, 2009.

[50] E.P. Gusev, D.A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Zafar, P.C.

Jamison, D.A. Neumayer, M. Copel, M.A. Gribelyuk, H. Okorn-Schmidt, C. D’Emic, P.

Kozlowski, K. Chan, N. Bojarezuk, L.-A. Ragnarsson, P. Ronsheim, K. Rim, R.J.

Fleming, A. Mocuta, and A. Ajmera, “Ultrathin high-K gate stacks for advanced CMOS devices,” International Electron Devices Meeting , pp. 451-454, Washington DC, USA,

Dec. 2001.

[51] M.G. Betti, G. Bertoni, V. Corradini, V.De Renzi, and C. Mariani, “Metal-Induced

Gap States at InAs (110) Surface,” Surface Science , vol. 454, pp. 539-542, 2000.

56 [52] K. Xiong, P.W. Peacock, and J. Robertson, “Fermi level pinning and Hf–Si bonds at

HfO 2: Polycrystalline silicon gate electrode interfaces,” Applied Physics Letters , vol. 86, pp. 1-3, 2005.

[53] L. Pantisano, V.V. Afanas’ev, S. Cimino, C. Adelmann, L. Goux, Y.Y. Chen, J.A.

Kittl, D. Wouters, and M. Jurczak, “Towards barrier height modulation in HfO 2/TiN by oxygen scavenging – Dielectric defects or metal induced gap states?,” Microelectronic

Engineering Journal , vol. 88, pp. 1251-1254, 2011.

[54] M.V. Fischetti, D.A. Neumayer, and E.A. Cartier, “Effective electron mobility in Si inversion layers in metal–oxide–semiconductor systems with a high-k insulator: The role of remote phonon scattering,” Journal of Applied Physics , vol. 90, no. 9, pp. 4587–4608,

2001.

[55] V K Khanna, “Physics of carrier-transport mechanisms and ultra-small scale phenomena for theoretical modelling of nanometer MOS transistors from diffusive to ballistic regimes of operation,” Physics Reports , vol. 398,pp. 67-131, 2004.

[56] R.E. Yang-Yu Fan Nieh, J.C. Lee, G. Lucovsky, G.A. Brown, L.F. Register, S.K.

Banerjee, “Voltage- and temperature-dependent gate capacitance and current model: application to ZrO 2 n-channel MOS capacitor,” IEEE Transactions on Electron Devices , vol. 49, no. 11, pp. 1969-1978, 2002.

[57] S.Y. Tan, “Challenges and performance limitations of high-k and oxynitride gate dielectrics for 90/65 nm CMOS technology,” Microelectronic Engineering Journal , vol.

38, pp. 783-786, 2007.

[58] C.H. Fu, K.S. Chang, Y.A. Chang, Y.Y. Hsu, T.H. Tzeng, T.K. Wang, D.W. Heh,

P.Y. Gu, and M.J. Tsai, “A low gate leakage current and small equivalent oxide thickness

57 MOSFET with Ti/HfO 2 high-k dielectric,” Microelectronic Engineering Journal , vol. 88

201, pp 1309-1311, 2011.

[59] Z.J. Luo, X. Guo, and T.P. Ma, “Temperature dependence of gate currents in thin

Ta 2O5 and TiO 2 films,” Applied Physics Letters , vol. 79, no. 17, pp. 2803-2804, 2001.

[60] W.J. Zhu, T.P. Ma, T. Tamagawa, J. Kim, and Y. Di, “Current transport in metal/Hafnium oxide Silicon structure,” IEEE Electron Device Letters , vol. 23, pp.97-99,

2002.

[61] C. Lin, J. Kang, D. Han, D. Tian, W. Wang, J. Zhang, M. Liu, X. Liu, and R. Han,

“Electrical properties of Al 2O3 gate dielectrics,” Microelectronic Engineering , vol. 66, pp. 830-834, 2003.

[62] A. Negarestani, S. Setayeshi, M.G. Maragheh, and B. Akashe, “Estimation of the radon concentration in soil related to the environmental parameters by a modified

Adaline neural network,” Applied Radiation and Isotopes , vol. 58, no.2, pp. 269-273,

2003.

[63] K.E. Kweon, J.H. Lee, Y.-D. Ko, M.-C. Jeong, J.-M. Myoung, and I. Yun, “Neural network based modeling of HfO 2 thin film characteristics using Latin Hypercube

Sampling,” Expert Systems with Applications , vol. 32, pp. 358–363, 2007.

[64] P. Ojala, J. Saarinen, P. Elo, and K. Kaski, “Novel technology independent neural network approach on device modeling interface,” IEE Proceedings-Circuits Devices

Systems , vol. 142, no. 1, pp. 74-82, 1995.

[65] G.L. Creech and J.M. Zurada, “Neural network modeling of GaAs IC material and

MESFET device characteristics,” John Wiley and Sons , pp. 242-253, 1999.

58 [66] S. Sze and K. Ng, Physics of Semiconductor Devices , Third Ed., Wiley, New Jersey,

2007.

[67] D. Schroder, Semiconductor Material and Device Characterization , Third Ed.,

Wiley, New Jersey, 2006.

[68] L. Liao, J. Bai, R. Cheng, Y.-C. Lin, S. Jiang, Y. Huang, and X. Duan, “Top-Gated

Graphene Nanoribbon Transistor with Ultrathin High-k Dielectrics,” Nano letters ,

American Chemical Society , vol. 10, pp. 1917–1921, 2010.

[69] M. Liang, B. Luo, and L. Zhi, “Application of graphene and graphene-based materials in clean energy-related devices,” International Journal of Energy Research , vol.

33, pp. 1161-1170, 2009.

[70] K.S. Kim, Y.Zhao, H. Jang, S.Y. Lee, J.M. Kim, K.S. Kim, J.-H. Ahn, P. Kim, J.-Y.

Choi, and B.H. Hong, “Large-scale pattern growth of graphene films for stretchable transparent electrodes,” Nature , vol. 457, pp. 706-710, 2009.

[71] J.Y. Son, Y.-H. Shin, H. Kim, and H.M. Jang, “NiO Resistive Random Access

Memory Nanocapacitor Array on Graphene,” Nano letters, American Chemical Society , vol. 4, pp. 2655–2658, 2010.

[72] J. Kwo and M. Hong, “Research advances on III–V MOSFET electronics beyond Si

CMOS,” Journal of Crystal Growth , vol. 311, no. 7, pp. 1944-1949, 2009.

59 Appendix A

Statistics of Ni/NiO x/Al devices failure

Table A. 1 Switching analysis for For 200 µm devices.

Device # Stuck in State Current Level Voltage (A) (V) 1 High Hits compliance -3 2 Low 10E-7 1.5 3 Low 10E-2 2.5 4 High Hits compliance -5 5 Low 10E-3 3.5

Table A. 2 Switching analysis for 100 µm devices.

Device # Stuck in State Current Level (A) Voltage (V)

1 High Hits compliance 2 2 Low 10E-3 -4 3 Low 10E-4 3 4 Low 10E-4 -4 5 High Hits Compliance 3

60 Table A. 3 Switching analysis for 50 µm devices.

Device # Stuck in State Current Level Voltage (A) (V)

1 High Hits compliance 3

2 High Hits compliance 3 3 High Hits compliance -3 4 Low 10E-3 -1.5

61 Appendix B

Repeatable Devices for Ru/NiO x/Ru Switching

0.01

0.001

0.0001

10 -5 Cycle 1 Cycle 2 Cycle 3 Current (A) Current Cycle 4 -6 10 Cycle 5 Cycle 6 Cycle 7 -7 Cycle 8 10 Cycle 9 Cycle 10

10 -8 -1.5 -1 -0.5 0 0.5 1 1.5

Voltage (V)

Figure B- 1 200 µm device 1 showing switching cycles.

.

62 0.01

0.001

0.0001 Cycle 1 Cycle 2 Cycle 3 -5 Cycle 4 10 Data R7D7 Forming loops Cycle 5 0.01 0.001

Current (A) Current Cycle 6 Cycle 7 0.0001 10 -6 Cycle 8 10 -5 Cycle 9 10 -6

Cycle 10 Current (A) -7 10 Current (A) -7 Cycle 11 10 10 -8 Cycle 12 10 -9 Cycle 13 0 0.5 1 1.5 2 2.5 3 Voltage (V) 10 -8 -1.5 -1 -0.5 0 0.5 1 1.5

Voltage (V) Figure B- 2 200 µm device 2 showing switching cycles.

0.01 (b)

0.001

0.0001

10 -5

Data R7D8 Forming 0.01 0.001 Current(A) -6 10 0.0001 10 -5 10 -6

-7 Current(A) -7 10 10 -8 10 Current (A) 10 -9 0 0.5 1 1.5 2 2.5 3 3.5 10 -8 Voltage (V) -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Voltage (V)

Figure B- 3 200 µm device 3 showing cycles.

63 Appendix C

Charge Transport Mechanism in High-k Dielectric

Based MOS Capacitors

C.1 Introduction

Gate leakage current is becoming the bottleneck in designing of the high speed and low power consumption devices due to continuous scaling of the dielectric thickness of SiO 2 [33]. To ensure Moore’s Law remains valid in the next decade, leading integrated circuits (ICs) manufacturers are now making a breakthrough by replacing the long standing SiO 2 and polysilicon [34] gate with high-k dielectrics like HfO 2, Al 2O3, TiO 2, and with a metal gate like Ti, W, Pt etc. respectively [35], [36]. The reason for replacement of poly-silicon gate with that of metal gate is to avoid high threshold voltages which arise due to Fermi-level pinning along with degradation of channel carrier mobility [37] - [39]. Fermi level pinning is nothing but inability to entirely move the

Fermi level (E F) across Si band gap [40], [41].

However, in poly-Si/HfO 2 interface (metal induced gap states) MIGS are more in number and die less swiftly as compared to SiO 2. Hence, a larger alteration in work 64 function would be needed to oscillate E F across the Si band gap [42]. High-k based dielectric helps in maintaining the same capacitance as that of SiO 2 dielectric but with a thinner material layer [43]. In spite of significant research progress in this area [44], the mechanism of charge transport responsible for the gate leakage current and its dependence on the gate dielectrics and metal electrodes is not well-understood. To address this problem, in this chapter, the charge conduction mechanism of gate leakage current in different high-k dielectric based MOS capacitors with metal electrodes on top, have been reported. Temperature dependent measurements were made to compare the charge transport mechanism of atomic layer deposited (ALD) HfO 2 based MOS capacitor with that of ALD Al 2O3 based MOS capacitor with Ti and W electrodes. In addition to that, temperature dependent measurements were made to compare the charge transport mechanism of atomic layer deposited (ALD) HfO 2 based MOS capacitor with that of

Al 2O3 based MOS capacitor with Ti and W electrodes. I-V curves were fitted for different conduction mechanisms at different temperatures and voltage ranges [45]. A neural network method of modeling has been employed to ease the duplication of same sample by avoiding calculating parameters like effective mass of electron, material specific parameters, which reduces the cost of fabrication and increases the speed of data acquisition.

C.2 Background

The reduction of the gate dielectric thickness is one of the core reasons for increase in gate leakage current of MOS device [46]. To minimize this gate leakage current, many high-k gate dielectrics have been recommended to substitute SiO 2 in MOS structure with 65 effective oxide thickness (EOT) lower than 1.5 nm [47]. To study the interface better, temperature dependent measurements is one of the most important methods to determine the charge transport mechanism of the gate leakage current. Temperature dependent study was performed on Ta 2O5 and TiO 2 films to determine their conduction mechanisms and to verify whether the gate leakage current is supportable at high temperatures for either of these high-k dielectrics. From studies it was found that in Ta 2O5, I-Vcurves showed stronger temperature dependence than in TiO 2 samples [48], [49]. The chief reason was a lower electron barrier height in Ta 2O5, which resulted in Schottky emission to dominate the charge conduction mechanism. On the contrary, the TiO 2 sample demonstrated tunneling as the dominant conduction mechanism in the high-field region, and F-P conduction in the low-field region. In literature it was reported that, for HfO 2 dielectric, a high work function metal (Pt) would be responsible for F-P emission conduction mechanism [50]. This is because the Schottky barrier height would be larger than the energy level of the traps. However, for an Al electrode, Schottky emission dominated the conduction mechanism of gate leakage current. On the other hand, it has been proved that, Al 2O3 dielectric based MOS capacitor with Al electrodes showed F-P emission to be dominating charge transport mechanism at Al/Al 2O3 interface [51]. In spite of these available researches, a rigorous comparison was needed to identify which conduction mechanism dominates at which voltage level and temperature range for a specific metal/dielectric interface. Temperature dependent comparison has been made at different voltage range to identify the dominant current conduction mechanism. In addition, a neural network model based on Quasi-Newton algorithm was employed for ease of sample reproduction by avoiding extracting parameters like barrier height, effective mass

66 from equations which are labor intensive and time consuming processes. Neural network’s potential to learn quickly for building convincing solutions to unformulated problems, manage computationally expensive models, deliver fast interpolative analysis, and attaining very precise functional relationships between data SETs are its major advantages [52]. It is a well-established method for various process modelings such as the molecular beam epitaxy and plasma-enhanced chemical vapor deposition processes in semiconductor industry [53]. In literature, modeling of semiconductor process device characteristics was done in both the forward and inverse direction [54]. A multilayer perceptron neural network (MLPNN) was used for development of model. In the forward direction, data obtained from the characteristics of earlier fabrication processing points were used as input to a MLPNN, and the last characteristic values were modeled. On the other hand, for inverse modeling, final DC device characteristics measurements of total wafer were used as input to an MLPNN, and in-process characteristic data were modeled.

This method eliminates the necessity to statistically describe parametric deviation across a wafer. Modeling of gate leakage current is implemented for reducing the non- uniformity in fabrication process and collect additional data without fabricating the samples again.

C.3 Experimental

HfO 2 and Al 2O3 dielectric films were deposited on p-type Si wafers by ALD process at 300 °C. The thicknesses for both of the dielectrics were measured to be ~60 Å using ellipsometer. W and Ti metals of 1000 Å were deposited by RF sputtering and the gate electrodes were formed by the liftoff technique on all four devices, namely Al 2O3/Ti, 67 Al 2O3/W, HfO 2/Ti, and HfO 2/W. The back contact was formed by depositing 1000 Å of

Al on the backside of the samples by RF magnetron sputtering followed by a rapid thermal annealing (RTA) in N 2 environment at 600 ºC for 5 minutes to achieve a low resistance ohmic contact.

The modeling of the collected data (gate leakage current) was done using feed forward neural network which constitutes of an input layer, a hidden layer and an output layer. Each layer comprises of several elements called neurons, where the input layer is a relay function, hidden layer is sigmoid function and output layer is linear function of hidden neurons. Each neuron in a layer has an input from previous layer and a constant

(called bias) while its output is forwarded to the next layer. The inputs and outputs of the neuron are multiplied by a factor called weights. This feed forward neural network develops a model from the training data supplied. The network is said to be feed forward because each component/element in a layer receives inputs only from the components/elements in the previous layer. The modeling was done by covering the entire temperature points lying in the range of 300 K – 400 K using Quasi-Newton algorithm. Firstly the data set available from experiment was randomized and then segregated into two sections, namely training data set and validation data set. Voltage (-4

V to 4 V) and temperature (300 K, 350 K, 400 K) were taken as the two inputs for the neural network and current (corresponding to the voltage range) as the output. Out of the total data points, 80% were taken to train the neural network and 20% for validating the results. Neural network approach was taken for modeling because the same or additional results can be obtained again without revisiting the whole process of fabrication and

68 testing. This model will increase the uniformity in fabrication, simplify the data acquisition process and hence increase the future yield.

C.4 Results and Discussions

The samples were probed in the Lakeshore cryogenic probe station and I-V characteristics were obtained by Keithley 4200 Semiconductor Characterization System.

The room temperature measurements of gate leakage current for all four samples are shown in Fig. C-1(a). Currents for both devices with Ti electrodes resulted in much lower currents than those with W electrodes.

10 -2 10 -3 10 -4 10 -5 10 -6 10 -7 10 -8 (a) 10 -9

-10 Current HfO 2_W_300K

Gate Leakage Current (A) Current Leakage Gate 10 Current Al 2O3_W_300K -11 10 Current HfO 2_Ti_300K Current Al O _Ti_300K 10 -12 2 3 -4 -3 -2 -1 0 1 2 3 4

Voltage (V)

Figure C- 6 (a) I-V measurements for HfO 2/W, HfO 2/Ti, Al 2O3/ W, and Al 2O3/Ti at room temperature.

Temperature dependent studies of gate leakage current were performed for all four devices. The range of temperature, for which, gate leakage currents were measured was from 120 K to 400 K as shown in Fig. C-1(b), with an applied voltage of -4 V. At

69 temperatures below 250 K, tunneling mechanism dominates as the primary conduction mechanism for all four devices as evident from Fig. C-1(b).

10 -2

10 -3

Current_HfO _W_-4V -4 2 10 Current_Al 2O3_W_-4V Current_Al 2O3_Ti_-4V 10 -5 Current_HfO 2_Ti_-4V

-6 10 (b)

10 -7 Gate Leakage Current (A) Current Leakage Gate 10 -8

2 3 4 5 6 7 8 9 1000/T (1/K)

Figure C- 1 (b) Gate leakage current vs 1000/T for Al 2O3 and HfO 2 based MOS Capacitors with W and Ti electrodes.

For temperatures at and above room temperature, any of the three, i.e. , F-P,

Schottky emission and tunneling mechanism may dominate depending upon the voltage range. The processes are not completely independent of each other. It can be observed from Fig. C-1(b) that at higher temperatures, W based samples is showing much higher current than those of Ti based samples. For samples using W electrodes, it is observed that both F-P emission and tunneling mechanism are dominating at the same time.

However, for samples using Ti electrodes, tunneling mechanism is dominant at low temperatures only. I-V curves for all the four samples were fitted at 300 K, 350 K, and

400 K employing the following equations [55], [56]:

F-P Emission:

70 J ∝ E exp(−q(φb − (qE /πξ /) KT) (11)

where J is current density, E is electric field of the insulator, φb is barrier height,

ξ is dielectric permittivity.

Schottky Emission:

2 J = AT exp(−q(φb − (qE /πξ /) KT) (12)

where A is effective Richardson constant.

Tunneling:

2 2/3 J ∝ E exp(− 4( 2m(qφb ) 3/) qhE)) (13)

For temperatures above room temperature (300 K, 350 K, 400 K), the observation is split into two cases. Case1 deals with all the samples in high field region (-1.5 V to -4

V) and Case 2 deals with all the samples in low field region (-0.005 V to -1.5 V).

71 18.0 300K 17.5 350K 400K 17.0 )) 2 16.5 (a) 16.0 -ln(J/(AT 15.5

15.0

14.5 2100 2200 2300 2400 2500 2600

1/2 1/2 E (V/cm)

2 1/2 Figure C- 7 (a) Schottky emission curve fit for Al 2O3/Ti samples [–ln(J/(AT )) vs E 1/2 (V/cm) ] for Al 2O3/Ti at high field at temperatures of 300 K, 350 K and 400 K.

HfO 2_Ti_300K HfO 2_Ti_350K 26 HfO 2_Ti 400K Al 2O3_W_300K 24 Al 2O3_W 350K 22 Al 2O3_W_400K 20

18 (b) 16 14 -ln(J/E) (A/V*cm) -ln(J/E) 12 10 8 0 500 1000 1500 2000 2500 3000 E1/2 (V/cm) 1/2

Figure C- 2 (b) F-P emission curve fitting [–ln(J/E) (A/V*cm) Vs E1/2 (V/cm) 1/2 ] for Al 2O3/W and HfO 2/Ti at low and high fields at temperatures of 300 K, 350 K and 400 K.

72 In case 1 the I-V curve for sample 1(Al 2O3/Ti) fits the Schottky emission model well in this region and a barrier height of 0.59 eV was extracted as shown in Fig. C-2 (a).

On the contrary, for sample 2 (Al 2O3/W), F-P emission seems to dominate in this region.

This is logical, since for W, Schottky barrier becomes too large for Schottky emission to dominate. A barrier height of 0.356 eV was extracted from the curve fitting as shown in

Fig. C-2 (b). For sample 3 (HfO 2/Ti), it fits the F-P conduction mode extremely well. The calculated Schottky barrier turns out to be greater than the extracted F-P barrier height of

0.58 eV.

12.0 HfO 2_W Tunneling High Field 300K 11.5 350K 400K

) 11.0 HfO 2_W_F-P Emission High Field 2 10.1 (a) 10.0 10.5 9.9 ) (A/V 2 9.8 9.7 10.0 9.6 300K

-ln(J/E 9.5 350K -ln(J/E) (A/V*cm) 9.4 400K 9.5 9.3 1600 1800 2000 2200 2400 2600 1/2 9.0 E1/2 (V/cm) 1e-7 2e-7 3e-7 4e-7 5e-7 6e-7 7e-7 1/E (cm/V)

Figure C- 8 (a) Curve fitting for F-P emission [–ln(J/E) (A/Vcm) Vs E 1/2 (V/cm) 1/2 ] and 2 tunnelling [ –ln(J/E ) Vs 1/E] for HfO 2/W at high field at temperatures of 300 K, 350 K and 400 K.

73 26 300K 25 350K 400K 24

(b) 23

22 -ln(J/E) (A/V*cm) 21

20 200 300 400 500 600 700 800 900 1000

E1/2 (V/cm) 1/2

1/2 1/2 Figure C- 3 (b) F-P emission curve fit [–ln(J/E) (A/Vcm) vs E (V/cm) ] for Al 2O3/Ti sample at low field.

Therefore, at high electric fields F-P emission seems to dominate the conduction mode as shown in Fig. C-3 (a). From Fig. C-1(b), it can be interpreted that the current for sample 4 (HfO 2/W), is almost constant, but high relative to sample 1 and sample 3. The reason could be that, at high electric field the I-V curve fits well both in tunnelling and F-

P conduction mechanism. Again it is interesting to note from Fig.C-3 (a) that, the curves are not perfectly overlapping for tunnelling mechanism. This is due to the facts that charge conduction mode is not independent. Barrier heights of 0.24 eV and 0.27 eV were extracted for tunnelling and F-P emission respectively.

Now in case 2 at low electric field, for the sample 1, the extracted barrier height of 0.53 eV for F-P emission was lesser than that of Schottky-emission barrier height as shown in Fig.C- 3 (b). Therefore, F-P emission seems to dominate at low field for sample

1. Same as in case 1, the calculated Schottky barrier turns out to be greater than the

74 extracted F-P barrier height of 0.58 eV. Hence, from case 1 and case 2 for sample 2 and

sample 3, F-P emission dominates in both the regions as evident from Fig. C-2 (b).

However, for sample 4 at low field, Schottky emission acts as the dominant charge

conducting mode at low electric field. A barrier height of 0.49 eV was extracted from the

curve fitting as shown in Fig. C-4.

18

300K 350K 17 400K

)) 16 2 15

-ln(J/(AT 14

13

12 200 300 400 500 600 700 800 900 1000

E1/2 (V/cm) 1/2

Figure C-9 Curve fitting for Schottky emission [ –ln(J/(AT 2)) Vs E 1/2 (V/cm) 1/2 ] for HfO 2/W at low field at temperatures of 300 K, 350 K and 400 K.

Thereafter, the modeling of the data was done for all four samples using neural network to cover entire temperature points lying in the range of 300 K – 400 K for voltage ranging from-4 V to 4 V. Fig.C-5 shows the actual output current and neural model output current for all the samples. It can be easily observed that the model followed the experimental set of data very closely. Fig.C-5 demonstrated excellent modeling capabilities due to very low percentage of error. Once modeling is done, the current can be 75 accurately calculated using this model for any given temperature range which will be beneficial in reproducing the result without actually fabricating the device again. Hence, the model is cost effective and helps in speeding the entire process of fabrication and testing of devices. On the contrary, the already established equations like F-P emission, tunneling etc. require defining number of parameters like effective mass or barrier height, before calculating the output current. In this way, just by feeding the trained neural network with two inputs (voltage and temperature); the required output (current) can be easily established. This model in future would also help in comparing with different high- k or different metal gate based MOS capacitors as reproducing data will be very easy.

76

Figure C- 5 (a) Sample 1, (b) Sample 2, (c) Sample 3 and (d) Sample 4 shows the comparison of actual and modeled output current.

C.5 Conclusions

The series of experiments showed the method of conduction for different combinations of high-k dielectrics with both low (Ti: 4.3 eV) and mid-gap (W: 4.8 eV) work function metals. The mode of conduction consisted of a combination of F-P emission, Schottky emission, and tunneling, with each mechanism dominating according to the applied bias and temperature. At low temperatures tunneling remains as the dominant mode of conduction. However, at higher temperatures and in low field, mainly

F-P emission is dominating the mode of conduction except for HfO 2/W sample. For 77 Al 2O3 samples, in low field, the conduction mechanism is independent of electrodes being used unlike in high fields. However, for HfO 2 samples, the conduction mechanism is governed both by dielectrics and electrodes for the entire voltage range. Therefore, it is critical to fully understand the consequences in selecting the materials, as device performance could be drastically altered.

78 Appendix D

Fabrication of Graphene

Graphene is a building unit of graphite. It has extremely high carrier mobility exceeding 200,000 cm 2V-1s-1 [57]. The high transparency and flexibility of graphene due to its one atomic thickness can be extremely beneficial for electrodes. Graphene has already been in research to be used in resistive RAM technology. It has been demonstrated that graphene can lower the SET and RESET voltage of a RRAM when used as BE. In this section, the method of fabricating graphene using Metal-Organic

Chemical Vapour Deposition (MOCVD) has been discussed.

Following Fig.D-1 shows the steps involved in the process of fabricating graphene. Firstly, on a clean p- type Si substrate a minimum of 1000 Å of Ni was deposited in sputtering system. A thicker Ni would ensure a thicker layer of graphene to

be deposited on top of it. After deposition of Ni, the sample was loaded into the

MOCVD. There the temperature was elevated to 900 ºC and Ar: H 2 (150:125) gas mix was flown into the chamber for 20 mins. The flow rate of the mix was 195 sccm.

Thereafter, the flow of Ar was stopped and a CH 4: H2 mix of ratio1: 25 were flown into the chamber of MOCVD at the rate of 195 sccm at a constant temperature of 900 ºC.

79 After 20 mins, the temperature was gradually dropped at rate of 5 ºC/min until 600 ºC and the sample was gradually cooled in the presence of same CH 4 and H 2 gas mix.

Subsequently, the gas flow was stopped and only Ar was flown into the chamber for almost 70 min. The sample was then allowed to get cool down to room temperature overnight in the chamber. All the gases were turned off at this time.

Figure D- 1 Steps for fabrication of graphene.

80 1000

800 ]

600

400 Temperature (C) Temperature

200

1. Anneal(20mins) [Ar : H2= 150:125 sccm] Temp (C) 4. Inert Cool Down (68mins) in Ar (150 sccm) 2. Growth (20mins) [CH4 & H2 mix(1:25) = 195 sccm 0 3. Cool down andprecipitation (52mins) [CH4 & H2 mix(1:25) = 195 sccm] 020 40 5091 100 150 200 Time (mins)

Figure D- 2 Temperature vs. Time characteristics for fabrication of graphene in MOCVD.

81

Figure D- 3 Image of Graphene on Ni.

82 Appendix E

Simulation of GaSb Based MOSFET

Due to constant scaling of the dielectric (SiO 2) in the conventional MOSFET structure, huge increase in OFF state current is observed. Therefore SiO 2 is being replaced by high-K materials like HfO 2. However, the interface of HfO 2/Si cannot outshine the exceptional properties of SiO 2 and the SiO 2/Si (100) interface such as low- defect densities, thermal stability, and excellent uniformity over large area etc. Hence, Si are now being replaced by III-V materials which has very high carrier mobility.

Moreover, direct bandgaps in III–V materials which are unavailable in Si- and Ge-based materials, has provided enormous opportunities of fresh device architectures, consequently leading to high-performance integrated circuits. This work mainly focuses on building of p-mosfet using high-k material on III-V substrate (GaSb) [56].

83

Figure E- 1 Structure of p-MOS, Channel length= 100nm, Source/drain depth= 30 nm, tox= 10nm.

Models used to get the simulation results for GaSb based device are also used for

Si and Ge based devices, as Si and Ge are well known and well understood materials.

Figure E- 2 Drain Current (I d) vs. (V d) Drain Voltage for SHI Model for Si/HfO 2.

84

Figure E- 3 Drain Current (I d) vs. Drain Voltage (V d) for Watt Model for Si/HfO 2.

Figure E- 4 Current (Id) vs. Drain Voltage (Vd) for GaSb SHI model.

85

Figure E- 5 Drain Current (Id) vs. Drain Voltage (Vd) for GaSb Watt model.

Table E. 1 Current per unit length for Si, Ge and GaSb for two different models.

Material Id for Model 1 Id for Model 2 SURFMOB(Watt SHI (Shirahata Model) Model)

Si .005 A/µm .0028 A/µm

Ge .018 A/µm .012 A/µm

GaSb .02 A/µm .01 A/µm

The name of the simulator is Silvaco and the inversion layer models used from

ATLAS are SHIRAHATA model and WATT model. These models were again compared with a model in literature which is also an ATLAS model. The figures illustrate two different models for Si and GaSb. It is evident from both the models that, GaSb based

MOSFET is giving higher current as compared to Si based MOSFET. The models were

86 also compared with Ge based MOSFETs and from those results it can be concluded that

GaSb gives the highest current.

87