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Analysis of Various Memory Circuits Used in Digital VLSI

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Analysis of Various Memory Circuits Used in Digital VLSI International Journal of VLSI Design, Microelectronics and Embedded System Volume 4 Issue 1 Analysis of Various Memory Circuits Used In Digital VLSI Tanvi Upaskar, Ganesh Thorave, Prof. Sumita G*, Mayuresh Yerandekar, Siddhesh Mahadik K C College of Engineering and Management Studies Thane, India Corresponding author’s email id: [email protected]* DOI: http://doi.org/10.5281/zenodo.2652717 Abstract This paper presents comparison of semiconductor memory circuits such as volatile memories like SRAM, DRAM and non-volatile memories like ROM, PROM, EPROM, EEPROM, FLASH (NOR based & NAND based). This comparison is on the basis of some parameters including read speed, write speed, volatility, bits/cell, cell structure, cell density, power consumption, etc. In this paper we also focused on applications of those memory cells based on their characteristics. This paper presents the appropriate choice for selecting memory circuit with the read-write speed, capacity, power consumption. Keywords: Semiconductor memories, Volatility, Flash memory, memory cell, digital. INTRODUCTION non-volatile memory (which holds its data Semiconductor memory cells are capable even if the power is turned off). (See of storing large quantities of digital Figure:-1) information, essential to all digital systems. It is an essential element of VOLATILE MEMORY today's technical world. With the rapid Volatile memory needs power to maintain growth in the requirement for the stored information; it retains its semiconductor memories there have been contents while powered on but when the many types of memory that have emerged. power is interrupted, the stored data is There are basically two types of memory quickly lost. Volatile memory has many such as Volatile memory (which maintains uses including as primary storage its data while the device is powered) and 34 Page 34-44 © MANTECH PUBLICATIONS 2019. All Rights Reserved International Journal of VLSI Design, Microelectronics and Embedded System Volume 4 Issue 1 In addition to usually being faster than information, as it becomes unavailable on forms of mass storage such as a hard disk power-down.[4] drive, volatility can protect sensitive Figure:-1 A. Dynamic Random Access Memory Dynamic random-access memory is a type of random access semiconductor memory that stores each bit of data in a different capacitor within an integrated circuit. The capacitor can either be charged or discharged; these two states are used to represent the two values of a bit, conventionally called 0 and 1. Figure:-2 35 Page 34-44 © MANTECH PUBLICATIONS 2019. All Rights Reserved International Journal of VLSI Design, Microelectronics and Embedded System Volume 4 Issue 1 A typical 1-bit DRAM cell is shown in SRAM, but it is much more widely used. Figure 2. The capacitor CS stores the The advantage of DRAM is the structural charge for the cell. Transistor M1 gives the simplicity of its memory cells: only one R/W access to the cell. CB is the transistor and a capacitor are required. capacitance of the bit line per unit length. This allows DRAM to reach very high Memory cells are etched onto a silicon densities, making DRAM much cheaper wafer in an array of columns (bit lines) per bit. The transistors and capacitors used and rows (word lines). are extremely small; billions can fit on a single memory chip. Due to the dynamic The intersection of a bit line and word line nature of its memory cells, DRAM uses constitutes the address of the memory cell. relatively large amounts of power.[3] DRAM works by sending a charge through the appropriate column (CAS) to activate B. Static Random Access Memory the transistor at each bit in the column. Static random-access memory is a type of When writing, the row lines contain the semiconductor memory that uses bistable state the capacitor should take on. When latching circuitry (flip-flop) to store each reading, the sense amplifier determines the bit. SRAM exhibits data remanence, but it level of charge in the capacitor if it is more is still volatile in the conventional sense than 50%, it reads it as "1"; otherwise it that data is eventually lost when the reads it as "0". memory is not powered. One of the problems with this arrangement is that capacitors do not hold their charge indefinitely as there is some leakage across the capacitor. It will not be acceptable for the memory to lose its data, and to overcome this problem the data is periodically refreshed. The data is sensed and written and it then ensures that any leakage is overcome, and the data is re- instated. Due to its need of a system to Fig. 2 – 6T SRAM cell refreshing, DRAM has more complexed circuitry and timing requirements than 36 Page 34-44 © MANTECH PUBLICATIONS 2019. All Rights Reserved International Journal of VLSI Design, Microelectronics and Embedded System Volume 4 Issue 1 6T-SRAM cell is shown in fig 2. SRAM needed to be refreshed and due to their takes 6 transistors to store a 1 bit. It has latching arrangement. Due to its high three input ports (BL, BL bar, WL) and speed the SRAM is also used as the cache two output ports (Q,Qbar). In Fig. M5 and memory and also the main memory in the M6 are access transistors, M2 and M4 pull servers for providing the best performance up, M1 and M3 are pull down transistors. to the users.[3] SRAM has basic three operations. NON-VOLATILE MEMORY Hold operation: For Hold Operation both A drawback of volatile memory structures access transistors must be turned OFF such as DRAM and SRAM is that the (M5=M6=0). Due to presence of latching stored data is lost in the absence power element SRAM hold its state. supply. To overcome this problem, various types of non-volatile memory have been Read Operation: For Read operation both proposed. Non-volatile memory (NVM) is bit lines (BL, BL bar) must be precharged a type of computer memory that has the to VDD and access transistors must be turn ability to hold saved data even if the power on (M5=M6=1). Based data value stores is turned off. Unlike volatile memory, any one of bit line is discharge and the NVM does not require its memory data to voltage difference between two bit lines is be periodically refreshed. It is commonly sensed by sense amplifier and we are able used for secondary storage or long-term to detect what is present in memory. consistent storage. Non-volatile memory is highly popular among digital media; it is Write Operation: The data which we want widely used in memory chips for USB to write in the memory is given to bit line memory sticks and digital cameras. Non- and access transistors are turn volatile memory eradicates the need for on(M5=M6=1) and we are able to write relatively slow types of secondary storage the data. systems, including hard disks.[4] In one memory bit there are 6 transistors Read Only Memory of SRAM which makes the SRAM bulky. Read-only memory (ROM), also known as It needs the more space for the storage firmware, is an integrated circuit purpose. the speed of the SRAM is much programmed with specific data when it is faster than the DRAM as they are not manufactured. ROM chips are not only 37 Page 34-44 © MANTECH PUBLICATIONS 2019. All Rights Reserved International Journal of VLSI Design, Microelectronics and Embedded System Volume 4 Issue 1 used in computers, but in most other B. Programmable Read Only Memory electronic items as well. ROM-memory PROM is read-only memory that can be does not allow for deletion; it cannot be modified only once by a user. The user overwritten by the user's program buys a blank PROM and enters the desired commands. Therefore, all programs and contents using a PROM program. Inside data are supposed to be in the ROM to be the PROM chip, there are small fuses installed through the production process. which are burnt open during programming. This is done using a "ROM-Mask" which It can be programmed only once and is not contains all the data and is used during the erasable.[2] processing of the silicon chip. C. Erasable Programmable Read Only Memory An EPROM is erased by shining ultraviolet light on the cells through a transparent window in the package. The UV radiation renders the oxide slightly conductive by direct generation of an electron-hole pair in the material. The erasure process is slow and can take from Fig. 3- ROM array seconds to several minutes, depending on the intensity of the UV source. At first sight, the limitation of the Programming takes several (5-10) irreversible writing process seems to be a microseconds / word. Another problem disadvantage. But it also discourages with the process is limited endurance, that potential attackers to modify the program is, the number of erase / program cycles code on less secure chip cards. are generally limited to maximum of 1000, mainly due to UV erase procedure. The two different types of implementation Reliability is also an issue. The device of ROM array are – threshold may vary with repeated NOR based ROM array programming cycles. Most EPROM NAND based ROM array memories therefore contain an on-chip circuitry to control the value of the thresholds within a specified range during 38 Page 34-44 © MANTECH PUBLICATIONS 2019. All Rights Reserved International Journal of VLSI Design, Microelectronics and Embedded System Volume 4 Issue 1 programming. Finally, the injection always device that can be implemented with fewer entails a large channel current, as high as standards in cell design. The more 0.5mA at a control gate voltage of 12.5V.
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