A New Embedded M easurement Structure for eDRAM Capacitor

1&2 1 2 L.Lopez J.M. Portal D.Née

1 2 L2MP-Polytech-UMR CNRS 6137 ST-Microelectronics IM T - Technopôle de Château Gombert ZI de Rousset BP 2 F-13451 Marseille, France F-13106 Rousset, France portal@ polytech.univ-mrs.fr didier.nee@ st.com Tel:(33)-491-054-787 Tel:(33)-442-688-815

Abstract structure is switch off in the standard operation mode and the plate polarization is fixed to V /2 using the STD DD The embedded DRAM (eDRAM) is more and more used in transistor. During the test mode, the STD transistor is System On Chip (SOC). The integration of the DRAM switched off. The Select transistors allow the memory capacito r process into a logic process is challenging to array to connect each bit-line to the bit-line input named get sati sfactory yields. The specific process of DRAM INBLi. These transistors are named SBLi. capacitor and the low capacitance value (~30fF) of this eDRAM Macro-cellarray Measurement structure device induce problems of process monitoring and failure V INBL1 IN DD analysis. We propose a new test structure to measure the BL1 BL2 I PU capacita nce value of each DRAM cell capacitor in a REFP SBL1 SBL2 DRAM array. This concept has been validated by OUT LEC simulati on on a 0.18µm eDRAM technology. IN W L1 REF C PRG 1. Introduction m FP

The major challenge of eDRAM technologies remains STD Plate polarization W L V 2 DD the significant increase in the fabrication process 2 complex ity with its associated control problems. To face this m ajor challenge, Built-In-Self-Repair (BISR) Figure 1: eDRAM M acro-Cell with capacitor extraction structure connected to the plate node techniqu es are extensively developed. Complementary to these B ISR techniques, some failure analysis methods have been proposed [1,2], knowing that memories offer The measurement structure itself is composed of two specific properties of regularity. But none of these select transistors controlled respectively by the signal LEC methods targets the parametric values of eDRAM such as and PRG, one reference transistor REF with an input capacito r value. To enhance the failure analysis efficiency, capacitor CREF and one programmable current reference it appea rs that embedded capacitor measurement function named IREFP. The sensing function is composed of two inverters, which drive the digital output OUT. is a ve ry relevant feature to have information on the specific eDRAM process steps. Thus, the fundamental The measurement procedure is based on charge sharing discussio n of this paper is to present an embedded between the capacitor under measurement (Cm) and the capacito r measurement function for eDRAM, and the reference capacitor (CREF). The reference capacitor is the associate d diagnosis methodology improvement. input capacitor of the n-MOSFET used for the analog to digital conversion. 2. Capacitor measurement structure The measurement flow is composed of five steps of 10 ns. The first step is the discharge off all the capacitor in

As illustrated Figure 1, the proposed measurement the macro-cell and in the measurement structure. To do so, structure is connected to the plate node of the macro-cell all the world lines are selected (DRAM transistors ON). (to simp lify the scheme, only four cells of the macro-cell The n-MOSFET controlled by LEC is also turned on. All are repr esented) in order to delete capacitance noise the capacitors are then grounded on their both nodes: PRG is conducting and by applying 0V on the input IN, the measure ment due to the parasitic bit-line capacitance. This

1530-1591/05 $20.00 © 2005 IEEE plate node is grounded; All SBLi are conducting and by the same way than the digital one, with signatures applying 0V to each bitline inputs (INBLi are grounded), all categorization depending on the capacitor values. This the bit line nodes are grounded. signatures categorization might be very useful to The second step of the measurement flow consists in characterize process and defect impact on the array. charging the capacitor Cm that is controlled by W L1, ) 2 V (

without charging all the others capacitors in the macro- l a

i OUT (a) t 1 cell. This operation is performed by turning off all the n e t VDS word lines except W L1, and by raising all the bit-lines to o P 0 VDD except the one that is connected to Cm that remains 0 10 20 30 40 50 grounded. LEC is grounded to unselect CREF and applying Time (ns)

VDD on the input IN performs the charge of Cm. At the end ) 2 of the step, PRG is turned off. V (

l a

The third step is straightforward and consists in turning i OUT t 1 n

(b) e off the bit-line selection signal SBLi except the one of Cm to t VDS o put on high impedance state all the other capacitors of the P 0 macro-cell. In this configuration, the capacitor Cm is the 0 10 20 30 40 50 Time (ns) only one still active on the plate node. The fourth step consists in turning on the LEC signal. A Figure 2: Capacitor extraction simulation results : charge sharing is made between Cm and CREF. Thus, the (a) Cm = 20 fF; (b)Cm = 40 fF) potential VGS is a function of Cm. The last step of the measurement flow is to get a 20 numerical data of VGS and thus, of Cm. This step is based

on a current injection through the transistor REF. The

_ 15 _ programmable current source IREFP has been designed to p e t s

get a numerical linear ramp of current with 20 steps t

n 10 e controlled by a shift register [3]. The current rises by step r r u and the drain potential rises too. W hen V is larger than C DS 5 VDD/2, the inverter connected to the drain of REF switches from a logical 1 to a logical 0. Thus, the output (OUT) 0 switches from a logical 0 to a logical 1. The stored value 0 10 20 30 40 50 60 in the shift register that is used to control the current ramp, Cm (fF) is then extracted on the output switches, and gives a digital image of the capacitor‘s value. Figure 3: Abacus to define the equivalence between This structure has been validated by simulation using a current step and capacitor value. design kit of the 0.18µm eDRAM technology from ST- Microelectronics. The Figure 2 presents simulation results 3. Conclusion with Cm set to 30fF. The capacitance variation induces a variation of time of the OUT switch and so, a variation of In this paper, an embedded test structure is developed the current steps of IREFP. The conversion of the register to extract the capacitor values of each cell in the array value to the image of the capacitor one is straightforward. during the functional test. The capacitor values are The switch of the output OUT occurs for different current extracted in a digital format that enables a diagnosis steps depending on the capacitor value. The register value methodology based on analog bitmapping complementary gives directly the current step. This current value is used to the classical digital bitmapping. Thus, the diagnosis of as an image of the capacitor value, thus a specification failure of each cell in the array is improved. window is defined in current. Using the abacus obtained from a set of simulation, Figure 3 shows the current steps 4. Reference versus the capacitor values. W ith our design, the test structure is scaled in a range of eDRAM capacitor of [1] D. Lepejian et al., “An Automated Failure Analysis (AFA) 10fF-55fF with an accuracy of 6%. If the number of Methodology for Repeated Structures“, Proc. 12th IEEE VLSI current step is 0, three diagnoses are possible: The Test Symposium, pp.319-324., 1994. capacitor value is under 10fF; the capacitor is shorted; the [2] A. Jee et al., —Carafe: A Software Tool for Failure Analysis“, capacitor behaves like an open. If the number of current Proc. Of Int‘l Symp. On Testing and Failure Analysis, pp.143- step is 20, the capacitor value is equal or superior to 55fF. 149, 1993. The main idea, when extracting the capacitor value, is to [3] J. M. Portal et al., —EEPROM Memory Diagnosis Based on build an Analog Bitmap of the capacitor values of the cells Threshold Current Extraction“, Proceedings of the IEEE Design of Circuits and Integrated Systems, pp.133-139, 2003. in the memory array. This analog bitmap can be treated in