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A New Embedded Measurement Structure for Edram Capacitor

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A New Embedded Measurement Structure for Edram Capacitor A New Embedded M easurement Structure for eDRAM Capacitor 1:22.2ope. 1J.M. Portal 2D.1ée 1 L2M,-,olytech-.MR CNRS 0131 2 ST-Microelectronics 2MT - Technop3le de Ch4teau 5ombert 62 de Rousset 7, 2 F-13851 Marseille, France F-13100 Rousset, France portal; polytech.univ-mrs.fr didier.nee; st.com Tel:(33)-891-058-181 Tel:(33)-882-088-815 Abstract structure is switch off in the standard operation mode and the plate polari.ation is fixed to /DD02 using the STD The embedded DRAM (eDRAM) is more and more used in transistor. During the test mode, the STD transistor is System On Chip (SOC). The integration of the DRAM switched off. The Select transistors allow the memory capacito r process into a logic process is challenging to array to connect each bit line to the bit line input named get sati sfactory yields. The specific process of DRAM I1B2i. These transistors are named SB2i. capacitor and the lo capacitance value ("30fF) of this eDRAM Macro cellarray Measurement structure device induce problems of process monitoring and failure / I1B21 I1 DD analysis. We propose a ne test structure to measure the B21 B22 I P7 capacita nce value of each DRAM cell capacitor in a RE-P SB21 SB22 DRAM array. This concept has been validated by O7T 2EC simulati on on a 0.18)m eDRAM technology. I1 W 21 REF C PR5 1. Introduction m -P The major challenge of eDRAM technologies remains STD Plate polari.ation W 2 / 2 DD the significant increase in the fabrication process 2 complex ity with its associated control problems. To face Figure 1 eDRAM M acro-Cell with capacitor this m ajor challenge, Built In Self Repair (BISR) extraction structure connected to the plate node techniqu es are extensively developed. Complementary to these BISR techniques, some failure analysis methods have been proposed (1,2+, ,nowing that memories offer The measurement structure itself is composed of two specific properties of regularity. But none of these select transistors controlled respectively by the signal 2EC methods targets the parametric values of eDRAM such as and PR5, one reference transistor RE- with an input capacito r value. To enhance the failure analysis efficiency, capacitor CRE- and one programmable current reference named I . The sensing function is composed of two it appea rs that embedded capacitor measurement function RE-P is a very relevant feature to have information on the inverters, which drive the digital output O7T. specific eDRAM process steps. Thus, the fundamental The measurement procedure is based on charge sharing discussio n of this paper is to present an embedded between the capacitor under measurement (Cm) and the capacito r measurement function for eDRAM, and the reference capacitor (CRE-). The reference capacitor is the associate d diagnosis methodology improvement. input capacitor of the n MOS-ET used for the analog to digital conversion. The measurement flow is composed of five steps of 10 2. Ca pacitor measurement structure ns. The first step is the discharge off all the capacitor in As illustrated -igure 1, the proposed measurement the macro cell and in the measurement structure. To do so, structure is connected to the plate node of the macro cell all the world lines are selected (DRAM transistors O1). (to simp lify the scheme, only four cells of the macro cell The n MOS-ET controlled by 2EC is also turned on. All the capacitors are then grounded on their both nodes9 PR5 are repr esented) in order to delete capacitance noise is conducting and by applying 0/ on the input I1, the measure ment due to the parasitic bit line capacitance. This 1530-1591/05 $20.00 © 2005 IEEE plate node is grounded; All SB2i are conducting and by the same way than the digital one, with signatures applying 0/ to each bitline inputs (I1B2i are grounded), all categori.ation depending on the capacitor values. This the bit line nodes are grounded. signatures categori.ation might be very useful to The second step of the measurement flow consists in characteri.e process and defect impact on the array. charging the capacitor Cm that is controlled by W 21, ) 2 / ( without charging all the others capacitors in the macro l a i O7T (a) t 1 cell. This operation is performed by turning off all the n e t /DS word lines except W 21, and by raising all the bit lines to o P 0 /DD except the one that is connected to Cm that remains 0 10 20 30 40 C0 grounded. 2EC is grounded to unselect CRE- and applying Time (ns) /DD on the input I1 performs the charge of Cm. At the end ) 2 of the step, PR5 is turned off. / ( l a The third step is straightforward and consists in turning i O7T t 1 n (b) e off the bit line selection signal SB2i except the one of Cm to t /DS o put on high impedance state all the other capacitors of the P 0 macro cell. In this configuration, the capacitor Cm is the 0 10 20 30 40 C0 Time (ns) only one still active on the plate node. The fourth step consists in turning on the 2EC signal. A Figure 2 Capacitor extraction simulation results charge sharing is made between Cm and CRE-. Thus, the (a) Cm ' 20 fF) (b)Cm ' 40 fF) potential /5S is a function of Cm. The last step of the measurement flow is to get a 20 numerical data of /5S and thus, of Cm. This step is based on a current injection through the transistor RE-. The _ 1C _ programmable current source IRE-P has been designed to p e t s get a numerical linear ramp of current with 20 steps t n 10 e controlled by a shift register (3+. The current rises by step r r u and the drain potential rises too. W hen / is larger than C DS C /DD02, the inverter connected to the drain of RE- switches from a logical 1 to a logical 0. Thus, the output (O7T) 0 switches from a logical 0 to a logical 1. The stored value 0 10 20 30 40 C0 D0 in the shift register that is used to control the current ramp, Cm (f-) is then extracted on the output switches, and gives a digital image of the capacitor@s value. Figure 3 Abacus to define the e,uivalence between This structure has been validated by simulation using a current step and capacitor value. design ,it of the 0.1ABm eDRAM technology from ST Microelectronics. The -igure 2 presents simulation results 3. Conclusion with Cm set to 30f-. The capacitance variation induces a variation of time of the O7T switch and so, a variation of In this paper, an embedded test structure is developed the current steps of IRE-P. The conversion of the register to extract the capacitor values of each cell in the array value to the image of the capacitor one is straightforward. during the functional test. The capacitor values are The switch of the output O7T occurs for different current extracted in a digital format that enables a diagnosis steps depending on the capacitor value. The register value methodology based on analog bitmapping complementary gives directly the current step. This current value is used to the classical digital bitmapping. Thus, the diagnosis of as an image of the capacitor value, thus a specification failure of each cell in the array is improved. window is defined in current. 7sing the abacus obtained from a set of simulation, -igure 3 shows the current steps 4. Reference versus the capacitor values. W ith our design, the test structure is scaled in a range of eDRAM capacitor of (1+ D. 2epejian et al., HAn Automated -ailure Analysis (A-A) 10f- CCf- with an accuracy of DE. If the number of Methodology for Repeated StructuresH, Proc. 12th IEEE /2SI current step is 0, three diagnoses are possible9 The Test Symposium, pp.31I 324., 1II4. capacitor value is under 10f-; the capacitor is shorted; the (2+ A. Jee et al., JCarafe9 A Software Tool for -ailure AnalysisH, capacitor behaves li,e an open. If the number of current Proc. Of Int@l Symp. On Testing and -ailure Analysis, pp.143 step is 20, the capacitor value is equal or superior to CCf-. 14I, 1II3. The main idea, when extracting the capacitor value, is to (3+ J. M. Portal et al., JEEPROM Memory Diagnosis Based on build an Analog Bitmap of the capacitor values of the cells Threshold Current ExtractionH, Proceedings of the IEEE Design of Circuits and Integrated Systems, pp.133 13I, 2003. in the memory array. This analog bitmap can be treated in .
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