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ECE 274 - Digital Logic 5.6 Lecture 18 Memory Components

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ECE 274 - Digital Logic 5.6 Lecture 18 Memory Components ECE 274 - Digital Logic 5.6 Lecture 18 Memory Components Register-transfer level Lecture 18 – Memory design instantiates datapath components to create RAM/ROM/EPROM/EEPROM/FLASH datapath, controlled by a controller A few more components are often used outside the M words controller and datapath MxN memory M words, N bits wide each N-bits wide each Several varieties of memory, which we now M×Nmemory introduce 1 2 Random Access Memory (RAM) RAM Internal Structure 32 RAM – Readable and writable memory 32 32 data W_data R_data 10 wdata(N-1) wdata(N-2)wdata0 addr Let A = log2M “Random access memory” 1024x32 4 4 rw bit storage W_addr R_addr RAM word Strange name – Created several decades ago to en enable block d0 (aka “cell”) contrast with sequentially-accessed storage like W_en R_en tape drives 16×32 addr0 a0 word a1 register file addr1 AxM d1 Logically same as register file – Memory with decoder Register file from Chpt. 4 adr address inputs, data inputs/outputs, and control addr(A-1) a(A-1) data cell RAM usually just one port; register file usually word word d(M-1) two or more clk e enableenable 32 rw data RAM vs. register file en data rw to all cells 10 RAM typically larger than roughly 512 or 1024 addr RAM cell words 1024× 32 rdata(N-1) rdata(N-2) rdata0 rw RA M RAM typically stores bits using a bit storage en approach that is more efficient than a flip flop Similar internal structure as register file RAM typically implemented on a chip in a square Decoder enables appropriate word based on address rather than rectangular shape – keeps longest RAM block symbol inputs wires (hence delay) short rw controls whether cell is written or read Let’s see what’s inside each RAM cell 3 4 Static RAM (SRAM) Static RAM (SRAM) SRAM cell wdata(N-1) wdat a(N-2) wdata0 wdata(N-1) wdat a(N-2) wdata0 32 Let A = log2 M 32 Let A = log2 M data word bit storage data data’ data word bit storage block block ,, 10 enable ,, ,, 10 enable ,, addr d0 (aka cell ) cell addr d0 (aka cell ) 1024x32 addr0 a0 word d d’ 1024x32 addr0 a0 word rw a1 rw a1 RAM addr1 A ⋅ M d1 RAM addr1 A ⋅ M d1 decoder decoder en addr data cell en addr data cell addr(A-1) a(A-1) a addr(A-1) a(A-1) word word word word d(M-1) d(M-1) clk e enable enable clk e enable enable rw data rw data en en rw rw to all cells word 0 to all cells SRAM cell rdata(N-1) rdat a(N-2) rdata0 enable “Static” RAM cell rdata(N-1) rdat a(N-2) rdata0 data data’ “Static” RAM cell SRAM cell Reading this cell 11 d 6 transistors (recall inverter is 2 transistors) data data’ Somewhat trickier 1 0 When rw set to read, the RAM logic sets Writing this cell d both data and data’ to 1 1 0 word enable input comes from decoder a a 1 0 The stored bit d will pull either the left line When 0, value d loops around inverters 1<1 or the right bit down slightly below 1 word 1 That loop is where a bit stays stored enable “Sense amplifiers” detect which side is When 1, the data bit value enters the loop word 1 slightly pulled down To sense amplifiers data is the bit to be stored in this cell enable The electrical description of SRAM is really data’ enters on other side data data’ beyond our scope – just general idea here, Example shows a “1” being written into cell cell d d’ mainly to contrast with DRAM... 1 0 a word 0 enable 5 6 Dynamic RAM (DRAM) Comparing Memory Types wdata(N-1) wdat a(N-2) wdata0 32 Let A = log2 M data word bit storage Register file block MxN Memory 10 enable ,, ,, addr d0 (aka cell ) Fastest implemented as a: 1024x32 addr0 a0 word rw a1 RAM addr1 A ⋅ M d1 register decoder addr But biggest size en cell addr(A-1) a(A-1) data file word word d(M-1) SRAM clk e enable enable rw data en rw to all cells DRAM cell Fast SRAM rdata(N-1) rdat a(N-2) rdata0 data More compact than register file “Dynamic” RAM cell DRAM cell DRAM 1 transistor (rather than 6) word Slowest enable Relies on large capacitor to store bit d And refreshing takes time capacitor Size comparison for same Write: Transistor conducts, data voltage But very compact slowly number of bits (not to scale) level gets stored on top plate of capacitor discharging Use register file for small items, Read: Just look at value of d (a) SRAM for large items, and DRAM Problem: Capacitor discharges over time for huge items data Must “refresh” regularly, by reading d and Note: DRAM’s big capacitor then writing it right back enable requires a special chip design discharges d process, so DRAM is often a (b) separate chip 7 8 Reading and Writing a RAM RAM Example: Digital Sound Recorder 4096⋅ 16 clk clk 1 2 3 RAM addr 9913 addr valid setup data addr rw en time wire 16 data 500 999 Z 500 valid analog-t o- digital-to- data hold Z 500 12 digital ad_buf Ra Rr w Re n analog wire time microphone converter converter rw 1 means write rw setup ad_ldprocessor da_ld time en access RAM[9] RAM[13] time now equals 500 now equals 999 speaker Behavior Writing (b) Record: Digitize sound, store as series of 4096 12-bit digital values in Put address on addr lines, data on data lines, set rw=1, en=1 RAM Reading We’ll use a 4096x16 RAM (12-bit wide RAM not common) Set addr and en lines, but put nothing (Z) on data lines, set rw=0 Play back later Data will appear on data lines Common behavior in telephone answering machine, toys, voice recorders Don’t forget to obey setup and hold times To record, processor should read a-to-d, store read values into In short – keep inputs stable before and after a clock edge successive RAM words To play, processor should read successive RAM words and enable d-to-a 9 10 RAM Example: Digital Sound Recorder RAM Example: Digital Sound Recorder 4096x16 4096x16 RTL design of processor RAM Now create play behavior RAM data bus Create high-level state Use local register a again, machine 16 create state machine that 16 analog-to- digital-to- analog-to- digital-to- 12 counts from 0 to 4095 again 12 Begin with the record digital ad_buf Ra Rw Ren analog digital ad_buf Ra Rw Ren analog converter converter For each a converter converter behavior ad_ldprocessor da_ld ad_ldprocessor da_ld Read RAM Keep local register a Write to digital-to-analog Stores current address, Record behavior conv. ranges from 0 to 4095 (thus Play behavior Local register: a (12 bits) Note: Must write d-to-a one need 12 bits) Local register: a (12 bits) a<4095 cycle after reading RAM, when Create state machine that S T the read data is available on a<4095 the data bus V W counts from 0 to 4095 using a=0 ad_ld=1 a a ad_buf=1 a=0 ad_buf=0 a The record and play state Ra=a U Ra=a Rrw=0 X For each a Rrw=1 a=a+1 machines would be parts of a Ren=1 Ren=1 Read analog-to-digital larger state machine controlled da_ld=1 a=a+1 conv. a=4095 by signals that determine ad_ld=1, ad_buf=1 when to record or play a=4095 Write to RAM at address a Ra=a, Rrw=1, Ren=1 11 12 Read-Only Memory – ROM Read-Only Memory – ROM 32 32 data Memory that can only be read from, not data 10 1024x32 10 addr Let A = log M written to addr ROM 2 1024× 32 en word bit storage Data lines are output only rw RAM enable block No need for rw input en ROM block symbol d0 (aka “cell”) a0 Advantages over RAM addr0 word addr1 a1 RAM block symbol AxM d1 Compact: May be smaller decoder adr data Nonvolatile: Saves bits even if power addr(A-1) a(A-1) supply is turned off 32 word word e d(M-1) enableenable Speed: May be faster (especially than data clk data 10 1024x32 en DRAM) addr ROM Low power: Doesn’t need power supply to en save bits, so can extend battery life rdata(N-1) rdata(N-2) rdata0 ROM cell Choose ROM over RAM if stored data won’t ROM block symbol change (or won’t change often) Internal logical structure similar to RAM, without the data For example, a table of Celsius to input lines Fahrenheit conversions in a digital thermometer 13 14 ROM Types ROM Types If a ROM can only be read, Let A = log2 M Let A = log2 M word bit storage Fuse-Based Programmable word bit storage block block ,, enable ,, ,, enable ,, d0 (a cell ) d0 (a cell ) how are the stored bits stored addr0 a0 word addr0 a0 word a1 a1 addr1 A ⋅ M d1 ROM addr1 A ⋅ M d1 decoder decoder addr data addr data in the first place? addr(A-1) a(A-1) cell addr(A-1) a(A-1) cell word word word word e d(M-1) enable enable Each cell has a fuse e d(M-1) enable enable data data en en Storing bits in a ROM known as data(N-1) data(N-2) data0 A special device, known as a data(N-1) data(N-2) data0 programming programmer, blows certain fuses Several methods (using higher-than-normal voltage) 1 data line0 data line 1 data line1 data line Mask-programmed ROM Those cells will be read as 0s Bits are hardwired as 0s or 1s cell cell (involving some special electronics) cell cell during chip manufacturing a word Cells with unblown fuses will be read word 2-bit word on right stores “10” enable as 1s enable word enable (from decoder) 2-bit word on right stores “10” simply passes the hardwired value fuse blown fuse through transistor Also known as One-Time Programmable (OTP) ROM Notice how compact, and fast, this memory would be 15 16 ROM Types ROM Types Erasable Programmable ROM Let A = log2 M Electronically-Erasable Programmable ROM word bit storage block enable ,, ,, d0 (a cell ) (EEPROM) (EPROM) addr0 a0 word a1 addr1 A ⋅ M d1 decoder addr data Similar to EPROM Uses “floating-gate transistor” in each addr(A-1) a(A-1) cell word word e d(M-1) enable enable data Uses floating-gate transistor, electronic programming cell en to trap electrons in certain cells Special programmer device uses higher- data(N-1)
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