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Lecture 23. Read-Only Memories & Programmable Logic Arrays

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Lecture 23. Read-Only Memories & Programmable Logic Arrays EE 280 Introduction to Digital Logic Design Lecture 23. Read-Only Memories & Programmable Logic Arrays EE280 Lecture 23 23 - 1 Read-Only Memories Memory is like an array of mailboxes (registries of binary data) A stored array of binary data which can be read only, but not changed In general, 2n × m ROM ≡ I/P lines ≡ O/P lines ≡ words* each bits long For each combination of inputs on the n input lines, the corresponding pattern of 0’s and 1’s (a word) is generated on the m output lines - typical sizes range from (32 words x 4 bits) to (512K words x 8 bits) or larger EE280 Lecture 23 23 - 2 1 ROM Realization of Logic Functions A B C F0 F1 F2 F3 0 0 0 A ROM 0 0 1 B 8 words 0 1 0 C x 4 bits 0 1 1 1 0 0 1 0 1 F F F F 1 1 0 0 1 2 3 1 1 1 a. Block diagram b. Truth table for ROM F0 = = A'B' + AC‘ F1 = = B + AC‘ F2 = = A'B' + BC‘ F3 = = AC + B EE280 Lecture 23 23 - 3 ROM Realization of Logic Functions ROM consists of a decoder and a memory array. When a particular input sequence is applied to the n decoder inputs, exactly one of the 2n outputs is set to 1. This output line selects one of the words in the memory array. decoder outputs mi are consecutive minterms ROM outputs Fi are generated by ORing selected minterms Switching elements pass 1 to output, otherwise resistors at the top set output to 0 EE280 Lecture 23 23 - 4 2 Code Conversion Network using ROM The ROM realizes conversion between BDC (8421) code and Excess-3 code Decimal Input Output digit ABCD W X Y Z 0 0000 0 0 1 1 A W 1 0001 0 1 0 0 B X 2 0010 0 1 0 1 ROM C Y 3 0011 0 1 1 0 4 0100 0 1 1 1 D Z 5 0101 1 0 0 0 6 0110 1 0 0 1 7 0111 1 0 1 0 8 1000 1 0 1 1 9 1001 1 1 0 0 X 1010 X X X X X 1011 X X X X EE280 Lecture 23 23 - 5 Code Conversion Network using ROM m0 m1 m2 m3 m4 m5 A m6 B m7 m C 8 m9 D DECODER 4-line to 16-line 16-line 4-line to m10 m11 m12 m13 m14 m15 EE280 Lecture 23 23 - 6 3 ROM Realization of Logic Functions Internal structure of a 128 x 1 ROM using two-dimensional decoding - rectangular form reduces complexity and increases flexibility - note the inverted decoder, and +5V on ROM output lines EE280 Lecture 23 23 - 7 ROM Types Mask-programmable (ROM) - Permanent programming done at fabrication time - Diodes blown at factory as per customer order - Very expensive and therefore feasible only for large quantity orders Programmable ROM (PROM) - User programmed after purchase, called field-programmable ROM (FPROM) - Reprogrammable by user, erasable by UV emission, called erasable, programmable ROM (EPROM) Electrically erasable, programmable ROM (EEPROM) - User can erase individual words; switching elements can be enabled/disabled - Can be erased and reprogrammed limited number of times, typically 100 to 1000 times EE280 Lecture 23 23 - 8 4 Programmable Logic Arrays (PLA) Performs the same basic functions as ROM ROM - the inner organization is different - decoder is replaced with an AND array and realizes selected product terms of the input variables - output functions are realized by OR array that Ors together the product terms - PLA implements SOP expressions, while PLA ROM implements a truth table EE280 Lecture 23 23 - 9 Programmable Logic Arrays (PLA) PLA with n I/P's and m O/P's can realize PLA is used instead of ROM when n is large, and number of terms is not large e.g., if n = 16 EE280 Lecture 23 23 - 10 5 Programmable Logic Arrays (PLA) PLA can be represented by a PLA table Inputs Outputs Product terms A B C f1 f2 f3 f4 A’C’ 0 – 0 1 0 1 0 A B’ 1 0 – 0 0 0 1 A C 1 – 1 1 1 0 0 B’C –0 1 0 1 1 1 EE280 Lecture 23 23 - 11 PLA - Example Design PLA that implements following functions a’bd abd … EE280 Lecture 23 23 - 12 6 Programmable Arrays Logic (PAL) The PAL has many features in common with PROM and PLA The PAL is a special case of the of the PLA in which the array is programmable and the array is fixed by the manufacturer Because for PAL only AND array is programmable it is cheaper than PLA; it is also easier to program and therefore often used A’ A B’ B C’ C AND gates with 6 inputs (A’, A, B’, B, C’, C) EE280 Lecture 23 23 - 13 7.
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