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The Design and Implementation of a Universal EPROM Programmer Nathan David Department of Electronic Engineering, Faculty of Engineering, University of Nigeria, Nsukka

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The Design and Implementation of a Universal EPROM Programmer Nathan David Department of Electronic Engineering, Faculty of Engineering, University of Nigeria, Nsukka International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 2 Issue 9, September - 2013 The Design and Implementation of a Universal EPROM Programmer Nathan David Department of Electronic Engineering, Faculty of Engineering, University of Nigeria, Nsukka. Nnamani, Uchenna H Department of Electronic Engineering, Faculty of Engineering, University of Nigeria, Nsukka. Odoeze, Jideofor A.H Department of Electrical and Electronic Engineering Federal Science and Technical College, Yaba ABSTRACT usually rare thus the relevance of this work.Gibilisco [1] defined Since the discovery of transistors and consequently the digital memory as the section of a digital computer that records and integrated circuits used in digital system, memory devices have holds data until it is necessary. In computer systems, ideally been used extensively and unavoidably in most digital memory device is group into different categories using the applications. The embedded and non-embedded system such as following parameter which is commonly referred to as Memory the microprocessor and microcontroller systems respectively are Hierarchy. one of those systems that make extensive use of memory devices These parameters include Speed, Size, Power Consumption, both the volatile and non-volatile memories for temporal data or Volatility and Cost. variable storage and permanent instruction storage respectively. REGISTERS The non-volatile memory is used in the state of art CD and DVD At the very top of this memory hierarchy is registers (also playback sets and computer systems as a repository for the low- sometimes referred to as processor registers), which consist of level system information such as the BIOS. A more reliable and an extremely small amount of very fast (i.e., much faster than efficient digital circuit miniaturization such as the sequential the main memory) memory cells that are built directly into the circuit is best implemented using the non-volatile memories CPU. Their purpose is to speed up the execution of the CPU, and particularly the EPROM which has been programmed to thus of programs, by providing quick access to commonly used accomplish such sequential functions. It is in light of this that we values, generally those in the midst of a calculation. Registers have taken up the challenge to Design and Implement a are usually implemented using array of SRAM (i.e., Static Universal EPROM Programmer that complies with the Joint RAM) cells. Electron Device Engineering Council (JEDEC) Specification.IJERT ItIJERT CACHE is microprocessor based with a user-friendly GUI that is Below the registers in the memory hierarchy is the cache supported by any Microsoft Windows Operating System memory, it is a small amount of high-speed memory, usually platform. It incorporates a software driver with Chip with a memory cycle time comparable to the time required by Identification Algorithm (CIA) that has the capability of the CPU to fetch one instruction. Whose purpose is to reduce the identifying any specific EPROM and automatically selects the mismatch in speeds between the CPU and RAM because the optimal programming algorithm for that particular EPROM. The modern processors have clock rates of several gigahertz (billions software interacts with the external hardware via the computer of cycles per second), whereas RAM chips have access times parallel port using the bi-directional protocol of the Line Printer measured in megahertz (millions of cycles per second). (LPT) interface. The hardware and the software is designed to The amount of information which is replaces at one time in the support a large memory addressing capability which is about cache is called theline sizefor the cache. This is normally the 65kb more than most available non-volatile memory capacity in width of the data bus between the cache memory and the main the market today. memory. PRIMARY MEMORY 1.0 INTRODUCTION Primary memory, previously known as storage, is the only one EPROM is widely used in various instruments and devices for directly accessible to the CPU. The CPU continuously reads storing experimental or ordinary data, assembly code and boot instructions stored there and executes them as required. Any data loader. Its relevance in microprocessor – based projects can actively operated on is also stored there in uniform manner. never be over emphasized. This memory chip has large Primary memory is directly or indirectly connected to the CPU applications in any industry or institute. An EPROM integrated via a memory bus, today sometimes referred to as a front side circuit has no usefulness until data or assembly code has been bus. It is actually comprised of two buses, an address bus and a programmed or written in it. A device programmer or data bus. specifically EPROM programmer is a device used to feed data The Cpushack [2] based on these core characteristics the and code into an EPROM. The device programmer has the following are the different classification of Primary memory. capability of performing all the EPROM programming operation Random Access Memory (RAM) such as the program reading operation, program or write Static Random Access Memory (SRAM) Dynamic Random operation etc. Although device programmer for particular Access Memory (DRAM) EPROM are available but universal EPROM programmer are Read Only Memory (ROM) IJERTV2IS90700 www.ijert.org 2346 International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 2 Issue 9, September - 2013 Mask Read Only Memory (MROM) The Microprocessor Parallel Port Interface Programmable Read-Only Memory (PROM) The Decoder Clocking Unit One Time Programmable Read-Only Memory (OTPROM) The Address Register Unit Erasable Programmable Read-Only Memory (EPROM The Data Latching Register Unit UV-Erasable Programmable Rom (UV-EPROM) The Programming Control Latch Registers Unit Non-Volatile UV-Erasable Programmable Rom (NVROM) The Programmer Identification Register Unit Hybrid Memory The Voltage Level Selection Units Non-Volatile Ram (NVRAM) The Graphic User Interface was implemented using Visual Basic Electrically Erasable Programmable Rom (EEPROM) Languageto keep the user in track with the events taking place in Flash Memory the programmer such as the Chip Write, Chip Read, Chip Verify 1.5 SECONDARY MEMORY controls. The GUI uses a very simple programming control Secondary memory or storage in popular usage differs from structure such that with very minimal computer knowledge any primary storage in that it is not directly accessible by the CPU. individual can use it effectively. Secondary storage does not lose the data when the device is The Microprocessor Parallel Port Interface is a computer powered down - therefore it is non-volatile. Some other peripheral device interface used to connect devices to the examples of secondary storage technologies are flash memory microprocessors bus. The use of Parallel port interface is (e.g. USB sticks or keys), floppy disks, magnetic tape, paper primarily due to it easy of programmability and speed which tape, punch cards, standalone RAM disks, and Zip drives. makes it optimal for real-time communication application. 1.6 TERTIARY MEMORY The Decoder Clocking Unit employs the use of digital Integrated Tertiary Memory or Tertiary Storage provides a third level of circuit decoder and some logic gate to generate pulsing signal storage. Typically it involves a robotic mechanism which will for the various part of the system. This clocking unit mountand unmount removable mass storage media into a storage synchronizes the operation of the Programmer with the device according to the system's demands; this data is often microprocessor data transfer speed. copied to secondary storage before use. It is primarily used for The Address Register Unit uses the address multiplexing archival of rarely accessed information since it is much slower technique to hold the address of the memory location in the than secondary storage EPROM to be programmed or read using the D-type registers. 2.0 JOINT ELECTRONIC DEVICE ENGINEERING The Data Latching Register Unit also uses this aforementioned COUNCIL (JEDEC). multiplexing technique to hold the data to be written into the JEDEC Standard [3] Joint Electronic Device Engineering memory location of the EPROM. It employs the use of D-type Council (JEDEC) standards and publications are designed to register and a transparent latch circuits. This unit is responsible serve the public interest through eliminating misunderstandings of transferring data from the EPROM to the microprocessor bus between manufacturers and purchasers, facilitating line and from the microprocessor bus line into the EPROM interoperability, interchangeability and improvement of memory cells products, and assisting the purchaser in selecting and obtainingIJERTIJERT The Programming Control Latch registers Unit uses transparent with minimum delay the proper product for use by those other latch interrogated circuit. It controls the selection or the different than JEDEC members, whether the standard is to be used either programming control signal such as the Chip Enable ( CE ), domestically or internationally. JEDEC standards and OE PGM publications are adopted without regard to whether or not their Output enable ( ) and Programming Voltages ( ) also the adoption may involve patents or articles, materials, or processes. selection of the different programming voltage levels form the This project also adopted some of the regulation of this Voltage Level Selection Units standardization
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