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Application Note 63 Using Nonvolatile Static Rams APPLICATION NOTE 63 Application Note 63 Using Nonvolatile Static RAMs Vast resources have been expended by the semicon- ability, higher density, low cost, and the ability to be used ductor industry trying to build a nonvolatile random ac- in any semiconductor memory application. cess read/write memory. The effort has been undertak- en because nonvolatile RAM offers several advantages While the various memory components designed to over other memory devices – DRAM, Static RAM, date do not meet the ideal memory scenario, each ex- Shadow RAM, EEPROM, EPROM and ROM – which cels in meeting one or more of the sought after attributes were developed to meet specific applications needs. (Figure 1). Characteristics of the ideal nonvolatile RAM are: low power consumption, higher performance, greater reli- MEMORY ATTRIBUTES Figure 1 EASE OF DATA COST INTERFACE NONVOLATILE DENSITY PERFORMANCE READ/WRITE RETENTION DRAM +++ +++ ++ +++ STATIC RAM +++ + +++ +++ NV SRAM +++ ++ + +++ +++ ++ PARTITIONABLE +++ ++ + +++ +++ ++ NV SRAM PSEUDO STATIC + + ++ + +++ FLASH ++ ++ ++ + ++ + ++ EEPROM + ++ + + + + EPROM ++ ++ ++ ++ + ++ OTP EPROM +++ +++ +++ +++ + +++ ROM +++ +++ +++ +++ + +++ + = Degree of excellence TYPES OF MEMORY ing much more current then an SRAM to maintain the Many types of memories have been devised to meet va- stored data. The net memory cell size is smaller for the rying application needs. However, nonvolatile read/ DRAM than for the SRAM, so the total cost per bit of write random access memories can be substituted for memory is less. The DRAM’s capacitors must be con- all memory types independent of application, if cost is stantly refreshed so that they retain their charge, and re- not a primary consideration. quire more sophisticated interface circuitry. DRAM: Dynamic Random Access Memory. A DRAM, SRAM: Static Random Access Memory. An SRAM is similar to an SRAM, stores information as a 1 or a 0. In essentially a stable DC flip–flop requiring no clock tim- an SRAM, this information is stored in a four to six tran- ing or refreshing. The contents of an SRAM type sistor flip–flop which is easy to address, but requires a memory are retained so long as power is supplied, and relatively large memory cell. A DRAM, by comparison, support extremely fast access times. SRAMs also have stores its 1 or 0 as a charge on a small capacitor, requir- relatively few strict timing requirements and a parallel ECopyright 1995 by Dallas Semiconductor Corporation. 090194 1/11 All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor databooks. APPLICATION NOTE 63 address structure, making them particularly suited for FLASH: A flash memory combines the electrical erase cache and other low density, frequent access applica- capability of the EEPROM in a cell that is similar to an tions. EPROM. The result is that the modified cell may be block erased electrically instead of with UV light. This NV SRAM: An NV SRAM is a single package which feature allows a Flash memory to accept new code up- contains a low current SRAM, a memory controller ca- dates or information while it is functioning in a system. pable of measuring voltage, and a lithium type battery. When the power supply to this single modular package EEPROM: Electrically Erasable/Programmable Read falls below the minimum requirement to maintain the Only Memory. A significant disadvantage of the contents of the SRAM, the memory controller in the EPROM is the fact that it cannot be reprogrammed while module switches the power supply from the external in a circuit. The EPROM requires an external program- source to the internal lithium battery and write protects ming device to receive new code or data. An EEPROM the SRAM. These transitions to and from the external eliminates this problem by providing a write function power source are transparent to the SRAM, transform- which can be used while the EEPROM is still in a circuit. ing it into a true non–volatile memory. This unique con- A penalty of obtaining the write function while the EE- struction combines the strategic advantages of SRAM– PROM is still in a circuit is having to provide a high volt- addressing structure, high speed access, and timing age (12.5V or above) source for the EEPROM to source requirements, with the non–volatility advantages of EE- when accepting new code, or buying a more expensive PROM technologies. Battery backed SRAM modules EEPROM which has a charge pump in its package that from Dallas Semiconductor are pin–to–pin compatible allows the EEPROM to be used with a standard 5–>7V with non battery backed SRAMs, making them ideal for input. Although nonvolatile, EEPROM memory cells any application where a traditional SRAM would be suit- exhibit slow read/write access rates, making them most able. suitable for systems where performance is not an issue. The other read/write capable memories listed in Figure PARTITIONABLE NV SRAM: A partitionable Dallas 1 provide the ability to frequently read and write data Semiconductor NV SRAM offers the same nonvolatility, continuously over their entire lifetimes, in excess of 10 addressing structure, and timing requirements of a reg- years, while EEPROM memory cells can rarely be re- ular Dallas Semiconductor NV SRAM product with the written more than 10,000 times. An EEPROM can be additional feature of the ability to write protect selected placed in a system and accessed as a standard RAM. blocks of memory, regardless of VCC. EPROM: Electrically Programmable Read Only The write protection feature requires no additional pins, Memory. An EPROM is a nonvolatile memory source and is instead controlled by a unique combination of ad- which offers flexibility to both program and erase the dressing and read cycles (see DS1630, DS1645 and contents of the memory multiple times. An EPROM DS1650 data sheets). This feature allows a designer to must be programmed using a 12.5 voltage or above use a battery backed SRAM as both a RAM and a ROM PROM programmer, and then transferred into the sys- – in one device. Because no additional pins are re- tem in which it is intended to function. EPROMs can be quired for control, partitionable devices can be substi- erased by shining ultraviolet light into the window in the tuted for non–partitionables in existing designs, without top of the IC package. The process of writing data into making costly hardware changes. an EPROM and then erasing it may be repeated almost indefinitely. EPROMs are usually used for product de- PSEUDO STATIC RAM: Pseudo Static Random Ac- velopment, and later replaced with less expensive one– cess Memory. The advantages of using a Static Ram time programmable EPROMS. are the simplicity of the interface circuitry required, and the fact that the device is by nature “static”, not requiring OTP EPROM: One Time Programmable EPROM. An periodic refreshing to retain its data. A DRAM, however, EPROM which can only be written with code/data once provides lower cost per bit advantages and a higher instead of multiple times. Generally, OTP EPROMs are memory density. A Pseudo static RAM combines the less expensive then erasable EPROMs. advantages of the SRAM and DRAM by using dynamic storage cells to retain memory, and by placing all the re- ROM: Mask Programmable Read Only Memory. Mask quired refresh logic on–chip so that the device functions programmable ROM’s are the most durable form of similarly to an SRAM. memory storage. They are, however, “read only” and of- 090194 2/11 APPLICATION NOTE 63 fer fairly slow performance. If a design has code/data Finally, because of the complexity of programming cir- that is very stable and will not need to be changed, a cuits, the cell structure and the special process technol- custom mask for the IC die can be made which will sig- ogy required, the density of EEPROMs has not kept up nificantly reduce the cost of the ROM. A drawback to us- with industry demands. ing a masked ROM is the significant cost penalty that must be incurred if an error in the code/data being In systems requiring store–and–forward data, the non- stored forces a mask set change. The OTP EPROM fills volatile RAM must provide the desired fast write cycle as the gap between ROM applications (no changes) and well as protection of memory in the event of a power EPROMs (frequent changes). loss. Despite the promise of such a memory device and the effort invested by the industry, the ideal nonvolatile RAM remains elusive. MEETING APPLICATIONS NEEDS NMOS DRAM memory provides performance and den- To more nearly emulate the ideal nonvolatile RAM, Dal- sity, but, on the down side, must be constantly refreshed las Semiconductor combines its intelligent CMOS con- to retain data. At the opposite extreme are ROMs, offer- trol circuitry (DS1210), a lithium energy source, and a ing nonvolatility and density, but lacking the ability to be very low power SRAM to offer a high density, nonvolatile updated with new data because information is burned in memory. only once. Between these two are a wide range of de- vices that fulfill some characteristics of the ideal Four devices, the DS1220 (2K x 8 bits), DS1225 (8K x 8 memory. bits), DS1230 (32K x 8 bits), and DS1245 (128K x 8 bits), use this fusion of technologies to provide a nonvol- Two popular devices, EEPROMs and Shadow RAMs, atile random access memory solution at a density of up are designed to emulate a static RAM but also have the to 1024K bits. ability to retain data after a power loss. But despite their capability to retain data, both EEPROMs and Shadow CMOS static RAMs currently available have read and RAMs fall short of meeting the industry’s needs for sev- write cycle times of under 100 ns, which exceed most eral reasons.
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