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A 13T Single-Ended Low Power SRAM Using Schmitt-Trigger and Write-Assist

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A 13T Single-Ended Low Power SRAM Using Schmitt-Trigger and Write-Assist Wright State University CORE Scholar Browse all Theses and Dissertations Theses and Dissertations 2017 A 13T Single-Ended Low Power SRAM Using Schmitt-Trigger and Write-Assist Praneeth Namala Wright State University Follow this and additional works at: https://corescholar.libraries.wright.edu/etd_all Part of the Electrical and Computer Engineering Commons Repository Citation Namala, Praneeth, "A 13T Single-Ended Low Power SRAM Using Schmitt-Trigger and Write-Assist" (2017). Browse all Theses and Dissertations. 1843. https://corescholar.libraries.wright.edu/etd_all/1843 This Thesis is brought to you for free and open access by the Theses and Dissertations at CORE Scholar. It has been accepted for inclusion in Browse all Theses and Dissertations by an authorized administrator of CORE Scholar. For more information, please contact [email protected]. A 13T Single-Ended Low Power SRAM Using Schmitt-Trigger and Write-Assist A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering By PRANEETH NAMALA B.Tech., Jawaharlal Nehru Technological University, India, 2014 2017 WRIGHT STATE UNIVERSITY i WRIGHT STATE UNIVERSITY GRADUATE SCHOOL July 25, 2017 I HEREBY RECOMMEND THAT THE THESIS PREPARED UNDER MY SUPERVISION BY Praneeth Namala ENTITLED ―A 13T Single-Ended Low Power SRAM Using Schmitt-Trigger and Write-Assist‖ BE ACCEPTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Master of Science in Electrical Engineering ___________________________ Chien-In Henry Chen, Ph.D. Thesis Director ___________________________ Brian Rigling, Ph.D. Department Chair Committee on Final Examination ___________________________ Chien-In Henry Chen, Ph.D. ___________________________ Yan Zhuang, Ph.D. ___________________________ Jiafeng Xie, Ph.D. ___________________________ Robert E. W. Fyffe,Ph.D. Vice President for Research and Dean of the Graduate School ii Abstract Namala, Praneeth. M.S.E.E, Department of Electrical Engineering, Wright State University, 2017.―A 13T Single- Ended Low Power SRAM Using Schmitt-Trigger and Write-Assist‖ SRAMs are widely used in application based systems like medical instruments, portable electronic devices from caches to registers. Technology scaling of transistor into nanometer regime has substantially increased memory density that occupies large silicon area in today’s IC’s and consumes significant amount of active and leakage power. So, design requirements and challenges such as memory write and read speed, leakage power, noise margin and process-voltage-temperature (PVT) variations also significantly increase. In this thesis, a 13T single-ended low power SRAM using Schmitt-Trigger and write-assist technique is presented. It enhances read static noise margin, write-1 and read-0 access time, specifically at low supply voltages. Designed in 1.05V 32 nanometer CMOS process, employing a Schmitt-Trigger in SRAM design achieves a higher read static noise margin (RSNM) of 3.65x and 1.79x as that of the standard 6T and conventional 8T SRAM, respectively. The read port configuration used in this SRAM design reduces about 50% of the Read-Bit- Line (RBL) leakage from un-accessed memory cells as compared with conventional 8T SRAM. The SRAM functions successfully with a minimum VDD of 340 mV, 100 mV lower than the threshold voltage so as to consume extremely low power. iii TABLE OF CONTENTS 1. Introduction .......................................................................................................................................... 1 1.1. Introduction to memories ............................................................................................................................. 1 1.2. Memory Arrays ............................................................................................................................................ 1 1.2.1. Random Access Memory ......................................................................................................... 2 1.2.1.1. Static Random Access Memory (SRAM) ..................................................................... 2 1.2.1.2. Dynamic Random Access Memory (DRAM) ............................................................... 2 1.2.2. Read-Only Memory .................................................................................................................. 4 1.2.2.1. Mask ROM (MROM) ................................................................................................... 5 1.2.2.2. Programmable ROM (PROM) ...................................................................................... 5 1.2.2.3. Erasable PROM (EPROM) ........................................................................................... 5 1.2.2.4. Electrically Erasable PROM (EEPROM) ..................................................................... 6 1.2.2.5. Flash ROM .................................................................................................................... 6 1.2.3. Serial Access Memory .............................................................................................................. 7 1.2.3.1. Shift Registers ............................................................................................................... 7 1.2.3.2. Queues ........................................................................................................................... 8 1.2.4. Content Addressable Memory (CAM) ..................................................................................... 8 1.3. SRAM Array Architecture ........................................................................................................................... 9 2. Conventional 6T SRAM Cell ............................................................................................................... 11 2.1. Write-Operation ......................................................................................................................................... 11 2.2. Read-Operation .......................................................................................................................................... 12 2.3. Stability of 6T SRAM cell ......................................................................................................................... 13 2.3.1. Hold Static Noise Margin (HSNM) ........................................................................................ 13 2.3.2. Read Static Noise Margin (RSNM) ........................................................................................ 14 2.3.3. Write Static Noise Margin (WSNM) ...................................................................................... 14 2.3.3.1. Butterfly curve method ............................................................................................... 15 iv 2.3.3.2. Bit-line method ........................................................................................................... 15 2.3.3.3. Word-line method ....................................................................................................... 16 3. Past Work of SRAM Cell ....................................................................................................................... 17 4. Proposed 13T Schmitt-Trigger SRAM Cell .............................................................................. 21 4.1. Single Ended SRAM Challenges ............................................................................................................... 21 4.2. Schmitt-Trigger .......................................................................................................................................... 22 4.3. 13T Schmitt-Trigger SRAM ...................................................................................................................... 23 4.3.1 Write-Operation ...................................................................................................................... 24 4.3.2 Read-Operation....................................................................................................................... 25 4.3.3 Hold-Operation ....................................................................................................................... 25 4.4 13T SRAM Cell Performance Evaluation ................................................................................................ 26 4.4.1 Write Access Time ................................................................................................................. 26 4.4.2 Read Access Time .................................................................................................................. 29 4.4.3 Static Noise Margin ................................................................................................................ 31 4.4.3.1 Hold Static Noise Margin (HSNM) ............................................................................ 31 4.4.3.2 Write Static Noise Margin (WSNM) .......................................................................... 32 4.4.3.3 Read Static Noise Margin (RSNM) ............................................................................ 33 4.4.4 Write and Read Power Consumption ..................................................................................... 34 4.5 4x4 memory array design ......................................................................................................................... 35 4.5.1 Read-Bit-Line Leakage Analysis ..........................................................................................
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