Via-Programmable Read-Only Memory Design for Full Code Coverage Using A Dynamic Bit-Line Shielding Technique Meng-Fan Chang1, 2, Ding-Ming Kwai2, and Kuei-Ann Wen1 1 Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan 2 Intellectual Property Library Company, Hsinchu, Taiwan
[email protected] Abstract 0-cell 1-cell 0-cell Crosstalk between bit lines leads to read-1 failure Metal-3 (BL) in a high-speed via-programmable read only memory (ROM) and limits the coverage of applicable code Via-2 (Code) patterns. Due to the fluctuations in bit-line intrinsic Metal-2 and coupling capacitances, the amount of noise coupled to a selected bit line may vary, resulting in the Via-1 reduction of sensing margin. In this paper, we propose a dynamic bit-line shielding (DBS) technique, suitable Metal-1 to be implemented in compliable ROM, to eliminate the Contact crosstalk-induced read failure and to achieve full code coverage. Experiments of the 256Kb instances with Diffusion Diffusion Diffusion and without the DBS circuit were undertaken using STI STI STI STI 0.25µm and 0.18µm standard CMOS processes. The test results demonstrate the read-1 failures and Fig. 1. Cross-sectional view of ROM array with via-2 confirm that the DBS technique can remove them codes and metal-3 bit lines. successfully, allowing the ROM to operate under a wide range of supply voltage. sectional view of the memory array with via-2 codes 1. Introduction and metal-3 bit lines. This leads to more severe bit-line crosstalk, since the contact and via at the lower levels Mask-programmable read-only memory (ROM) must be stacked and the metal islands for them to land macros are commonly embedded into system-on-chip upon contribute considerable side-wall capacitances to (SoC) designs today.