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New Ultra High Density EPROM and Flash EEPROM with NAND Structure

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New Ultra High Density EPROM and Flash EEPROM with NAND Structure NEW ULTRAHIGH DENSITY EPROM ANDFLASH EEPROM WITHNAND STRUCTURE CELL FUJI0 MASUOKA,MASAKI MOMODOMI, YOSHIHISA IWATA and RIICHIRO SHIROTA VLSIResearch Center, Toshiba Corporation 1, KomukaiToshiba-cho, Saiwai-ku, Kawasaki, 210 JAPAN ABSTRACT MEMORY CELL ARRAY Inorder to realize ultra highdensity Thenew NAND structurecell is EPROM andFlash EEPROM, a NAND structure fabricated by conventionaldouble poly cell is proposed.This new structure is silicontechnology. The floating gate is ableto shrink cell size without scaling madeof the first poly-Si layer, and the ofdevice dimensions. The NAND structur9 controlgate is madeof the second poly-Si cell realizes a cell as small as 6.43 um layer.The gate length ofmemory cell using 1.0 um designrule. As a result, transistor is 0.9 um. Thegate oxide cellarea per bit can be reduced by 30% thicknessunder the floating gate is comparedwith that of a 4M bit EPROM 200A.The interpoly oxide between the usingthe conventional structure and the floatinggate and the control gate is also samedesign rule. It is confirmedthat 200A thick.These parameters are the each bit in a NAND cell is ableto be same in 4M bit EPROM ofconventional programmedselectively. Thishio,h technology [ 11. Thenew NAND structure performance NAND structurecell is cellhaving 4 bits is showninFig.1-(a) applicableto high density nonvolatile comparedwith the current EPROM cell memoriesas large as 8M bit EPROM and having4bits as shown in Fig.1-(c). The Flash-EEPROM orbeyond. NAND cellarranges each bit in series. Theequivalent circuit of the NAND cell is showninFig.1-(b). Figure 2 shows occupiedarea of each bit versusnumber INTRODUCTION of bits connectedinone NAND cell structure.The current EPROM cellhas one Withthedevelopment VLSIof contactarea per two bits. However,for a technologies, bit densityof nonvolatile new NAND cell , onlysingle contact hole memories is undergoingrevolutionary is requiredper two NAND cells. As a growth. To realizeHegabit density result,the NAND cellcan realize smaller memories,current EPROM'shavebeen cellarea per bit thanthe current EPROM simply shrunk by introducingself-aligned cell. floatinggate structure and scaled dielectric.However, the current EPROM cell is now beginningto reach limitation in thescaling law, because it is hardto reducecontact hole size and spacing betweengate electrode and drain contact PRINCIPLE OF OPERATION hole.Therefore, a new NAND structure cell is proposedtoextend memory density The NAND structure cell is able to be beyondHegabit level. The cell described programmed by hotelectron injection to inthis paper realizes 30% cell area thefloating gate and erased by UV reductioncompared with a current irradiationor electric field emission of approach,such contactas hole size electronsfrom the floating gate. In a reduction.This NAND structurecell is programmode, 9V is appliedto the bit ableto be fabricated by current EPROM line. 1OV is appliedto the word line of processtechnology. the'selected bit and 2OV is appliedto the Thispaper describes the structure, otherthree word lines of unselected bits operationprinciple and reliability of a inthe NAND structure cell. Thebit line new NAND structurecell. voltage is mostlysupplied between the 25.6 552-IEDM 87 CH2515-5/87/0000-0552 $1.00 0 1987 IEEE drainand source of the selected bit. READING: Therefore,the selected bit operates in saturationmode and hot electrons are Figure 7 showssensing drain currents in generatedin the channel. On thecontrary, theread out mode of a NAND cellas a theother three unselected bits operatein functionof bit line voltage. 4V is deeptriode mode because of high gate appliedtothe control gate ofthe voltage,where the hot electrons are not addressed bit and 7V is appliedto the generated.Therefore, it is possibleto controlgates of theother bits. write onlythe selected bit in the NAND Currentdoes not flow at all when the cell . Figure 3 showsthat an EPROM has addressed bit is in written state. On the notbeen written in thetriode operation otherhand, current increases asthe mode.Thisprogramming characteristics drainvoltage increases when theselected were measured by thefollowing conditions. bit is in erasedstate. Two resistorsof 6k-ohms are connected between V anddrain and also between Vs RELIABILITY: and sou?~!e. Theresistance ofbot!? resistors is equivalentto the sum of Readretention characteristics is shown thatof the channels and the diffusion inFig.10. No threshold shift during read layersof the rest bits inthe NAND cell. operation in any bit ofthe NAND cell has Thethreshold voltage shift of a written beenobserved. transistorstrongly depends onthe Dataretention of the NAND cell is the control gatevoltage during programming. sameas that of current EPROM, because Thethreshold voltage shift does not occur each bit ofthe NAND cellhas the same with Vcg exceeding 13V. structureas that of current EPROM cell. In a readingoperation, 1V is appliedto bit lines,the low level CONCLUSION voltage is applied to theselected word lineand the high level voltage is applied A new EPROM with the NAND structure cell tothe other unselected word lines in the hasbeen developed. Each bit ofthe NAND NAND cell.Then the selected bit flows cellcan be programmedandread currentwhen the bit is inerased state separately,and also the reliability of anddoes not flow current when it is in thenew NAND structure is excellentas writtenstate. sameas the current EPROM. Thisnew technology enables one to shrinkthe cell size by 30% ascompared EXPERIMENTAL RESULTS withcurrent EPROMs withoutscaling the devicedimensions, Flash-EEPROM using NAND PROGRAMMING: cellarray is alsorealized by addingan extraerase gate. This NAND structurecan Theprogramming characteristics of the be successfullyapplied 8M or 16M bit NAND cellare shown in Figs.4, 5 and6. EPROMs andFlash-EEPROMs. Figure 4 showsthe threshold shifts of the selectedbit and the other three unselectedbits as a functionof the ACKNOWLEDGMENT programmingtime with all bits inthe NAND cellin erased state by UV irradiation. Theauthors would like to thank Theselected bit is writtenand the other K.Yoshikawa,N.Matsukawa, R.Nakayama, threeunselected bits are not written. S.Inoue,R.Kirisawa and H.Oodaira for Figure 5 alsoshows the threshold shifts theirsupports and useful discussions. as a functionof programming time withthe Theauthors would like tothank to selected bit inerased state by UV H.Iizukaforhis encouragement and irradiationand the other three unselected support. bits inwritten state. It is shownthat theselected bit is writtenwith the thresholdvoltage of the other three REFERENCES unselected bits remaining at the initial value.After sequential programming of [l] S.Atumi , S.Tanaka,S.Saito, the NAND cell,the threshold windows are N.Ohtsuka, N. Matsukawa,S.Hori, Y.Kaneko, kept at lager than 2V, as shown in fig.6. K.Yoshikawa, J. Yatsunagaand T.Iizuka., A 120ns4Nb CHOS EPROM", ISSCCDig. Tech.Papers, P.74-75 1987 25.6 IEDM 87-553 Bit line ri 1 OO IO 20 3.lpm -J Source Cell \3.1pmJ CONTROL GATE VOLTAGE, VcG (VI (A) (6) (C) Fig.3, Cell thresholdvoltage as a Fig.1.Comparison between a new NAND function Of a gate structurecell (A) andconventional cell (C).Figure (B) showsequivalent circuit of the NAND structure cell having 4 bits. 0 I- I I I 1 I I24 8 1632 0.I I IO 100 1000 NUMBER OF NAND CELL PROGRAMMINGTIME (msec) Fig.2.Occupied area of eachbit as a Fig.4. Cell thresholdvoltage as a function of thenumber of bitsconnected functionof programming time in the NAND inone NAND structure cell. structurecell. All bits are erased by UV initially,then cell(4) is programmed selectively. 25.6 554-IEDM 87 SELECT GATE = 4 V UNSELELCT GATE = 7 V ERASECELL / 0/ WRITE CELL - 0-0-0-0 / I I I 0.I I IO 100 IO00 0 I 2 3 PROGRAMMING TIME (msec) DRAIN VOLT. (VI Fig.5.Cell threshold voltage as a Fig.7.Cell current as a function of a functionof programming time in the NAND drainvoltage. structurecell. Cell(l), (2) and (3) are programmedand cell(4) is erased by UV initially,then cell(4) is programmed selectively. - Cell (3) I I I I I I 10 I o2 lo3 lo4 READ RETENTION TIME (SEC) Fig.8Read retention characteristcs. Fig.6. NAXD cellthreshold voltage after sequentialprogramming from cell(&) to cell( 1). 25.6 IEDM 87-555 .
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