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Fault Modeling and Testing of Flash Memories Olivier Ginez Fault Modeling and Testing of Flash Memories Olivier Ginez To cite this version: Olivier Ginez. Fault Modeling and Testing of Flash Memories. Micro and nanotechnolo- gies/Microelectronics. Université Montpellier II - Sciences et Techniques du Languedoc, 2007. English. tel-00194584 HAL Id: tel-00194584 https://tel.archives-ouvertes.fr/tel-00194584 Submitted on 6 Dec 2007 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. UNIVERSITE MONTPELLIER II SCIENCES ET TECHNIQUES DU LANGUEDOC T H E S E pour obtenir le grade de DOCTEUR DE L'UNIVERSITE MONTPELLIER II Spécialité : Microélectronique. Formation Doctorale : Systèmes Automatiques et Microélectroniques. Ecole Doctorale : Information, Structures et Systèmes. présentée et soutenue publiquement par Olivier GINEZ le 29 Novembre 2007 Modélisation de Fautes et Test des Mémoires Flash (Fault Modeling and Testing of Flash Memories) JURY M. Dominique Dallet, Professeur, IMS, ENSEIRB, Bordeaux Rapporteur M. Jean-Michel Portal, Maître de Conférences, L2MP, Polytech’ Marseille Rapporteur M. Jean-Michel Daga, Sté ATMEL, Rousset Examinateur M. Arnaud Virazel, Maître de Conférences, Université Montpellier II – LIRMM Examinateur M. Joan Figueras, Professeur, Politecnica de Catalunya, Barcelone Membre Invité M. Patrick Girard, Directeur de Recherche CNRS, LIRMM Directeur de Thèse M. Serge Pravossoudovitch, Professeur, Université Montpellier II – LIRMM Co-Directeur de Thèse Fault Modeling and Testing of Flash Memories 2 --------------------------------------------------------------------------------------------------------------------- A ma fille et à ma femme dont le soutien et la présence m’ont permis de mener cette thèse à bien. A mon grand-père qui je l’espère est fier de moi même si parfois le chemin que je trace n’est pas toujours droit. A mes parents qui ont su se montrer patients avec moi. Fault Modeling and Testing of Flash Memories 3 --------------------------------------------------------------------------------------------------------------------- Remerciements Cette thèse a été effectuée au Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), dirigé par Monsieur Michel Robert, Professeur à l’Université de Montpellier II, dans le département Microélectronique dont le responsable est Monsieur Lionel Torres, Professeur à l’Université de Montpellier II. Je les remercie de m’avoir accueilli. Toute ma gratitude va à mon directeur de thèse, Patrick Girard, Directeur de Recherche au CNRS, dont l’encadrement très professionnel, la présence et les encouragements constants m’ont permis d’évoluer en thèse en toute sérénité. Je voudrais qu’il trouve ici toute l’expression de ma reconnaissance. Je tiens à remercier mon co-directeur de thèse Serge Pravossoudovitch, Professeur à l’Université de Montpellier II, dont la pédagogie a suscité en moi l’envie d’enseigner mais aussi d’avoir bien voulu présider le jury chargé de juger ma thèse. Je remercie aussi Christian Landrault ainsi qu’Arnaud Virazel pour m’avoir encadrer avec beaucoup d’enthousiasme durant ces trois années mais aussi pour m’avoir tant apporté sur le plan scientifique et technique. La thèse nous prouve parfois qu’il ne s’agit pas forcément que d’une histoire de scientifiques mais aussi d’hommes ! Je voudrais également remercier Jean-Michel Daga, Manager de l’équipe conception de mémoires non-volatiles dans la société ATMEL, qui m’a beaucoup aidé tout au long de cette thèse tant sur l’aspect technique qu’industriel de mes travaux. Sa vision pragmatique et son esprit de synthèse ont été très précieux pour mener à bien cette thèse. Je lui adresse ici mes remerciements les plus sincères. Je remercie également Messieurs Dominique Dallet, Professeur à l’ENSEIRB de Bordeaux, Joans Figueras, Professeur à l’Université de Catalogne, et Jean-Michel Portal, Maître de Conférences à Polytech’ Marseille, de s’être intéressés à ce travail de thèse et d’avoir accepté d’en être les rapporteurs. Qu’ils trouvent ici toute l’expression de ma reconnaissance. Enfin, je terminerais en remerciant tous mes collègues du laboratoire pour les bons moments que nous avons passés ensemble, Grand Nico, Petit Nico, Marie, Lio, Alex N, Alex R, Fab, Alin, Seb, Robin, Olivier B, Nico H, JE, Julien V, Julien D, Olivier L, Marion, Mehdi, Olivier H, Luigi, Norbert, Réou, JB, JD, Diego. A tous Merci… Fault Modeling and Testing of Flash Memories 4 --------------------------------------------------------------------------------------------------------------------- Index INDEX--------------------------------------------------------------------------------------------------------------------------------4 GENERAL INTRODUCTION --------------------------------------------------------------------------------------------------6 CHAPTER 1: IN THE FIELD OF NON-VOLATILE MEMORIES -------------------------------------------------- 10 1.1 SEMICONDUCTOR MEMORIES: STATE OF THE ART------------------------------------------------------ 10 1.1.1 VOLATILE MEMORIES --------------------------------------------------------------------------------------------------- 11 1.1.1.1 Sram------------------------------------------------------------------------------------------------------------ 11 1.1.1.2 Dram ----------------------------------------------------------------------------------------------------------- 11 1.1.2 NON -VOLATILE MEMORIES --------------------------------------------------------------------------------------------- 12 1.1.2.1 Rom------------------------------------------------------------------------------------------------------------- 12 1.1.2.2 Eprom---------------------------------------------------------------------------------------------------------- 13 1.1.2.3 Eeprom--------------------------------------------------------------------------------------------------------- 13 1.1.2.4 Flash ----------------------------------------------------------------------------------------------------------- 14 1.1.3 FUTURE NON -VOLATILE MEMORIES ----------------------------------------------------------------------------------- 15 1.1.3.1 Phase Change Memories ------------------------------------------------------------------------------------ 15 1.1.3.2 FeRam --------------------------------------------------------------------------------------------------------- 16 1.2 NON-VOLATILE MEMORY TECHNOLOGY -------------------------------------------------------------------- 17 1.2.1 FLOATING GATE TECHNOLOGY ---------------------------------------------------------------------------------------- 17 1.2.2 CHARGE TRAP TECHNOLOGY ------------------------------------------------------------------------------------------ 19 1.2.2.1 Mnos Technology--------------------------------------------------------------------------------------------- 19 1.2.2.2 Sonos Technology -------------------------------------------------------------------------------------------- 20 1.3 EMBEDDED FLASH (EFLASH) MEMORIES BUILT WITH FLOTOX CORE CELLS----------------- 21 1.3.1 EFLASH MEMORIES ARCHITECTURE ---------------------------------------------------------------------------------- 21 1.3.2 EFLASH MEMORY FUNCTIONING -------------------------------------------------------------------------------------- 23 1.4 CONCLUSION------------------------------------------------------------------------------------------------------------- 24 CHAPTER 2: GENERAL ASPECTS ON MEMORY FAULT MODELING AND TESTING ------------------ 26 2.1 BACKGROUND OF RAM FAULT MODELING AND TESTING--------------------------------------------- 26 2.1.1 RAM FAULT MODELS ---------------------------------------------------------------------------------------------------- 27 2.1.2 RAM TEST ALGORITHMS ------------------------------------------------------------------------------------------------ 29 2.2 BACKGROUND OF FLASH MEMORY FAULT MODELING AND TESTING --------------------------- 32 2.2.1 THE 7-PATTERNS TEST SEQUENCE ------------------------------------------------------------------------------------ 32 2.2.2 THE 5-STEPS TEST SEQUENCE ----------------------------------------------------------------------------------------- 34 2.2.3 AN E FLASH FAULT SIMULATOR TO EVALUATE A BASIC TEST FLOW -------------------------------------------- 36 2.3 MARCH ALGORITHMS APPLIED TO EFLASH MEMORY ------------------------------------------------- 37 2.3.1 EFLASH COMPARED TO RAM ------------------------------------------------------------------------------------------- 37 2.3.2 EVALUATION OF MARCH ALGORITHMS IN E FLASH ---------------------------------------------------------------- 38 2.4 CONCLUSION------------------------------------------------------------------------------------------------------------- 40 CHAPTER 3: ANALYSIS AND MODELING OF ACTUAL EFLASH DEFECTS AND RELATED FAILURE MECHANISMS ---------------------------------------------------------------------------------------------------- 41 3.1 QUALITATIVE ANALYSIS OF FAILURE MECHANISMS IN FLOTOX CORE CELLS EFLASH-- 41 3.1.1 EXPERIMENTAL SET -UP AND FAILURE CLASSIFICATION -----------------------------------------------------------
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