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Introduction to Advanced Semiconductor Memories

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Introduction to Advanced Semiconductor Memories CHAPTER 1 INTRODUCTION TO ADVANCED SEMICONDUCTOR MEMORIES 1.1. SEMICONDUCTOR MEMORIES OVERVIEW The goal of Advanced Semiconductor Memories is to complement the material already covered in Semiconductor Memories. The earlier book covered the fol- lowing topics: random access memory technologies (SRAMs and DRAMs) and their application to specific architectures; nonvolatile technologies such as the read-only memories (ROMs), programmable read-only memories (PROMs), and erasable PROMs in both ultraviolet erasable (UVPROM) and electrically erasable (EEPROM) versions; memory fault modeling and testing; memory design for testability and fault tolerance; semiconductor memory reliability; semiconductor memories radiation effects; advanced memory technologies; and high-density memory packaging technologies [1]. This section provides a general overview of the semiconductor memories topics that are covered in Semiconductor Memories. In the last three decades of semiconductor memories’ phenomenal growth, the DRAMs have been the largest volume volatile memory produced for use as main computer memories because of their high density and low cost per bit advantage. SRAM densities have generally lagged a generation behind the DRAM. However, the SRAMs offer low-power consumption and high-per- formance features, which makes them practical alternatives to the DRAMs. Nowadays, a vast majority of SRAMs are being fabricated in the NMOS and CMOS technologies (and a combination of two technologies, also referred to as the mixed-MOS) for commodity SRAMs. 1 2 INTRODUCTION TO ADVANCED SEMICONDUCTOR MEMORIES Figure 1.1 Semiconductor memory market as a percentage of the total IC market [2]. In 1995, semiconductor memories accounted for 42% of the total IC market, but following 1995’s strong growth, memory prices collapsed for the next three years. In 1998, memory devices represented only 21% of the total IC market. During the 1990s, semiconductor memory sales averaged approximately 30% of total IC sales. It is forecasted that the memory portion of total IC sales will gradually increase through year 2005. Figure 1.1 shows the semiconductor memory market as a percentage of the total IC market [2]. In high-density and high-speed applications, various combinations of bipo- lar and MOS technologies are being used. In addition to MOS and bipolar memories, referred to as the ‘‘bulk silicon’’ technologies, silicon-on-insulator (SOI) isolation technologies have been developed for improved radiation hardness. SRAM density and performance are usually enhanced by scaling down the device geometries. Advanced SRAM designs and architectures for 4 to 16-Mb chips with submicron feature sizes have been developed and currently available as commodity chips. Application-specific memory designs include first-in-first- out (FIFO) buffer memory, in which the data are transferred in and out serially. The dual-port RAMs allow two independent devices to have simulta- neous read and write access to the same memory. The content addressable memories (CAMs) are designed and used both as the embedded modules on SEMICONDUCTOR MEMORIES OVERVIEW 3 larger VLSI chips, and as stand-alone memory for specific system applications. A major improvement in DRAM evolution has been the switch from three-transistor (3T) designs to one-transistor (1T) cell design, enabling pro- duction of 4- to 16-Mb density chips that use advanced 3-D trench capacitor and stacked capacitor cell structure. Currently, 64-Mb to 1-Gb DRAM chips are in production, and multigigabit density chips are being developed. The technical advances in multimegabit DRAMs have resulted in greater demand for application-specific products such as the pseudostatic DRAM (PSRAM), which uses dynamic storage cells but contains all refresh logic on-chip that enables it to function similarly to an SRAM. Video DRAMs (VDRAMs) have been produced for use as the multiport graphic buffers. Some other examples of high-speed DRAM innovative architectures are synchronous DRAMs (SDRAMs), cache DRAMs (CDRAMs), and Rambus2+ DRAMs (RDRAMs). Nonvolatile memories (NVMs) have also experienced tremendous growth since the introduction in 1970 of a floating polysilicon gate-based erasable program read-only memory (EPROM), in which hot electrons are injected into the floating gate and removed either by ultraviolet internal photoemission or by Fowler—Nordheim tunneling. The EPROMs (also referred to as the UVEPROMs) are erased by removing them from the target system and exposing them to ultraviolet light. An alternative to EPROM (or UVEPROM) has been the development of electrically erasable PROMs (EEPROMs), which offer in-circuit programming flexibility. Several variations of this technology include metal—nitride—oxide—semiconductor (MNOS), silicon—oxide—nitride— oxide—semiconductor (SONOS), floating gate tunneling oxide (FLOTOX), and textured polysilicon. The FLOTOX is most commonly used EEPROM technology. An interesting NVM architecture is the nonvolatile SRAM, a combination of EEPROM and SRAM in which each SRAM has a correspond- ing ‘‘shadow’’ EEPROM cell. Flash memories based on EPROM or EEPROM technologies are devices for which contents of all memory array cells can be erased simultaneously, unlike the EEPROMs that have select transistors incorporated in each cell to allow for the individual byte erasure. Therefore, the flash memories can be made roughly two or three times smaller than the floating gate EEPROM cells. Flash memories are available in 8- to 512-Mb densities as production devices, and even higher densities in development. DRAMs are currently (and predicted to be in the future) the largest memory segment in terms of dollar sales. After DRAMs the SRAMs and flash markets represent the next two largest memory segments. In year 2000, the flash memory market surpassed the SRAM market and became the second-largest memory market segment. Both DRAM and flash market shares are expected to continue growing through 2005, although flash memory at a much faster pace. The remaining memory segments are predicted to remain stable. 4 INTRODUCTION TO ADVANCED SEMICONDUCTOR MEMORIES Figure 1.2a shows a comparison of different MOS technologies market share projected to year 2005 [2]. It is predicted that in year 2005, the DRAMs will account for just 60% of the memory market, whereas flash memory sales is forecast to account for 29% of the total memory market. Figure 2.2b shows percentages for each MOS memory technology market for the year 2000 and predicted values for the year 2005. Semiconductor Memories reviewed various memory failure modes and mech- anisms, fault modeling, and electrical testing [1]. A most commonly used fault model is the single-stuck-at fault (SSF), which is also referred to as the classical standard fault model. However, many other fault models have also been developed for transition faults (TFs), address faults (AFs), bridging faults (BFs), coupling faults (CFs), pattern-sensitive faults (PSFs), and the dynamic (or delay) faults. A large percentage of physical faults occurring in the ICs can be considered as the bridging faults (BFs), consisting of shorts between the two or more cells or lines. Another important category of faults that can cause the RAM cell to function erroneously is the coupling or PSFs. In general, the memory electrical testing consists of the dc and ac parametric tests and functional tests. For RAMs, various functional test algorithms have been developed for which the test time is a function of the number of memory bits (n) and range in complexity from O(n) to O(n). The selection of a particular set of test patterns for a given RAM is influenced by the type of failure modes to be detected, memory bit density that influences the test time, and the memory automated test equipment (ATE) availability. Advanced megabit memory architectures are being designed with special test features to reduce the test time by the use of multibit test (MBT), line mode test (LMT), and built-in self-test (BIST). Application-specific memories such as the FIFOs, video RAMs, synchronous static and dynamic RAMs, and double- buffered memories (DBMs) have complex timing requirements and multiple setup modes that require a suitable mix of sophisticated test hardware, design for testability (DFT), and BIST approach. In general, the memory testability is a function of variables such as circuit complexity and design methodology. Therefore, the DFT techniques, RAM and ROM BIST architectures, memory error detection and correction (EDAC), and the memory fault tolerance are important design considerations. Structured design techniques are based upon the concept of providing uniform design to increase controllability and observability. The commonly used methodologies include the level-sensitive scan design (LSSD), scan path, scan/set logic, random access scan, and the boundary scan testing (BST). The RAM BIST implementation strategies include the use of algorithmic test sequence (ATS), the 13-N March algorithms with a data-retention test, a fault-syndrome-based strategy for detecting the PSFs, and built-in logic block observation (BILBO) technique. For the embedded memories, various DFT SEMICONDUCTOR MEMORIES OVERVIEW 5 Figure 1.2 (a) Comparison of different MOS memory technologies market share. (b) Percentages for each MOS memory technology market for year 2000 and predicted values for year 2005 [2]. and BIST techniques have been developed such as the scan-path-based flag- scan register (FLSR) and the random-pattern-based circular self-test path (CSTP). Advanced BIST architectures
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