44 SEMICONDUCTORS www.infineon.com Power Semiconductors on 300-Millimeter Wafers In February 2013 Infineon Technologies released the first products of the CoolMOS™ family being produced on its new 300-millimeter line at the Villach site in Austria. The production process based on the new technology has completed qualification and is now ready for delivery. This follows more than three years of intensive research and development activities within Infineon and with partners all over Europe in the fields of process technologies, production technologies as well as handling and automation for advanced power technologies. Dr. Gerald Deboy, Dr. Kurt Aigner Infineon Technologies, Villach, Austria
Due to their larger diameter compared 50 % loss being the norm rather than the sophisticated electric ballasts drives the to standard 200-millimeter wafers, two- exception. Figure 2 depicts the losses from saving of energy. Power electronics support and-a-half times as many chips can be the first conversion into electricity, along these transitions with fitting high voltage made from each wafer. With this massive the distribution to the final delivery of MOSFETs, drivers and controllers. invest of capital and engineering efforts power to the load in the end user Last but not least power supplies Infineon Technologies will be able to equipment. Modern power semiconductor fuelling datacenters and RF sustainably support the market with devices play a vital role to drive power telecommunication base stations are significantly enhanced capacity for leading electronics to better performance and indispensable for modern life style with edge power semiconductor devices. lower system costs, thus supporting further ubiquitous internet access and exchange proliferation of power electronics into more of data at high speed. Industry has The need for efficient power and more aspects of power conversion undertaken major steps under the electronics and control. Computing Climate Initiative to set out Power electronics play a major role in If we take a closer look into the saving more and more challenging efficiency harvesting the huge potentials towards a potential of various power applications the targets now culminating in the titanium more efficient usage of energy around the biggest impact can be reached in motor standard, which will be rolled out with ever globe as outlined in the OECD scenarios in control applications, where up to 40 % of increasing share in new IT equipment in Figure 1. Being more efficient along the the electricity is being consumed. The key the coming years. Key technologies here generation and conversion chain will be topic here is to move from on/off control are mainly high voltage and low voltage the key enabler to reduce the emission of to variable speed drives, which besides the MOSFETs ranging from 600 V devices in greenhouse gases. enormous energy saving foster less noise the AC front end to 25 V in the point-of- With an ever increasing contribution of generation and more comfort in e.g. air load converter. electricity to the global energy mix the conditioning applications. A further Strongly growing applications such as importance of power electronics will important focus area are lighting photovoltaics (forecasted to 60 GW fresh further grow. Most importantly, power applications with a roughly 15 % installations in 2016) and electro mobility electronics are mandatory to dramatically contribution to the energy consumption. In will further drive global demand for power reduce the huge energy losses that occur lighting mainly the transition from semiconductor devices. between the primary energy source and incandescent bulbs and magnetic ballasts, the energy end use(r). Today, even losses now being widely banned from EU Power technologies on 300 mm of up to 90 % are seen in the market, with countries to LED lighting and more Infineon Technologies hence undertook as
Figure 1: CO 2 reduction in different scenarios. The highest CO 2 savings can be gained from increasing energy efficiency
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Figure 2: Energy 300mm manufacturing losses from the In the first step to enable power source to the technologies on 300mm wafers, existing sink are 200mm technologies have to be dramatic “transferred”. Nevertheless it is much more than a transfer, because no power base materials were available for 300 mm at project start. Also some equipment for power technologies was not available for 300 mm. In reality it was and still is a challenging R&D project and not a “transfer”. Therefore it is necessary to prove the 1:1 capabilities of transferred products which are already available on 200 mm. Identical or improved performance of the devices has to be proved. Out of this, three major challenges are pointed out as a key for the development the first power semiconductor company manufacturing challenges. and production of power on 300mm the challenging task to manufacture To overcome this limitation, the EPT300 wafer diameter: leading edge power devices on 300 mm project aimed to provide solutions to the 1. Availability of power substrate on 300 wafers. This massive investment of capital following targets: mm at a cost efficient level (e.g. and engineering efforts will put Infineon Ⅲ Provide first MOSFET-products fabricated Infineon modification of p-type standard Technologies into a prime position for on 300 mm wafers in lead-fab substrate, development of 300 mm sustainably delivering production capacity environment in a 1:1 transfer approach power substrate by substrate suppliers) into a power sustainably growing market. to fully prove compliance with 2. Adaptation of 300mm CMOS Bundling the results of more than three application requirements on new equipment for power processes (e.g. years intensive research with the substrate material. front side- and back side processing and manufacturing expertise in factories such Ⅲ Provide enhanced equipment and new processing, thick layer processing, high as Villach and Dresden, Infineon achieved process technologies. temperature processing and of course the first customer releases for proprietary Ⅲ Prove manufacturability of these thin wafer processing, processing on CoolMOS™ technology fabricated on products in a high volume production bridge tools) 300mm by February 2013. environment with stable and acceptable 3. Thin wafer technology for 300 mm Infineon Technologies is partner in the yield figures. power technologies (adaptations of EPT300 project [1] – “Enabling Power Ⅲ Set the technology base for future Infineon’s 200 mm thin wafer Technologies on 300 mm wafers” – an enhancements in power semiconductor technology for 300 mm down to 40 ENIAC Joint Undertaking. With the help of technologies. µm, enabling 20 µm silicon thickness). EPT300, a consortium of 23 Partners from the European semiconductor The production of power 300 mm power substrate material manufacturing and the European semiconductors is highly complex, challenges equipment & materials industries are the involving many production steps requiring Today, CMOS devices are routinely first worldwide with a 300 mm power in-depth material knowledge and know- manufactured on 300 mm substrates, semiconductor processing line dedicated how. The first precondition is the enabling better chip performance at lower to power device production, realizing availability of proper raw materials and costs. While the performance is driven by leading edge manufacturing capabilities in production equipment. Given these, the smaller feature size (<45 nm), the cost Europe. first manufacturing steps deal with a series per device depends on chip size and wafer It is important to clearly distinguish of steps in which the active area of the power electronics fabrication from device is built up. Consequent steps are conventional CMOS manufacturing dedicated to semiconductor back-end technology. Having very different product production, which includes thin-layer characteristics, power electronics require metallization and a set of wafer backside different materials and processes, which process steps that are essential in had not been realized on 300 mm wafers manufacturing power semiconductors. before. The current state-of-the-art in One key process out of these is wafer manufacturing power semiconductors thinning, since the thickness of a power (MOSFETs, IGBTs and power IC device has significant influence on its technologies) today relies worldwide on performance. Infineon Technologies has 150 mm and 200 mm wafer technology. been pioneering the field of thin wafer Consequently, today’s manufacturing manufacturing mainly for its portfolio of equipment for such applications is IGBTs enabling e.g. the performance of its specifically designed to these wafer TRENCHSTOP IGBTs. However, wafer diameters. Technologies dedicated to thinning will also be a performance boost manufacturing power semiconductors on for Low voltage MOSFETs and is being 300mm wafers require capabilities that in used in our CoolMOS technology. the recent past posed unresolved Specific challenges on the way to www.power-mag.com Issue 3 2013 Power Electronics Europe 46 SEMICONDUCTORS www.infineon.com
Figure 3: Power Semiconductors significantly reduce energy losses
diameter as well. Still, given the demand device. Contaminations and impurities in generates a demand that calls for the volume, the available substrate materials the substrate thus affect the properties of adoption of 300mm technology also for are optimized to the requirements of these the devices in a much stronger way than these devices. However, even though all CMOS technologies, and do not CMOS structures. mainstream equipment for the necessarily allow for the specific Even now, dedicated raw materials for semiconductor production is now requirements of power technologies on 200mm power technologies are far more commercially available for 300 mm wafers, the substrate material. expensive than standard materials for there are big differences between For CMOS-technologies, p-type advanced CMOS processes. It is essential mainstream CMOS tools and the special substrates (mostly Boron) are in use, while to find a cost efficient solution for the equipment required in power technologies power technologies require n-type substrate to maintain the expected cost manufacturing. (typically Phosphor-doping) substrates. benefits out of the 300mm wafer Compared to CMOS processing the Furthermore, the needed doping levels diameter. processing of energy efficient power and device thicknesses depend strongly on semiconductor requires “3 dimensional the desired break down voltage, which Equipment challenges processing” (front side processing, back created another technological gap that The bigger part of the semiconductor side processing and processing vertically could be solved within the project. market is 300 mm CMOS technology (trenches) in the silicon), thick layer In CMOS technologies, the only active down to 28 nm feature size for mass processing, high temperature processing electrical area is located on the surface, products like DRAMs, Flash memories or and of course thin wafer technology. whereas in most power technologies the CPUs for PCs, notebooks and smart Infineon`s high voltage MOSFETs are entire silicon volume is used as electric phones. At the same time, the rapidly based on the so-called Superjunction currents flow from top to bottom of the growing potential of power technologies principle, a technology which allows to
Figure 4: Flexible use of equipment processing 200 mm and 300 mm is crucial
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Figure 5: Target wafer thicknesses for IGBTs
drastically reduce the on-state resistance bridge tools is the possibility to have an Using 300 mm wafers will further increase per chip area and to overcome the famous identical 200 mm reference on the same this challenge, with the trend pointing limit line of Silicon. While the on-state equipment. towards further reductions in the thickness performance benefits from an ever higher of the wafers. Ultimate wafer thicknesses doping level of the drift region the blocking Thin wafer manufacturing challenges may be as thin as 20 µm. Other voltage demands a perfect compensation As outlined above, power devices show technologies such as Infineon Low Voltage of three-dimensionally structured p- and n- vertical current flow, the load current MOSFETs will benefit from the doped regions across each device, across flows from the front to the backside of achievements in thin wafer handling to the entire wafer, from wafer to wafer and the device. To optimize the performance reduce both electrical on-state resistance from lot to lot. Significant effort is spent on the final thickness of a power device is and thermal resistivity of the remaining in-line control methods and sophisticated essential. Infineon`s IGBT technology substrate thickness. equipment operation and maintenance relies on extremely shallow p-doped respectively to successfully transfer the backside implants to control accurately its Conclusion CoolMOS technologies to 300 mm. emitter efficiency. In combination with a Infineon has shown the successful Other challenges for power technologies less shallow n-doped field-stop layer and implementation of power MOSFET are the high-temperature furnace the top side trench structure both the technologies on 300 mm wafer processes. Standard equipment for 300 distribution of the electric field (and manufacturing. The challenges regarding mm technologies is capable of processing hence the blocking capability) as well as availability of raw material as well as thin at a maximum temperature of ~1000°C. the carrier profile are precisely wafer manufacturing have been solved. Power technologies require temperatures engineered. Any excess in device Specific topics such as those posed for up to ~1200°C. This leads to major thickness would result both in an increase Superjunction devices and low voltage research on the hardware of furnaces in of the forward saturation voltage as well MOSFETs have been successfully order to comply with these challenging as the turn-off losses. Hence both key demonstrated. These achievements will requirements. This includes the heating performance indicators of an IGBT would put Infineon Technologies into a pole system and sophisticated temperature be compromised. Figure 5 shows the position to sustainably deliver capacity into controllers as well as special, adapted target wafer thicknesses for the coming a market with ever increasing demand for quartz ware technologies. years for the respective IGBT voltage power semiconductor devices. The flexible use of equipment being classes. capable to process 200 mm and 300 mm State of the art wafer thickness for [1] A part of the work has been wafers (bridge tool) is a key to enable 150mm and 200mm wafers for power performed in the project EPT300, co- highly flexible and cost competitive technologies is today 70 µm. This already funded by grants from Austria, Germany, manufacturing on European manufacturing implies a huge challenge in the handling of The Netherlands, Italy and the ENIAC Joint sites. Another important aspect of these such thin wafers because of their fragility. Undertaking.
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