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PROCESSING of INTEGRATED CIRCUITS 1. Overview Trends In ME477 Fall 2004 1. Overview • Integrated Circuit (IC) - a collection of electronic devices such as transistors, diodes, and resistors that are fabricated and PROCESSING OF electronically interconnected onto a small flat chip (die) of semiconductor material, resulting in ‘Solid State Electronics.’ INTEGRATED CIRCUITS • Materials in IC: – Silicon(Si) - Most common due to its properties and low cost 1. Overview – Germanium (Ge) 2. Silicon Processing – Gallium Arsenide (GaAs) 3. Lithography • Analog – Operate with continuous and variable voltages. 4. Layer Processing – Examples: Amplifiers, Oscillators, Voltage regulators 5. IC Packaging • Digital 6. Yields in IC Processing – Operate on signals of two discrete energy levels, 0 or 1. – Examples: Microprocessors and Memory devices for data storage 1 2 Trends in IC’s Transistor and Packaging • ICs are on a chip (a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) square or rectangular Integration # of Devices Yr silicon plate (0.5mm thick Level on a Chip introduced and 5-25mm on each Small Scale 10-50 1959 Integration (SSI) side)) connected by fine Medium Scale 50-103 1960s lines of conducting Integration (MSI) material (Al). Large Scale 103-104 1970s Integration (LSI) • IC’s are categorized by Very large Scale 104-106 1980s size and density of Integration (VLSI) devices per unit area, or Ultra Large Scale 106-108 1990s integration. Integration (ULSI) Giga Scale 109-1010 2000s • Packaging Integration 3 4 Processing Sequence Steps Clean Rooms A. Silicon Processing A. A large single crystal Silicon log (boule) B. Slicing into a wafer. • Reduce free air A number (in increments of ten) B. IC fabrication (Planar Process) particles through to indicate the quantity of A. Add (PVD & CVD), alter (Ion implantation, diffusion and thermal filtration, bunny suits. particles of size 0.5 µm or oxidation), remove (chemical and plasma etchants) a layer of • Control Humidity, greater in one cubic foot of air materials in selected regions (lithography) of the wafer Temperature. •A class 100 (10) clean room B. Finish and clean surface of wafer must maintain a count of C. The processed wafer is cut into chips • Control Radiation, particles of size 0.5 µm or C. IC Packaging. Light filters. greater at less than 100(10)/ft3 IC Packaging • Protect from IC Fabrication processing gases, • The clean room is air solvents, acids and conditioned to 21°C (70°F) and bases, organics, etc. 45% relative humidity Silicon Processing 5 6 Kwon 1 ME477 Fall 2004 2. Silicon Processing Crystal Growth • Production of Electron Grade Silicon (EDS) • The silicon substrate for microelectronic chips must be made of a single crystal – Start with very pure SiO2, quartzite – Submerge in an electron arc furnace with coke, coal, whose unit cell is oriented in a certain and wood chips to add Carbon, Heating will produce direction MGS (Metallurgical Grade Si) (98% pure) • Czochralski process – Start with a single crystal seed of known •SiO2 + C -> MGS + SiO +CO – Grind MGS into a powder, react with HCL orientation. – Somewhere along its length will be the • MGS + 3HCl -> SiHCl3 gas + H2 gas interface of the melt to air. In other words, –SiHCl3 will separate itself from impurities by melt half of it. evaporation. – Slowly pull up into air. • SiHCl3(gas) + H2(gas) → Si + 3HCl(gas) – Crucible material will reintroduce some impurities at the surface of boule. – Introduce more hydrogen gas to separate Si from HCl3 – EDS: nearly pure Si (less than 1ppb impurity). 7 8 A single crystal A diamond silicon ingot Shaping of Si into Wafers Wafer Preparation abrasive cut-off saw • Ingot Preparation • Thin saw blade with diamond grit on internal diameter – Thin saw to reduce waste of Si – Seed and tang ends are cut off – Internal diameter cutting for better control over flatness, thickness, parallelism, – Portions that don’t meet electronic specifications are removed surface characteristics • Resistivity and Crystallographic Specifications. • Edges are rounded to reduce chipping and to minimize accumulation of photoresist at rims of wafer • Shaping by cylindrical grinding for identification, • Chemical etch to create uniform surface topography and chemistry orientation and mechanical location • A flat polishing operation using a slurry of SiO2 to prepare the surface for photolithograph • Cleaning operation to remove residue and organic film High Speed Rotation Diamond contoured grinding wheel Slurry Wafer Wafer Polishing Pad Contour Grinding 9 Surface Polishing 10 3. Lithography Photolithograph Processes • An IC consists of many microscopic regions on the wafer surface that make up the transistors, devices and intraconnections imposed by the circuit design. • In the planar process, the regions are fabricated by steps that add, alter, or remove layers in selected areas of the wafer surface • Each layer is determined by a geometric pattern from circuit design, which is transferred to the wafer surface by lithography • Photolithography Align mask and – Uses light radiation (ultraviolet (UV) light) to expose a coating of Prepare Surface Apply photoresist Soft-bake photoresist on the surface of the wafer exposure –A mask containing the required geometric pattern for each layer covers the light source from the wafer, so that only the portions of the photoresist not blocked by the mask are exposed – Flat plate of transparent glass (2 mm thick) onto which a PVD/CVD- coated thin film of metal(few to less than one µm thick) of mask (patterned metal, usually Cr). Created by CAD, Pattern Generator and photolithography techniques Develop resist Hard-bake Etch Strip resist 11 12 Kwon 2 ME477 Fall 2004 Three Exposure techniques Photoresist 1. Contact - Wears mask, large resolution size, relatively inexpensive, high • An organic polymer polymer that is sensitive to light throughput 2. Proximity - No wear, large resolution size radiation in a certain wavelength range. 3. Projection - No wear, high resolution, serial processing: lower throughput, • The sensitivity causes either an increase or decrease in must be able to focus the beam. solubility of the polymer to certain chemicals • Typical practice in semiconductor processing is to use photoresists sensitive to ultraviolet light. UV light has a short wavelength compared to visible light, permitting sharper imaging of microscopic circuit details • Polymer must have good – Adhesion, Etch resistance, Resolution and Photosensitivity • Positive, Negative, Image Reversal Si Substrate Si Substrate Resist SiO2 Contact Printing Proximity Printing Projection Printing Positive resist Negative resist Si Substrate 13 14 3.2 Other Lithography 4. Layer Processes Techniques • Thermal Oxidation –SiOon Si acts as an insulator or a mask. • Electron Beam Lithography Method Wave Finest 2 –To grow SiO2, expose Si to oxygen gas and heat. Time and exact – Very small feature size, down Length Feature temperature effect thickness. to 1nm, No mask needed. (nm) Size (nm) – The Si wafer must have .44d to get the depth, d, of SiO2 – Costly equipment, Highly UV 365 350 • Chemical Vapor Deposition skilled user, slow. – Plasma-enhanced CVD takes place at a lower temperature. – Add layers of SiO , Si N and Si • X-ray Beam Lithography 2 3 4 Deep UV 248 250 •A SiOlayer is formed by thermal oxidation. – Can’t focus, Must use contact 2 •A SI3N4 layer is used as a masking layer. or proximity methods. • Polycrystalline silicon – Very small features. Extreme 10-20 30-100 – Epitaxial Deposition UV • controls the orientation of crystals • Electron & Ion Beam • Vapor-phase, Liquid-phase and molecular-beam epitaxy Lithography X ray 0.01-1 20-100 • Introduction of Impurities – Uses mask, can be focused. – Doping – adding impurities into silicon surface • Used to create p-n junctions that function as transistors, diodes and other devices Electron - 80 • p-type – Boron Beam • n-type – P(phorous), As(Arsenic), Sb(Antimony) – Methods • Thermal Diffusion • Ion Implantation 15 16 4. Layer Processes • Metallization 5. IC Fabrication Sequence – Deposition of conductive materials • Form certain components • Provide intraconnecting conduction path •Si3N4 mask is deposited by CVD onto the Si. • Connect the chip to external circuits •SiO2 insulator layer is grown in the exposed regions by – Metallization materials thermal oxidation. • Aluminum with Si and Cu • Other materials such as polisilicon, Au, refractory metals, silicides and •SiN is stripped by etching. nitrides 3 4 – Processes – vacuum evaporation, sputtering, CVD and electroplating • Additional SiO2 is grown on areas just exposed to act as • Etching Techniques a gate. – Material removal by etching away the unwanted materials • Polysilicon is blanket deposited by CVD and doped n- – Wet Chemical Etching d type using ion implantation. • Acid to etch away a target material Degree of Anisotropy: A= –Dry Plasma Etching u • Selective etch of polysilicon, remaining acts as a gate. • Ionized gas to etch away a target material. u • Dope source and drain with As by ion implantation. Resist SiO2 d • P-glass is deposited as a protective layer on the surface Si underetch overetch by CVD. 17 18 Kwon 3 ME477 Fall 2004 IC Fabrication sequence 6. Packaging Manufacturing 1. A layer of Si3N4 is deposited by CVD onto 5. Polysilicon is deposited Si substrate using The final series of operations to transform the wafer into individual photolithography to by CVD onto surface chips, ready to connect to external circuits and prepared to define the regions – the and then doped n-type withstand the harsh environment of the world
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