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Home , Electronics, Photolithography, Planar process, Rework (electronics), Wafer (electronics)

ME477 Fall 2004

1. Overview

• (IC) - a collection of electronic devices such as , , and that are fabricated and PROCESSING OF electronically interconnected onto a small flat chip () of material, resulting in ‘Solid State .’ INTEGRATED CIRCUITS • Materials in IC: – (Si) - Most common due to its properties and low cost 1. Overview – (Ge) 2. Silicon Processing – Arsenide (GaAs) 3. • Analog – Operate with continuous and variable voltages. 4. Layer Processing – Examples: , Oscillators, Voltage regulators 5. IC Packaging • Digital 6. Yields in IC Processing – Operate on signals of two discrete energy levels, 0 or 1. – Examples: and Memory devices for data storage

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Trends in IC’s and Packaging • ICs are on a chip (a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) square or rectangular Integration # of Devices Yr silicon plate (0.5mm thick Level on a Chip introduced and 5-25mm on each Small Scale 10-50 1959 Integration (SSI) side)) connected by fine Medium Scale 50-103 1960s lines of conducting Integration (MSI) material (Al). Large Scale 103-104 1970s Integration (LSI) • IC’s are categorized by Very large Scale 104-106 1980s size and density of Integration (VLSI) devices per unit area, or Ultra Large Scale 106-108 1990s integration. Integration (ULSI) Giga Scale 109-1010 2000s • Packaging Integration

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Processing Sequence Steps Clean Rooms A. Silicon Processing A. A large single Silicon log () B. Slicing into a . • Reduce free air A number (in increments of ten) B. IC fabrication () particles through to indicate the quantity of A. Add (PVD & CVD), alter (, and thermal filtration, bunny suits. particles of size 0.5 µm or oxidation), remove (chemical and etchants) a layer of • Control Humidity, greater in one cubic foot of air materials in selected regions (lithography) of the wafer Temperature. •A class 100 (10) clean room B. Finish and clean surface of wafer must maintain a count of C. The processed wafer is cut into chips • Control , particles of size 0.5 µm or C. IC Packaging. filters. greater at less than 100(10)/ft3 IC Packaging • Protect from IC Fabrication processing , • The clean room is air solvents, acids and conditioned to 21°C (70°F) and bases, organics, etc. 45% relative humidity

Silicon Processing 5 6

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2. Silicon Processing Crystal Growth • Production of Grade Silicon (EDS) • The silicon substrate for microelectronic chips must be made of a single crystal – Start with very pure SiO2, quartzite – Submerge in an electron arc furnace with coke, coal, whose unit cell is oriented in a certain and wood chips to add , Heating will produce direction MGS (Metallurgical Grade Si) (98% pure) • Czochralski process – Start with a single crystal seed of known •SiO2 + C -> MGS + SiO +CO – Grind MGS into a powder, react with HCL orientation. – Somewhere along its length will be the • MGS + 3HCl -> SiHCl3 + H2 gas interface of the melt to air. In other words, –SiHCl3 will separate itself from impurities by melt half of it. evaporation. – Slowly pull up into air.

• SiHCl3(gas) + H2(gas) → Si + 3HCl(gas) – Crucible material will reintroduce some impurities at the surface of boule. – Introduce more hydrogen gas to separate Si from HCl3 – EDS: nearly pure Si (less than 1ppb impurity).

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A single crystal A silicon ingot Shaping of Si into Wafers Wafer Preparation abrasive cut-off saw • Ingot Preparation • Thin saw blade with diamond grit on internal diameter – Thin saw to reduce waste of Si – Seed and tang ends are cut off – Internal diameter cutting for better control over flatness, thickness, parallelism, – Portions that don’t meet electronic specifications are removed surface characteristics • Resistivity and Crystallographic Specifications. • Edges are rounded to reduce chipping and to minimize accumulation of at rims of wafer • Shaping by cylindrical grinding for identification, • Chemical etch to create uniform surface topography and chemistry orientation and mechanical location • A flat polishing operation using a slurry of SiO2 to prepare the surface for photolithograph • Cleaning operation to remove residue and organic film

High Speed Rotation Diamond contoured grinding wheel Slurry Wafer Wafer Polishing Pad Contour Grinding

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3. Lithography Photolithograph Processes • An IC consists of many microscopic regions on the wafer surface that make up the transistors, devices and intraconnections imposed by the . • In the planar process, the regions are fabricated by steps that add, alter, or remove layers in selected areas of the wafer surface • Each layer is determined by a geometric pattern from circuit design, which is transferred to the wafer surface by lithography • Align mask and – Uses light radiation ( (UV) light) to expose a coating of Prepare Surface Apply photoresist Soft-bake photoresist on the surface of the wafer exposure –A mask containing the required geometric pattern for each layer covers the light source from the wafer, so that only the portions of the photoresist not blocked by the mask are exposed – Flat plate of transparent glass (2 mm thick) onto which a PVD/CVD- coated of metal(few to less than one µm thick) of mask (patterned metal, usually Cr). Created by CAD, Pattern Generator and photolithography techniques Develop resist Hard-bake Etch Strip resist

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Three Exposure techniques Photoresist 1. Contact - Wears mask, large resolution size, relatively inexpensive, high • An organic polymer polymer that is sensitive to light throughput 2. Proximity - No wear, large resolution size radiation in a certain range. 3. Projection - No wear, high resolution, serial processing: lower throughput, • The sensitivity causes either an increase or decrease in must be able to focus the beam. solubility of the polymer to certain chemicals • Typical practice in semiconductor processing is to use sensitive to ultraviolet light. UV light has a short wavelength compared to visible light, permitting sharper imaging of microscopic circuit details • Polymer must have good – Adhesion, Etch resistance, Resolution and Photosensitivity • Positive, Negative, Image Reversal

Si Substrate Si Substrate Resist SiO2 Contact Printing Proximity Printing Projection Printing Positive resist Negative resist Si Substrate 13 14

3.2 Other Lithography 4. Layer Processes Techniques • Thermal Oxidation –SiOon Si acts as an or a mask. • Electron Beam Lithography Method Finest 2 –To grow SiO2, expose Si to gas and heat. Time and exact – Very small feature size, down Length Feature temperature effect thickness.

to 1nm, No mask needed. (nm) Size (nm) – The Si wafer must have .44d to get the depth, d, of SiO2 – Costly equipment, Highly UV 365 350 • Chemical Vapor Deposition skilled user, slow. – Plasma-enhanced CVD takes place at a lower temperature. – Add layers of SiO , Si N and Si • X-ray Beam Lithography 2 3 4 Deep UV 248 250 •A SiOlayer is formed by thermal oxidation. – Can’t focus, Must use contact 2 •A SI3N4 layer is used as a masking layer. or proximity methods. • – Very small features. Extreme 10-20 30-100 – Epitaxial Deposition UV • controls the orientation of • Electron & Ion Beam • Vapor-phase, -phase and molecular-beam Lithography X ray 0.01-1 20-100 • Introduction of Impurities – Uses mask, can be focused. – – adding impurities into silicon surface • Used to create p-n junctions that function as transistors, diodes and other devices Electron - 80 • p-type – Beam • n-type – P(phorous), As(), Sb() – Methods • Thermal Diffusion • Ion Implantation 15 16

4. Layer Processes • Metallization 5. IC Fabrication Sequence – Deposition of conductive materials • Form certain components • Provide intraconnecting conduction path •Si3N4 mask is deposited by CVD onto the Si. • Connect the chip to external circuits •SiO2 insulator layer is grown in the exposed regions by – Metallization materials thermal oxidation. • Aluminum with Si and Cu • Other materials such as polisilicon, Au, refractory metals, silicides and •SiN is stripped by etching. nitrides 3 4 – Processes – evaporation, sputtering, CVD and electroplating • Additional SiO2 is grown on areas just exposed to act as • Etching Techniques a gate. – Material removal by etching away the unwanted materials • Polysilicon is blanket deposited by CVD and doped n- – Wet Chemical Etching d type using ion implantation. • Acid to etch away a target material Degree of : A= –Dry u • Selective etch of polysilicon, remaining acts as a gate. • Ionized gas to etch away a target material. u • Dope source and drain with As by ion implantation. Resist SiO2 d • P-glass is deposited as a protective layer on the surface Si underetch overetch by CVD. 17 18

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IC Fabrication sequence 6. Packaging Manufacturing

1. A layer of Si3N4 is deposited by CVD onto 5. Polysilicon is deposited Si substrate using The final series of operations to transform the wafer into individual photolithography to by CVD onto surface chips, ready to connect to external circuits and prepared to define the regions – the and then doped n-type withstand the harsh environment of the world outside the clean layer will serve as a using ion implantation mask for thermal room oxidation in step (2) 6. The polysilicon is selec- • Design Issues tively etched using 2. SiO2 is grown in – Electrical connections to external circuits exposed regions of photolithography to surface by thermal form gate electrode of – Materials to encase chip and protect it from the environment (humidity, corrosion, temperature, vibration, mechanical shock) oxidation. SiO2 regions transistor are insulating and will – Heat dissipation isolate this device from 7. The polysilicon is selec- other devices tively etched using – Performance, reliability, and service life –Cost 3. The Si3N4 mask is photolithography to stripped by etching form gate electrode of • Manufacturing Issues 4. Another thermal transistor oxidation to add a thin – Chip separation. gate oxide layer to 8. Phosphosilicate glass – Connecting the chip to the package. previously uncoated (P-glass) is deposited – Encapsulating the chip. surfaces and to onto the surface by increase thickness of – Circuit testing. CVD to protect the previous SiO2 layer • Materials – Ceramics and circuitry beneath 19 20

Packaging Considerations Major IC Package Styles • Dual in-line package (DIP) Rent’s Rule: – the most common form, available Determine the number of Input/Output leads. in both through-hole and surface mount configurations m nio = cnc • Square package – Leads are arranged around periphery so that number of where nio= # I/O leads required terminals on a side is nio/4 nc = # of devices in the IC • – Two dimensional array of pin terminals on underside of a square chip c, m = 4.5, 0.5 for modern VLSI enclosure – Square matrix of pins maximizes number of leads on a package – Entire bottom surface of package, except center area of package with no pins due to IC chip, is fully occupied by pins, so pin count in each direction is square root of nio • Some of these are available in both through-hole and surface mount styles, while others are designed for only one mounting method (a) through-hole, and several styles of surface mount : (b) butt , (c) "J" lead, and (d) gull-wing 21 22

Processing Steps Wire Bonding 1. Wafer testing - test chips while they are still part of the wafer using a multiprobe. • Ultrasonic Bonding 2. Chip separation using a thin, diamond tipped saw. Adhesive tape holds individual chips in place during and after sawing • Thermocompression Bonding 3. Die bonding - attach chips to the package by bonding with metal or • Thermosonic Bonding epoxy. After die is bonded to package, Packaging of an integrated circuit chip 1. Eutectic die bonding – for ceramic packages electrical connections are 2. Epoxy die bonding – for packages made between contact pads 4. Wire bonding - connect chip to package leads using a wire deposited by thermocompression, thermsonic, or ultrasonic on chip surface and package bonding. lead frame using small 5. Package sealing diameter wires 1. Ceramics (Alumina) –Hermeticaly sealed, lamination by pressing and sintering 2. Plastics (epoxies, polyimides, and silicones) – Cost effective, (a) cutaway view showing the chip postmolded or premolded. 6. Final Test attached to a lead frame and – Determine which units, if any, have been damaged during packaging encapsulated in a plastic enclosure – Measure performance characteristics of each device 23 24

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7. Yields in IC Processing • Fabrication of ICs consists of many processing steps performed in sequence Electronics Assembly and • At each step, a chance that something may go wrong results in the loss of the wafer or portions of it corresponding to individual chips Packaging • A simple probability model to predict the final yield of good product is:

Y = Yc Ys Yw Ym Yt – Crystal yield Yc - material in boule relative to starting amount of electronic grade silicon: Yc ∼ 50% 1. – Crystal-to-slice yield Ys - material left after grinding boule and sawing 2. (PCB) into wafers (kerf losses): Ys ∼ 50% 3. PCB Assembly – Wafer yield Yw - wafers surviving processing relative to starting quantity: Yw ∼ 70% 4. Surface Mounting Technology – Multiprobe yield Ym – proportion passing multiprobe test: Ym < 10% to 5. Electrical Connector Technology Ym > 90% – Final test yield Yt – proportion to pass final test after packaging: Yt = 90% to 95% 25 26

Levels in the Packaging 1. Electronics Packaging Hierarchy The physical means by which components in a system are electrically interconnected and Level Description of interconnection interfaced to external devices; it includes the 0 Intraconnections on the chip mechanical structure that holds and protects the 1 Chip to package interconnections circuitry to form IC package (e.g., dual in-line • Functions of a well-designed electronics package) package: 2 IC package to circuit board – Power distribution and signal interconnection interconnections – Structural support 3 Circuit board to rack; card-on-board – Protection from physical and chemical hazards packaging – Heat dissipation 4 Wiring and cabling connections – Minimize delays in signal transmission in cabinet 27 28

Level 0 Packaging Materials 2. Printed Circuit Boards (PCB)

• Semiconductor Materials • One or more thin sheets of insulating material – Silicon (Si), (GaAs), Hydrogenated amorphous silicon (a-Si-H) with thin lines on one or both surfaces that interconnect the components attached to –AlxGa1-xAs, Iny(AlxGa1-x)1-yP, Germanium (Ge), Si-Ge alloys – Wide-bandgap semiconductor, Tellurides, the board to each other. • Attachment Materials • Advantages: – Si, Polyurethane, Arcylic, Epoxynovolak, Phenolic, Bisphenol A, – Provide a convenient structural platform. Polyimide – Mass production of PCB’s can be consistent. • Substrate Materials – of PCB’s can be completed in one step. – Various ceramics – BeO, SiC, AlN, Si, Si3N4, SiO2, Al2O3, Diamond, , Steatite, Forsterite, Titanate, Cordierite, Mullite – Have reliable performance. – Molydenum, Cu:W, Tunsten, Kovar – Can be removed from work system and serviced separately

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Structures, Types and Materials Production • Starting Board • Insulating Materials Structure – Press multiple sheets of woven glass fiber that are impregnated with epoxy. – Polymer composites reinforced with E-glass. –Place Cu foil on one or both sides of laminate stack. If it is to be single – Substrate layer thickness = 0.8 to 3.2 mm sided, a thin release film will be placed on one side. – Heat and pressure are applied by a hydraulic press. • Material Properties - electrically insulating, strong and rigid, – Cool and trim. resistant to warpage, flame retardant. • Copper Foil - Produced by continuous electroforming, in which a • Copper foil thickness is ∼ 0.04 mm rotating smooth metal drum is partially submersed in an electrolytic • 3 types bath containing copper ions Copper foil – The drum is the cathode, causing the copper to plate onto its surface – Single sided board Insulating Substrate – As the drum rotates out of the bath, the thin copper foil is peeled. – Double sided board • Completed Board - Consists of a glass fabric reinforced thermoset – Multilayer board - consists of alternating layers of panel with copper over its surface on one or both sides – Usually produced in large standard widths designed to match the board conducting foil and insulation, Four layer board most handling systems in PCB processing and assembly equipment common – For a smaller size, several units can be processed together on the same larger board and then separated later

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Processes in PCB Fabrication Circuit Fabricator Processes • Board Preparation – Shearing, hole-making, and other shaping operations to create tabs, slots, and similar features • The circuit fabricator employs a variety of – The holes, called tooling holes, are made by drilling or punching – Bar coded for identification processes to produce a finished printed circuit – cleaning to remove dirt and grease from board surface board, ready for assembly of components • Hole Making – Mostly drilled but sometimes punched, using the tooling holes for – Operations include cleaning, shearing, hole drilling or location punching, pattern imaging, etching, and electroless • Drilled holes using standard twist drills are cleaner, but punching is faster • Most holes in PCB fabrication are drilled and electrolytic plating – For high production jobs, a stack of three or four panels may be – Some operations must be performed under clean drilled together or multiple spindle drills are sometimes used – Functional Holes: room conditions, especially for boards with fine tracks • Insertion holes for insertion of component leads • Via holes - to be copper-plated and used as conducting paths between and details two sides of the board • To fasten certain components such as heat sinks and connectors to the board • Circuit Pattern Imaging and Etching •Plating 33 34

Circuit Pattern Imaging & Etching Plating • Two basic methods to transfer circuit pattern to the copper surface of the board • Plating is needed on hole surfaces for 1. Screen printing conductive paths from one side to the 2. Photolithography other in double-sided boards, or between • Both methods use a resist coating on the board surface to determine where etching of the copper will occur to create layers in multilayer boards the tracks and lands of the circuit • Two plating processes used in PCB – Covered areas = circuit tracks and lands – Uncovered areas = open regions between them fabrication: • Etching is used to remove the copper cladding in the 1. Electroplating - higher deposition rate but unprotected regions from the board surface, usually by means of a chemical etchant coated surface must be metallic (conductive) – Transforms solid copper film into interconnections for an 2. Electroless plating - slower but does not electrical circuit require a conductive surface

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PCB Fabrication Subtractive Circuitization Method • Circuitization – The sequence of transforming a copper-clad board of reinforced • Open portions of copper cladding on starting polymer into PCB board are etched away from surface, so that – Subtractive, additive and semi-additive methods • Processing of different board types tracks and lands of desired circuit remain. – Single-sided board (1) apply resist to areas not to be etched, using photolithography to – Double-sided board expose the areas that are to be etched, (2) etch, and (3) strip resist – Multilayer board • Processes of Single-sided board – Cut to size, tooling hole & clean – Photoresist – Expose to UV – Resist developed –Etching – Strip remaining resist – Lead hole making Double-sided board

See Additive and Semi-additive Methods in Textbook 37 38

Testing and Finishing 3. PCB Assembly Electronic (e.g., IC packages, resistors, ) and • After fabricated on the board surface, it must be mechanical components (e.g., fasteners, heat sinks) inspected and tested for its functions and quality. mounted on a PCB • Two procedures are common: • Level two in electronic packaging 1. Visual inspection - by human eye or vision to detect • PCB assembly is based on either open/short circuits, errors in hole locations, and other faults 1. Pin-in-hole (PIH) technology 2. Continuity testing - use of contact probes brought 2. Surface mount technology (SMT) simultaneously into contact with tracks and lands on board – Some include both leaded and surface mounted components surface • Insertion - Hundreds of components to be inserted into • Apply a thin layer on tracks and lands to protect the board (PIH) the copper from oxidation and contamination. – Mostly by automatic insertion and a small proportion (perhaps 5% to 10%) by hand for nonstandard components. • Apply solder resist to all areas except lands, which will • Onsertion - Components are placed onto board surface be soldered during assembly. after adhesive application by automatic placement • An identification legend is printed. machines (SMT) – Place up to 4 components per second 39 40

Pin-In-Hole (PIH) Technology Soldering Processing of PCB assemblies with leaded components: 1. Wave soldering - Mechanized technique in which PCBs containing inserted 1. Component insertion – insertion of leads into through-holes components are moved by conveyor over 2. Soldering - leads are soldered into place in the holes a standing wave of molten solder 3. Cleaning • Use the combination of capillary action and 4. Testing upward force of wave 5. Rework • All solder joints are made in a single pass 2. Hand soldering - Skilled operator using Automatic Insertion Machines - perform component insertion either makes the circuit semi-automatically (position controlled by a human operator) or connections fully automatically (controlled by a program prepared directly from • Slow since each joint is made one at a time circuit design data) • Generally for small lot production and rework • In Automatic insertion machines, components are loaded into these • Prone to human error machines in the form of reels, magazines, or other • Sometimes used after wave soldering to add delicate components that would be damaged Manual Insertion - typically for a nonstandard configuration such as in the wave soldering chamber , connectors, resistors, capacitors and other components • High cost due to much lower production 41 42

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Cleaning, Testing, and Rework Surface Mount Technology (SMT) Component leads are soldered to lands on PCB surface rather than into holes running through the board • Cleaning - hand cleaning with appropriate • Inherent limitations of PIH in terms of packing density solvents and vapor degreasing to remove – mounted on only one side of board – Relatively large center-to-center distances between lead pins flux, oil and grease, salts, and dirt • Advantages of SMT – Increased packing densities • Inspection and Testing: – Require only 20% to 60% of board surface compared to PIH – Visual inspection to detect missing or – Mounted on both sides of board – No drilling of many through holes damaged components, soldering faults, etc. • Component Placement - Correctly positioning component on PCB and affixing it sufficiently until soldering provides a permanent – Functional tests to insure proper circuit connection operation 1. Adhesive bonding and wave soldering 2. Reflow soldering • Rework - manual repair of defects found in 3. Combined SMT-PIH Assembly • Certain types of SMT components are more suited to one method or inspection and/or testing the other

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Adhesive Bonding and Reflow Soldering Wave Soldering Solder paste = suspension of solder powders in a flux binder • Adhesive bond-fixes • Three functions: components to the surface until soldering 1. the solder - 80% to 90% of total paste volume attaches them 2. the flux permanently. 3. the adhesive to secure components to the board surface – Brush liquid adhesive • Methods of applying solder paste to board surface include through a stencil. screen printing and syringe dispensing – Automatic dispensing machine using x-y positioning. (1) adhesive is applied to areas on the board (1) apply solder paste where component will be placed; – Pin transfer method. (2) place components onto board, (2) component is placed onto adhesive-coated • Cure Adhesive areas; (3) bake paste, and • Wave Solder (3) adhesive is cured; and (4) solder reflow (4) solder joints are made by wave soldering 45 46

Cleaning, Inspection, Testing 4. Electrical Connector Technology and Rework • Printed circuit board assemblies must be connected to • Difficult due to smaller component size and increased density. back planes, and into racks and cabinets, which must • SMT Inspection be connected to other cabinets and systems using – More difficult due to denser packing, smaller solder joints, and different cables joint geometries than PIH assemblies – In SMT assembly, components are held by adhesive or paste • The performance of any electronic system depends on • During soldering this method is not as secure as PIH, and component the reliability of the individual connections shifting can occur • Connector technology is usually applied at the third – Another problem with smaller sizes is greater likelihood of solder bridges forming between adjacent leads, resulting in short circuits and fourth levels of electronics packaging •SMT Circuit Testing • Two Basic Connection Methods – Smaller scale also poses problems in circuit testing because of less 1. Soldering - most widely used technology in space around each component. Contact probes must be physically smaller and more probes are required because SMT assemblies are electronics more densely populated 2. Pressure connections - electrical connections in – One way of dealing with this issue is to design the circuit layout with which mechanical forces establish electrical extra lands whose only purpose is to provide a test probe contact site • Dilemma: this runs to the goal of higher packing densities continuity between components • Permanent or Separable solderless connections.

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Permanent Connections Separable Connectors • High-pressure contact between two metal surfaces, in Electrical connectors designed to permit disassembly and which one or both of the parts is mechanically deformed reassembly multiple times during the assembly process • When connected, metal-to-metal contact between mating • Permanent connection methods include: components with high reliability and low electrical – Crimping of connector terminals resistance • Mechanically deforming the terminal barrel to form a permanent connection with the stripped end of a wire inserted into it by hand tools • Typically consist of multiple contacts contained in a plastic or by crimping machines molded housing, designed to mate with a compatible – Insulation displacement connector or with individual wires or terminals • Permanent connection method in which a sharp, prong-shaped contact Terminal Blocks pierces the insulation and squeezes against the wire conductor to form Cable Connectors an electrical connection

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