resistanc collectod ean r capacit foune yar o t d commercial silicon controlled rectifier, today's necessarye b relative .Th e advantage lineaf so r thyristor. This later wor alss kowa r baseou n do and circular structures are considered both for 1956 research [19]. base resistanc r collectofo d an er capacity. Parameters, which are expected to affect the In the process of diffusing the p-type substrate frequency behavior considerede ar , , including wafer into an n-p-n configuration for the first emitter depletion layer capacity, collector stage of p-n-p-n construction, particularly in the depletion layer capacit diffusiod yan n transit redistribution "drive-in" e donophasth f ro e time. Finall parametere yth s which mighe b t diffusion at higher temperature in a dry gas
obtainabl comparee ear d with those needer dfo ambient (typically > 1100°C in H2), Frosch a few typical switching applications." would seriously damag r waferseou wafee Th . r surface woul e erodedb pittedd an d r eveo , n The Planar Process totally destroyed. Every time this happenee dth s e apparenlosexpressiowa th s y b tn o n The development of oxide masking by Frosch Frosch' smentiono t face t no , ourn o , s (N.H.). and Derick [9,10] on silicon deserves special We would make some adjustments, get more attention inasmuch as they anticipated planar, oxide- silicon wafers ready, and try again. protected device processing. Silicon is the key ingredien oxids MOSFEr it fo d ey an tpave wa Te dth In the early Spring of 1955, Frosch commented integrated electronics [22]. An account of their to Holonyak t again,i ,d "Weldi "e meaninw l g revolutionary developmen utilizatiod an t f SiOno s 2a e waferth s were again destroyed t thee Bu .nh vitae th l foundatio f today'o n s 1C industr s beeyha n smile displayed dan silicoe dth n wafer - snic e described by Holonyak [22]: and gree n coloi n n furthe(i r r instances also s techniciahi d an pink) ne H Deric. d ha k buildinn "I r variougou s experimental devices, switched from a dry-gas (typically N2 or H2) we were in contact with various groups and impurity diffusio wet-ambiena o nt t (H2O vapor individuals, but above all with Carl Frosch. carrie+ r gas) diffusion a consequenc, n a f o e Frosc consummata s hwa e process chemiso twh accident of the exhaust H2 igniting and flashing- was familiar with many types of processing back int diffusioe oth n chamber (becauss ga f eo procedure d beeha n d workingan s , wits hi h flow fluctuations) and causing H2O to cover, technician Derick n impurito , y diffusion into react with protecd an , silicoe th t n samples with silicon for several years. In spite of his oxide. The "wet" ambient, which was then considerable experience, Frosch, with dry gas immediately evaluated and adopted, created a diffusion procedures utilizing N2 or H2, protective oxide on silicon. It could be regularly reduced many of our silicon wafers to selectively remove r gaseoudfo s diffusion into "cinders, " particularly at higher temperatures the bare regions, which could the resealee nb d with oxide for higher temperature anneals or further diffusion. Many processing sequences Because we had mastered building a diff used- protective th coul f o devisee e db eus r oxidedfo , base alloyed-emitter silicon p-n-p transistor (in which f courseo , , prevented crystal pittind gan r problemspitou f o e s with diffusion)f o e on , erosion. Frosch and Derick quickly found out the p-n-p-n configurations that we could which impurities were blocked from diffusion explore was simply a modification of the p-n-p into silicon by the natural protective oxide (SiO ) transistor coule :W d fabricat diffused-base eth e 2 created in an H2O-vapor ambient and which alloyed-emitter p-n-p on one side of a p-type impurities would permeate the oxide (e.g., Ga). substrate wafer after it first was prepared with It was easy, once the issue of the oxide was an n-type diffused region (symmetrical) on known deviso t , e various scheme diffuso st e into both wafere sideth f o s. Either side coule db bloco t r o k impurity diffusion into silicone Th . chosen to form the p-n-p. The result was a p-n- process was so flexible that planar n-type p-n switch, in fact, the p-n-p-n switch of regions of any desired pattern could be prepared s exampla describe ) (b en i [19]d . (The o p-typna e substrate silicon oppositee th r o , - p , complementary versio f thino s exact structure, on-n diffused regions could be prepared on n- an n-p-n-p with Ga diffused into both sides of type silicon. All other diffusion procedures were an n-type silicon wafe d the an a rAu-Sn b suddenly rendered obsolete. We readily emitter alloyed on one side, was later converted the Frosch-diffused silicon n-p-n into introduce t a Generad l Electrie firsth ts a c a working p-n-p-n switch [19]."
12 Holonyak [22] noted "what Frosc Dericd han k added during the heating may be useful for revolutione basia th r t fo s hase do t n I don.s wa e protecting an electrical device from fact, it is the oxide on silicon that is the basis, the atmospheric conditions. For example, the vital foundatio f today'e no th f o sl 1al C f o chip d an , device might prove more stable if left silicon devices so critical to the electronics industry. enclose n i suc da hquart z envelope. Because of our (Holonyak) exploratory silicon possible b t Howeverno mako et y l ma eal t i , device work and our involvement with Frosch, we of the necessary electrical contacts through were close observers and witnesses of his work. For the quartz. In these cases some protection n a extensiv f L o BT e5 1 . examplep n o , ma e retaine yb e remova th a smaly db f o l l memorandum [177], Frosch wrote:" area of the envelope for the application of the contacts." "Thin silicon slices also were diffused with . HolonyaN r fo r preliminarb kfo S y device Holonya summarizes kha d Frosch's innovation development investigations. These were by "Frosch had, indeed, anticipated planar, oxide- hour6 1 d s an respectivel 5 diffuse , 2 r fo d y protected device processing e appreciateH . d at 1300°C in N2 saturated with water vapor immediatel e importancth y e oxides i th t f I o .e at room temperature. After diffusion, these questionabl f anyoni e e else's contributios a d ha n slices were green in color with an excellent o witmuce d existenc th ho e "chip t h th d f o an e" surface appearance. These layers were today's electronic Frosch's sa s oxide. Thi easils si y reporte havo dt e resistivitie o f t fro o s0 m1 see y simplb n y raisin e questionth g : Removee th 0 ohm 2 r squarepe s e diffusioTh . n layers oxide, say it doesn't exist, and then what would were reporte e uniforb o t d n thicknesmi s there Siliconbe? itself is,course,of criticalthe being 0.26, 0.39 and 0.76 mils respectively ingredient followed by its unique natural oxide. In for the 3 heating times. An additional run some sense it could its saidbe and that Si was made for Holonyak to produce layers of technology (its oxide) "invented" the 1C" (italics somewhat higher resistivity. In this run the entered by the author). thin silicon slices were heated for 1 hour at The benefits of SiO2 on the surface properties 1200°C followed by 16 hours at 1300°C in of silicon were concurrently, or shortly thereafter,
N2 saturated with water vapo t a roor m assesse Attala'y db s group [11,178]. They believed temperature. These samples again were that growing an oxide under clean and controlled gree n i colon r with excellent surface conditions, on a properly cleaned silicon wafer, appearance. These were reporte o havt d e would lead to both a reduction of surface states 0 ohm 9 resistivitier squaro pe t s 5 e4 f o s and passivatio e silicoth f no n surface e planaTh . r with a diffusion depth of 0.66 mils. The diffused transistor develope Hoerny db i [12-15f o ] higher resistivity values obtained indicate Fairchild Semiconductor Corporatio e latth e n i n not only a lower solubility of the Sb 1950's pulled together a number of these strands as compoun quarte th n di z envelop t 1200°ea C regards the benefits of SiO2 and was in production than at 1300°C but also the essential by 1959. These included the concept that the SiO2 absencb compounS f o e d e th vapo n i r masking layer, e utilizefabricatioth n i d f o n carrier gas when the temperature was raised diffused silicon transistors, be left in place for the to 1300°C. Holonyak was able to produce passivation of p-n junctions intersecting the very promising cross-point switches from surfacgrowe case th th f eo nn ei junction , allod yan some of these Sb diffusions." diffused mesa transistors, without the necessity of growing a passivating oxide under meticulously Holonyak [22] continue sayiny sb knee g"w w clean condition se insigh[179]th r f Hoerno pe t, i Frosch's work at first hand, and realized [12-15] as well as ensuring a dielectric layer for immediately what he and Derick had done. All of supporting metallic conductor overlayers in the 1C us near this work, which was just a few at first, a [16] e Si-SiOer Th . 2 diffusion technology hadn ,i realize s importanceit d , but truthn ,i , nonus f o e point of fact, been transferred from BTL to l Froschs al exceedinleashi f o n ti , g modesty, Shockley Semiconductor o t Fairchil, d projectes truit eo t futur t i d e scale. Frosch even Semiconductor Corporation and, from o t ther d ele e followinth ) wrot20 . gL (p estatemen BT s hi n i t the creation of Silicon Valley [180]. Numerous memorandum [177]:" testimonies as to the efficacy of the planar approach have been presented [122,158,181]. n additio "I e possibilitieth o t n f proceso s s Sparkes noted [159]: simplification, the protective quartz envelope
13 "Victor Grinich of the Fairchild Corporation e higth h electrical field wher junctioe eth n presented graphs of the change with time of came to the surface, was causing the current gain, base-emitter voltag cut-ofd ean f premature breakdow junctione th f nw o No . current of planar transistors which were so wbreakdownw e lo kne e e causwth th f o e . much better than anyone had seen before that All we had to do was eliminate all the quits iwa t e obvious tha f thei t y were genuine sources of particles." reaa l breakthroug beed hha n achieved. After several hours' discussion with Grinich it e planaTh r process introduced extreme becam e e tha e planacleam th t o t rr process flexibilit e fabricatioth n i y f junctioo n n transistors, was the process of the future. It was an sinc "tooline fabricateo th t " gup e different devices unpalatable conclusion, since, just at that time, involved changing the mask set, diffusion profiles many companies had recently invested large and doping levels and, as appropriate, the resistivity sum f monee double-diffusedo s th n i y e th , of the starting material. The planar process alloy-diffused or micro-diffused process with additionally facilitated the fabrication of a double- hope th f achievineo gcleaa r production nru diffused transistor essentially planar with the years.w fe o fa " original wafer surface, withou e necessitth t a f o y mesa structure. A photomicrograph of the first o morT e fully appreciat e significancth e f o e planar transisto s showi r Figurn ni e[122]4 . Chin- passsivating the p-n junction intersecting the Tang (Tom) Sah, Harry Sello and Tremere surfac mese th an ei transistor suc fabricates ha y db publishe firse dth t quantitative analysi oxide th f eso AT&T, one may consider Moore's assessment masking thickness and related time and temperature [122]: processin o ensurt g e blockag e diffusinth f o e g impurity in the oxide masked region [182]. It was n mes"I a transistors e emitter-basth , e especially important that these planar transistors had junctio p surfacto s i e exposen th e n o d the base contact completely surrounding the emitter betwee metae nth l contacts, whil basee eth - so as to eliminate any chance of the base inverting, collector junction intersects the sides of the as was the case for the original bipolar junction mesa (see Figure 3). The regions of high transistors [183,184]. With the advent of the planar electric fields wher junctioe th e n comeo t s technique, cut off frequencies in the range of 10 e surfacth e sensitivar e contaminationo t e . e achievedb z coulw GH no d , approaching values Contaminatio e emitter-basth f no e junction achieved for vacuum tubes [185]. Indeed, the can decreas e transisto th e gai f th eo n r exoduNoyceb Bo f so , Gordon Moore, Jean Hoerni, dramatically. In the case of the collector Jay Last, Julius Blank, Victor Grinich, Eugene junction, the breakdown voltage and Kleine d Sheldoan r n Roberts 1957 from Shockley leakage characteristics can change. We Semiconductor Laboratory, establishe n i 195d 5 note probleda m that transistore somth f eo s [69,122], and their subsequent formation of package hermeticalln di y sealedy candr n si Fairchild Semiconductor Corporation with the stated nitrogen showed very unstable collector goal of fabricating double-diffused transistors for junction characteristics. Breakdown commercial gain (the original goal of Shockley voltages sometimes decreased by several Semiconductor before Shockley redirecte effors dit t tens of volts and became unstable when p-n-p-e th o t n diod emajoe [174]th s r wa stimulu) s observed on an oscilloscope, potentially a to the invention of the planar transistor, Silicon major reliability problem formee W . tasda k e developmenth Valle d e fledglinan th y f o t g o understant y forctr o d correct e an d e th t electronics industry othee th n r O hand. t shouli , e db problem. One of our technicians, B. noted that Shockley, Noyce, Moore et al. were Robson, carefully cut the can off one of the cognizan f developmento t regards a L sBT SiOt a s 2 bad device d examinean s t i unded a r and were quite receptive to its advantages in the microscope e noticeH . a spod f ligho t t fabricatio f silicono n junction transistors factn I .e th , emitted from the side of the mesa when the entire diffusion technology at BTL was made transistor was biased into breakdown. He available to Shockley to help facilitate his ambition shut off the power and saw a tiny particle to derive a measure of success in the business world e poine e mesth th e th sidf ot o ntth a o e t transistoe baseth n do r technolog helped ha e o dyt h light emission. Carefully removing the develop. Shockley was not, however, to achieve his particl reapplyind ean g power foune h , d that business goal t contributedsbu , inadvertentlye th o t , the original high breakdown voltage was exodus from Shockley Semiconductor whichn i , restored. The particle, evidently attracted by conjunction with Stanford University's graduates, led
14 to the Silicon Valley phenomenon. Indeed, established the basis for the utilization of the Shockle s beeha y ne "Mose th referre s a f o s o t d aluminum metallization system [22]: Silicon Valley" [186].
Figure 4. Photomicrograph of the first planar transistor. The diameter of the circle that forms most of the outside ring is 0.030 in. The light areas are aluminum emitter and base electrodes. (From "A Solid State of Progress," Fairchild Camera and Instrument Corporation, 1979) [122]. Reproduced by permission of the IEEE, Inc.
s noteA d earlier e criticath , l elemente th r fo s "Satisfactort no l evaporatioA d y di i S n o n fabricatio e transistoth f o d nthryristo an r r and, exist whe r worou n k started. Moll obtained subsequently e 1Cth , electronic a (oxidationer s , permission fros mhi e Tanenbauus o t s u r mfo diffusion, photolithography, aluminum evaporator, and we quickly solved the metallization and thermocompression bonding) problem of evaporating Al on Si, on "hot" or were now all available. Jules Andrus and Bond on werd "coldan e, abl"Si realizo et e precise showed that certain photoresists, when deposited shallow alloyed p-type contact shallor so " w"p on SiO2, would protec underlyine th t g SiO2 during on junctions"nn "p- were W . e abl shoo et w etching processes [180,187,188]. Optical exposure e variouth s conditions under which uniform of the resist using contact masks in the late 1960's evaporate l contactA d s coul e realizeb d n do and early 1970's, projection maske middlth n i se i substratS e 660°th s f I ewa ) hotterr Co (1 : Si , 1970' stepped san r mask methodologies beginning the evaporated Al (mobile Al) nucleated at e lateith n r 1980' s use o wa creatt sd e precise random sites that grew into larger diameter window patterns (open regions) in the oxide and, islands with more evaporated Al, and formed therefore, precise contro f o diffusiol n areas. a discontinuous regrowthe n regionIn (2) . Aluminum metallization was utilized to form temperature range betwee Al-Se nth i eutectic ohmic contacts to both p- and n-type material. (577°C) and the melting point of Al (660°C), While the former was expected due to Al being a uniform l stickinA d e wettinth an g f o g grou I dopantpII lattee achieves th , wa r d since eth occurred and formed continuous metallized contac s subsequentlwa t y identifie o fort d a m and alloyed-regrown p-typ i withoueS t further tunnel diode with the n-type silicon, the tunnel heating. (This was nothing more than Hall's diode characteristic being linear (and, therefore, "local" liquid phase epitax [139,140]E LP y . simulatin n ohmia g c contact r botfo ) h small i substratS e th t r temperaturea Fo ) (3 e 577°C positive and negative voltages about the origin. r lowero e evaporateth , l merelA d y adhered Moor d Noycan e e receivee a th patend r fo t subsequentld an (uniformly , Si e th yn o )coul d aluminum metallization [189]. Holonyak has be alloyed or could be left as a Schottky described the experiments conducted at BTL which barrier laty B .e 1954, Golde Holonyad yan k had solve problee dth f metallizinmo d an i gS
15 forming uniform shallow p-n (or n-p) (formatio inversion a f o n n layer, i.e., enhancement junctions, or if desired, shallow ohmic mode) by Dawon (David) Kahng and Attala in 1960 contacts. Holonyak soon wrote a BTL [195-198], also summarized by Sah [44]. Kahng memorandum on Al metallization and shallow wrote an extensive BTL technical memorandum on junction formation on Si [190] and Goldey the silicon/silicon dioxide device in 1961 [199]. incorporated this material and some further Steven Hofstei Fredericd nan k Heima Radie th f noo results in a report published later [191]." Corporation of America (RCA) followed with an S 1C consistinMO 6 silico1 f o gn n-channeS MO l Contacts from the junction transistor to the transistor n 196i s 3 [200] t shoulI . d als e noteob d header were usually made by thermocompression tha . TorkeJ t l Wallmar patena too A t kou RC t f ko bonding, developed at BTL by O.L. Anderson, H .n 195i T 7 FE [201 n ot a napparentl ]bu o n d di y Cristensen and P. Andreasch [4]. Typically, gold furthe re fielth wor dn i kwhil e Paul Weimer (melting point 1063°C) was brought in contact with constructed an FET using CdS as the dielectric aluminue th m bondin (meltind gpa g point 660°Ca n )i materia insulatinn a n o l g substrat n 195i e 9 [202]. reducing atmosphere under pressure e goldTh . - Although these structures were minority-carrier aluminum eutectic forme t aboua d t 350°C which, devices e Metal-Semiconductoth , r Field Effect upon cooling, forme stronga d , reliable s bondwa t I . Transistor (MESFET e Junctioth d an )n Gate Field subsequently observed tha phenomenoa t n referreo dt Effect Transistor, see Figure 5 [4], first described "purpls a e plague" often develope undesireo t e ddu d and patented by Shockley [203,204] and built by reactions betwee gole nth daluminue th wire d an s m George Dacey and lan Ross [205] were majority bonding pads at the upper range of temperatures carrier devices [44,206,207]. where silicon transistors operate aluminue Th . d man gold forme a seried f coloreo s d intermetallics (i.e., MOSFET Transistor Fabrication e purplth e plague) that ultimately caused device failure [43]. Rectificatio f thio n s yield degradation e descriptioTh e oxidatioth f o n n procesd an s s subsequentlwa y achieve y restrictinb d e th g methodologies for controlling the electrical properties temperature range of operation (also required for the e silicon/silicooth f n dioxide interfac e latth e n i e plastic packages then utilized), utilizatiol al f o n 1950's were e th successfuessentia r fo ll aluminum systems using aluminum leads, wired an s commercialization of the MOSFET and aluminum coated package connections [43]. Gold implementatio e DRAth f o Mne th memor n i a er y metallization systems such as the beam lead method 1970's (see the Integrated Circuit section.) Deal and [192 multileved ]an l metallization schemes [193,194] Grove describe oxidatioe dth n kinetic f silicoso n [23], were also developed. followe Denniy db s Hess [208], Eugene Irene [209], The benefits of the planar research in Hisham Massoud [210] and Stanley Raider [211] and conjunction with Hoerni's insights resultee th n i d their colleague extendeo swh d this research. Richard first meaningful descriptio MOSFEe th f no T device Williams [212] and Akos Revesz [213] also made
Figur . e5 Schemati junctioe th f co n field-effect transistor [4]. Reproduce permissioy db IEEEe th f no , Inc.
16 significant contributions to the understanding of the abstract [31] (Sah's comment e addear s curln i d y silicon/silicon dioxide interface while George brackets): Schnable [214] advance understandinr dou hosa f go t of dielectric film deposition methodologies for "The main He effec2th treatmenf o t t appears Integrated Circuit (1C) applications [8]. e annihilatioth e b o t f fasno t states {another Device reliability studies by Ed Snow, Grove, name for interface states}. If these states are t Fairchila h Sa Deadd Semiconductoan l r identified relate o t vacanciesd , accompaniey b d that sodium contamination in SiO2, introduced by the chemically unsaturated bonds {has been heated tungsten filament [215 r aluminufo ] m know s danglina n g bonds d unpairean } d evaporation, was mobile under voltage stress, caused electrons neae interfaceth r e Hth 2, {not device parametrics to drift under operating bias and hydroge r protoo n s a somio nn e think} was exacerbate increasey db d operating temperature. n effeci e chemicaannealine th b t y ma lg The Fairchild team also observed that electron-beam saturation {now know s hydrogenationa n } evaporation did not introduce the sodium [215], wit atomhH f thesso e bondvacanciese th t sa . thereby developing technique r controllinfo s e th g The low state density obtained upon steam sodium and, furthermore, developed an extensive oxidatio s probabli n y cause y hydrogenb d , understanding of the phenomena taking place in the evolved during oxidation retained e an , th n di metal-oxide-silicon system that is basic to all modern oxide. The similarity in action between H2 and MOSFET systems. Deal described the silicon/silicon Al remain t unexplained.ye s sa " dioxide electrical interface stability and associated effect n silicoi s n dioxid 7 typen termi 1 e f f o so s Balk clarified the unresolved issue as regards charge mechanism d introducean s e standarth d d the similar benefit between a H2 and an N2 anneal of description for the charge notation associated with Al later that yea 196n ri 5 [32] [44h Sa .] again quotes thermally oxidized silicon [24-30]. The reduction of Balk: mobile charges, fixed charge (Qf) and interface state charge e (Dcontroe growt th s th welita ) s f a o ll h "The similarit e annealinth f yo g behaviof o r process (oxide f thicknesso paramoun s wa ) t electricae th l interface propertie f Si-SiOso n 2i importance in ensuring threshold voltage control and d Al-SiOHan 2 2-Sn Ni i2 around 300°C the successful commercialization of MOS device suggests that the same mechanism is operative products [216]. While most of the industry initially in both cases. Hydrogen release reactioa n di n chos fabricato et e PMOS devices, some companies betwee hydroxyd an l nA l group oxide th n esi electe o fabricatt d e NMOS becaus e higheth f o er is propose active th s dea Al-SiOagene th n i t 2- channel mobilit r electronsfo y , compare o holest d . Si case. This model is supported by the However, positive charge contro mora s i le serious absence of any annealing effects on 'ultra-dry' issu NMOn ei S technology. Post-oxidatio postd nan - oxide." metallization anneals were develope 1960'e th n di o st minimize both fixed interfacan d e charge [31,32]. It was suggested that residual H2O, released mobile Th e, als chargeK od requirean ,a sucN s dha from the Al during thermal processing, reacts with stringent control. the hydroxyl groups to yield hydrogen. Sah further Techniques were developed for the passivation points out the beneficial effect of annealing in H2 or of surface states introduce e silicon/silicoth t a d n forming gas (95% N /5% H ) [218]: dioxide interface during thermal processing. Pieter 2 2 Balk described in 1965 the significance of a post "Balk's hydrogen bond model of passivating SiO2 anneal in a hydrogen bearing ambient [31] and a nitrogen anneal in the case of the Al-SiO -Si system and deactivating the interface traps has also 2 been the chemical-atomic base for the [32 stabilizo t ] Si-SiOe eth 2 interfac reducd an e e eth fixed charge MoleculaQf. , r hydroge suggestenwas d characterizatio e generationth f o n , annealing to anneal the surface states by bonding with the and charging kinetice interfacth f d o s an e dangling silicon and oxygen bonds [31,32]. Kooi of oxid esilico to trap oxygesndue and n dangling Philips Research Labs in Eindhoven confirmed bonds." Balk's research [217]. Sah has noted that Balk's hydrogen annealing methodology has withstood the Balk's insigh s extremelwa t y important during tesf timo r tmor fo e a e s i tha 0 year3 d n an s the early 1970's stils ,dominane wheth lwa l nA t gate fundamental aspect of the MOSFET 1C processing electrode, befor introductioe eth polysilicoe th f no n gate methodology [44]. Sah has quoted from Balk's electrode and the fabrication of the IK and, in some dynamicasesK 4 e ,th c random access memory (DRAM)
17 1C. The last thermal process step (before packaging) corrosiv ambien 1 e furnacth HC e n e effeco teth f o t minutwa0 3 anneao s a r eo l between 400° 450°r Co C metal plumbing. ensuro t e sufficient reactio aluminue th f no m wite hth Getterin s initiallwa g y believe o occut d y b r silicon for good contacts; the release of H2 from the formatio f volatilo n e metal chlorides, althouge th h aluminum during the 450° C anneal was instrumental Gibbs free energy of formation of most metal in passivating the interface states and recovering the chlorides was not negative. The Cl, however, was desired threshold voltage e rol f hydrogeTh o e. n also interprete s a removind g interstitialss a , annealing and passivation in the broader context of evidence e shrinkagth y b d f oxidatioo e n induced the plasma deposited overlayer of silicon oxynitride stacking faults (OISF) at sufficiently high as a seal over the entire circuit has also been temperature by Hiromitsu Shiraki [233], Cor Claeys discussed [219]. [234 theid an ] r colleagues. Shih-Ming (Jimmyu H ) Dalton and Dorbek of AT&T [220] showed that the shrinkage (retrograde growth) of demonstrated tha overlayen a t f Sio r 3N4 could also OIS t sufficientlFa y high temperature absence th n si e provide an effective seal against sodium ions; to of HC1 was dependent on both the surface orientation avoi concurrenthe d t trappin hydrogeof g n ions and ambient [235]. The early utilization of these Cl resulting in threshold voltage instabilities, silicon ambients was in conjunction with the oxidation oxyitride was subsequently utilized. Indeed, a plasma ambient during high-temperature processingl C e Th . deposited overlayer of silicon oxynitride is used as a incorporate SiOe th 2n d i als o trappe immoblized dan d seal over the entire circuit structure, except for the the sodium at room temperature. It was suggested by contact pads e nitrid[4]Th . e fil s i alsm o very Kreigler and Osburn, furthermore, that it might be effectiv reducinn i e g pinhole e SiOth 2n i sdielectric . more advantageou cleao st furnace nth e quartz tube Concurrently, Kerr and Don Young of IBM were in the presence of the Cl bearing species but not to developing the utilization of a phosphosilicate glass incorporate the Cl into the SiO2 film, per se, due to (PSG) deposited on top of the MOS gate dielectric SiO2 reliability considerations [227,229]. silicon dioxide to getter the Na and K and stabilize The subsequent capacitance-voltage (C-V) e oxidth e film [221,222]. This approacs wa h diagnostic e analysiSi-SiOth f o s2 interface especially importan r aluminufo t m gate electrodes, electrical properties by Moll [236] and Terman utilized prior to the phosphorus doped polysilicon [237], was expanded upon by Grove, Snow, Deal gate technolog e discusseb o t y d below. Snod wan h [238an f usefuSa do d formulate t an ]se l a n i d Deal [223], followed by Pieter Balk and Jerome charts for fabrication engineers by Zaininger and Eldridge [224], showed thae thresholth t d voltage Heiman [239]. Edward Nicollia d Adolan n f shifts of MOSFET's, induced by polarization in the Goetzberger's conductance analysis [240-243] PSG layer on the SiO2 surface, could indeed be quantified the description of the silicon/silicon controlled. Stabilizatio e surfacth s alsf o wa noe dioxide interface electrical propertiesn whilp- e eth beneficia r bipolafo l r transistor r operatiosfo w lo t na junction under non-equilibrium conditions was current r higo s h voltages where deterioratioe th f no described by Grove and Fitzgerald [244]. The current gain and leakage current due to surface descriptio f oxidationo n kinetic Dea y Grovd sb an l e instabilities degraded device performance and yield. e locath [23ld oxidatioan ] f silicoo n n (LOCOS) Concurrently, Rudolf Kriegler championen a d process develope y Koo b d colleague an i e th n i s in-situ furnace gettering methodolog e earlth yn i y late 1960's [245-247], whic s instrumentawa h n i l 1970's removo t , e sodiu welms a othes a l r deleterious fabricatioe th achievemend nan f superioo t 1S C rMO contaminants such as metals and transport these characteristics (see Figur stage ) [247]e6 th r t efo se , mobile iond lifetime-killinan s g metallic impurities e initiatio e MOSFEth th f o n T Dynamic Random from the wafer to the gaseous ambient. This Access Memory (DRAM) era in the early 1970's. procedure becam especialln a e y prevalent industrial The LOCOS process has been the mainstay for technique [225-227]. Typically, abou gaseou% 3 t s CMOS 1C fabricatio r mornfo e tha 0 yearn3 d an s e HCO th 2r C1 1o oxidation i 2 n ambient [227s ]wa only now is shallow trench isolation seriously utilized, simila Robinsoo rt Heimad nan n [228]. Carl challengin utilizatios git n [248]. Osburn studied the improvement of gate oxide mese planad Th aan r processes described above integrity (GOI) via these Cl methodologies [229] as fabricatioe th r noe 1y fo Cb th w y f no pavewa e dth extensivn a par f o t e serie f analyseo s e Verth yn i s Jack Kilby (utilizin e mesgth a methodology) [8,33- Large Scale Integration (VLSI) laboratory of Arnold 36,43 Roberd an ] t Noyce [8,37-39,43] (utilizine gth Reisman [230]. TCE (trichloroethylene) [231] and planar procedure) n 195i , 8 (see Integrated Circuit A (trichloroethaneTC ) [232] were subsequently Beginnings section) and, subsequentlye th , utilized with similar benefits t withoubu , e th t microprocessor [40-42].
18 !b*
i Oxidation
^f' e >SW$ ' ; *
Si
Figur . e6 Conventional LOCOS procedures oxidd pa eA . (SiO2) unde nitride th r e oxidation mask relieves stress, but results in the formation of "bird's beaks" at the oxide edges. Fully recessed oxide patterns (right) exhibits complete "bird's heads" [247]. Reproduced by permission of The Electrochemical Society, Inc.
Integrated Circuit Beginnings "An a revelatiod s thie s allu wa sW . o t n realized that in chasing the vacuum tube, we The challenge after implementation of the had the wrong emphasis.... The net result was junctio t onlno yn o e t 1950transistor th s n i wa s a er that the semiconductor community began to emulate the vacuum tube in as many applications as relax about replacin tube focused gth ean n do possible (without the excessive power generation and developin right n transistoe e gth ow Th .s it n ri reduced operating lifetime)o t exploi t e th bu t, transisto eventualld rdi y replacl tube al eth n ei inherent advantage f solid-stato s e electronicw ne o st speciaw bufe a t l applications magnetroe th , n arenas. The smaller device dimensions required to being one outstanding example. But it took achieve higher frequency operatio e junctioth n i n n decades. In the meantime, semiconductor transistor was confronted, however, with the inherent technology opened up important new fields challenge of the limited power-handling capability thae tubth t e could never have supported.... device'e duth o et s small sizegoae f achievinTh .o l g Havin cleae gth rapplicatio n goaa f o l n a r nfo higher operating frequency and higher power- invention is a powerful stimulus for handling capability t odda seeme e sb wito dt h each innovation. But frequently, the original other. Ross describe situatioe dth follows na s [4]: application turns out not to be the most important." "In the meeting on that day, we were, as was frequentl e caseth y , discussin r problemgou s In a similar vein, Robert Lucky has recently noted in emulating the vacuum tube. R. Wallace "moreove determin o priorirt a thery o n wa s e i e what suddenly said: marketa wil p ti l . It' fundamentasa l instanc chaof eo s in-group dynamics. And that makes it fundamentally "Gentlemen, you've got it all wrong! The difficult to predict future societal behaviors in the advantage of the transistor is that it is adoption of technologies [249]." inherently a small size and low power device. Until the invention of the 1C, electronic This means that you can pack a large number systems were comprise y b individualld y of them in a small space without excessive connecting the various components (vacuum tubes heat generatio achievd nan propagatiow elo n r transistorso , diodes, capacitors, resistord an s delays d that'An . s wha e nee r w logit fo d c inductors) together e commoTh . n featur f theso e e applications. The significance of the transistor endeavor wirine th s g wa stogethe f discreto r d ean replacn that ca i st n no tube ti tha t eca th et bu i t separately packaged device components. Of thingo d s thae vacuuth t m tube could never courses essentiawa t i , l that these componente b s do!" spaced sufficiently clos o e thas systeeth t m propagatio t nbecom no dela e d factoth di ey r limitin e systeth g m speed. This requiree th d
19 miniaturizatio e systemth t f juse devico nno th ,t e buila singl n i t e chi f n-typo p e germanium components. Two major system concerns surfaced wher junctionn p- e s supplie e necessarth d y which required rectification. This involved the capacitance, the body resistance of the piece assembly yield and reliability of a system with of germanium supplie resistive dth e elements thousands of device components, which might be and an alloy transistor at one end of the unacceptably low. Additionally ,e deviceveth f i ne filamentary piec f germaniueo m suppliee dth component errorso n d ,sha there woul multituda e db e necessary amplification." of connections, resulting in the infamous "tyranny of numbers" [35,36,250-253]. "The significant poin s thai t t onlyearo ytw s Lester Hogan reviewe earliese th de b twhay ma t after the first junction transistor was reported attempt o t rectif se "tyrannth y f o numbersy " [reference added [66], research people were conundrum [254]; that is, the patents filed by both already trying to combine resistors, capacitors, Darlington [255] and Oliver [256] in 1952. (diodes d transistoran ) s e intpiecon f oo e Darlington and, apparently, Oliver used a grown semiconductor materia n ordei l o reduct r e junction transistor; both patents integrated several size, to reduce the number of interconnects transistors on one piece of germanium or silicon, an improvo dt e reliability." although they included no passive components. Geoffrey Dumme Royae th f o rl Radar Establishment e alloTh y junction transistors utilizedy b (RRE t Malverna ) , England initiate s solutiodhi o nt Johnson as well as the other, multi-faceted, the integration challenge in 1952 [257] and approache personney b s l familiar wit e state-ofhth - subsequently described his work at the Malvern the-art in the attempts to build an integrated circuit in Components Symposiu n i m195 7 [258d an ] the mid 1950's was perhaps best described by elsewhere [259]. Runyan and Bean [43] have quoted Dummer to be "pioneering stages" ... not capable of Dummer's 195 2n integrate statu"a s a s d approach production [261]." Dummer's review of the work in using a monolithic block comprising" [258,259]: Great Britain and Western Europe is also of interest [262]. "...layer f insulatingso , conducting, rectifying and amplifying materials, the electrical Runya d Beaan n n [43] have commented about functions being connected directl cuttiny yb g Johnson's contribution: ou tvariou e areath f so s layers." "The figures included in a patent ... by Hogan [254 s alsha ]o quote a portiod f o n Harwick Johnson ... (reference [260] added) Dummer's presentation at the 1957 meeting [258]: bear a superficial resemblance to an integrated circuit. However s expressea , e firsth tn i d "... a transistor flip-flop with two emitter sentenc patente th f eo , bot discussioe hth d nan follower outputs—a tota fouf o l r transistorl al s claims relate only to a transistor phase-shift containe chia f silicon d5 i po mil37 5 y n12 sb oscillator: This invention pertains to mils. The semiconductor was doped to form a semiconductor device d particularlan s o t y p-n-p d varioustructurha d san e sections semiconductor phase-shift oscillators and remove leavo dt e thin bridge materiaf so l with devices.' Componentt no isolatio s wa n relatively high resistances. These high- considered so that even if the concepts of the resistance paths forme e collectoth d d an r patent were extende deviceo dt s other thae nth emitter loads of the transistors connected to phase-shift oscillator clase th ,f device o s s that common power supply rails. Other resistors coul made db e woul vere db y limited." were provide filmy b d f resistivo s e material deposited on the surface of the silicon, while s Kilbwa f o Texa yt I s Instruments, capacitors were constructed from thin metallic Incorporated, however fileo patenda wh , t application layers with insulators between." on Februar , 6 195y 9 [8,33-36,43] explicitly "describin concepa g t that allowed, using relatively Concurrently, Harwick Johnson of RCA was simple steps, the fabrication of all the necessary also developin s e solutiohi integratiogth o t n n component e desireth f o sd circuit, both activd an e challenge [260]. Hogan [254] described Johnson's passive, in a single piece of semiconductor and their contribution: interconnection in situ" [43]. Kilby's initial proof of concep phasa s ewa t shift oscillator, built with about s earl "A s 1953ya , Harwick JohnsoA RC f no ten components, in germanium for expediency [43] conceived of a complete phase shift oscillator on September 12, 1958. Wire bonding was utilized to
20 interconnec e componentth t s withi e chith np (see material junctione ,th sucf so h components being Figure 7). near and/or extending to one face of the body,
Figure 7. The first integrated circuit, a phase shift oscillator fabricated in germanium by the mesa process, invented Jacy b . Kilb kS Texaf yo s Instrument 1958n si , courtes Texaf yo s Instruments Incorporated.
weekw fe sA later flip-floa , p circui mads wa t e with components spaced or electrically separated an a patend t application covering both germanium from one another as necessary in the circuit...." and silico s preparewa n d filean dd (Februar, 6 y 1959) firse Th .t commercially available 1C, intended "Figures l-5 n referenca(i 3 adde3 e y b d for binary counter, flip-flop or shift register author) illustrate schematically various circuit applications fabricates wa , silicon di announced nan d components fabricated in accordance with the in March, 196 Texay 0b s Instruments. Runyad an n principles of the present invention in order that Bean [43] have extracted several relevant portions of integratee b they yma d thes intoa yr o , constitute Kilby's patent [33], with appropriate commentary: parts of, a single body of semiconductor material:" "In contrast to the approaches to miniaturization that have been made in the past, the present Runya Bead nan n [43] continue, 'The figured an s inventio s resulte nha totalld an dyw frone ma text describe bulk resistors, diffused resistorsn p , different concept for miniaturization.... In junction capacitors, MOS capacitors, transistors, and accordance with the principles of the invention, diodes. In the press coverage of the March 1959 the ultimate in circuit miniaturization is attained announcement of the Kilby concept, this set of standard using only one material for all circuit elements components was stressed [263]. The patent text an limiteda d numbe f compatiblo r e processing continues:" steps for the production thereof... " "Because all of the circuit designs described U thio pt s point goale th perhape , sar t mucsno h formee abovb n edca fro msingla e materiala , different from those expresse n 195i d y Dummer2b . semiconductor s possibli t i , y physicab e d an l However, to continue with the Kilby patent: electrical shaping to integrate all of them into a single crystal semiconductor wafer containing a "In a more specific conception of the invention, diffused p-n junction, or junctions, and to all component electrin a f so c circui formee ar t d process the wafer to provide the proper circuit r neae io surfacn a relativelon r f o e y thin ancorrece dth t component values...." semiconductor wafer characterize diffusea y db d p-n junction or junctions...." With the subsequent planar process patent submissio y Hoernb n f Fairchilo i d Semiconductor primara s i t "I y objecinventioe th f o t provido nt e Corporatio , 195manne1 o t y e 9 du Ma [15n ri d n no ]an a miniaturized electronic circuit wherein the which the interconnection was described in Kilby's activ d passivan e e circuit componente ar s patent [33] compared to Noyce's 1C patent application, integrated within a body of semiconductor file Jul n , 195do y30 9 [37], Noyc actualls ewa y awarded
21 a patent before Kilby's (April 25, 1961 compared to then referencing the relevant portion of the Noyce June 23, 1964). Figure 8 is a photomicrograph of one claims [37]: e firsth of t planar integrated circuits madt a e Fairchild Semiconductor Corporation [122]; "... an electrical connection to one of said subsequent evolutionary trends have been contacts comprisin gconductoa r adhereno t t
Figur . Photomicrogrape8 firse th tf planao e on rf integrateho d circuits mad Fairchilt ea silicon)n d(i . Thia s si flip-flop circuit (wit transistors)o htw . aluminuSome th f eo m interconnection meta bees lha n damaged durin etchine gth g operatio forno t m circulaa r chi silicof po placno t e int otransistoa n rca modifie havo dt e more leads. (Fro SolimA " d Stat Progress,f eo " Fairchild Camer Instrumend aan t Corporation, 1979) [122]. Reproduce permissioy db IEEEe th f no .
described for ICs [44]. The Texas Instruments 1C said layer (italics entere authory db ) ....e "Th was developed utilizing the mesa process while disagreement centered around whether "laid Intel utilized the subsequent planar process. The down" was equivalent to "adherent to." The legal battle that ensued between Texas Instruments Board of Patent Interference, ruling in Kilby's and Fairchild Semiconductor centered around the favor, asserted that it was. However, a wording associated e witinterconnectioth h n subsequent e Courrulinth f Customo y tb g s scheme. Runyan and Bean [43] have summarized and Patent Appeals (Noyce v. Kilby; Kilby v. essence poine th th f contentio f o teo n betweee th n Noyce, decided November 6, 1969) reversed Kilby and Noyce patent dispute, quoting Kilby's e previouth s ruling d allowean s e Noycth d e patent [33]: claims. (The Supreme Court then refuseo t d review the case.) Contrary to assertions by "Instea f usino de golth g d n i wire 0 7 s somet depen e rulinno th ,whethen d o dgdi r making electrical connections, connections gold could or could not be made suitably may be provided in other ways. For adheren o t silicot n oxidee CourTh . t example, an insulating and inert material specifically commente n thao d t aspecte Th . suc s silicoa h ne evaporate b oxidy ma e d ruling depended on the Court's assessment of e ontsemiconductoth o r circuit wafer t whethesomeonno r o r e reading Kilby's throug a mash k eithe o covet re wafeth r r statement woul e inevitablb d y e drawth o t n completely except at the points where conclusion that the lead should be adherent." electrical contact is to be made thereto, or to cover only selected portions joinine th g Runyan and Bean then continue [43]: e b electricallpoint o t s y connected. Electrically conducting material sucs a h "Probably the most balanced assessment thegoly laide nb dma down (italics entered of Kilby's and Noyce's relative by author) on the insulating material to contributions is contained in the citations of make the necessary electrical connections." the Franklin Institute's 1966 Ballantine Medal award, which they shared. Kilbs ywa credited for 'conceiving and constructing e firsth t working monolithic circuin i t 1958, d Noyc an r ''hi fo es sophistication
22 e oth fmonolithi c circui r fo mort e fabrication, including, for example, self-aligned specialized use, particularl industry.n yi ' " structures and the lightly doped drain (LDD) configuration (see Integrated Circuit Scaling section). Implementatio e 1th C f o concepn s wa t epitaxf o e beeWhild us yimportan ha n ne a eth t somewhat slo consideration wi e anticipateth f no d design consideration for discrete transistors, its real 1yieln Ca f containingdo , say, 100-1000, transistors. impact occurred with the introduction of the bipolar reliabilite Thath , chiis a s tanticipate f pywa o o dt 1C. Prio epitaxyo t r , component isolation withie nth approximate the reliability of a discrete transistor bipola rs achieve1wa C y reverse-biaseb d n p- d degraded by a power to the number of transistors or junction isolation techniques (introduced by Lehovec components [4,264] t turneI . d out, however, that on Apri , 19522 l 9 [266,267] )diffusio y b suc s a h n neithe e yiel th rr reliabilit o d s determinewa y y b d (consider boron) from both the front- and back- random events degrading the transistor uniformity, surface wafee th f ro s unti diffusioe th l n n i front t me s e batcth o ht methoe du f , silicoo dse r npe 1C centen-type e th th f ro e wafer, leaving n-type welln si processing [4] poinn I . f facto t , there tendee b o dt the masked regions. Runyan and Bean have reviewed large areas of a silicon wafer where the yield was the p-n junction isolation technique, including clos 100o et % whil yiele eth othe n di r areas tended Lehovec's contribution to the interconnection to zero [265]. Thus, if the 1C chip area was small methodolog e isolatio th s wela ys a l n techniques compared to the area on the wafer with high utilized by Kilby and Noyce [43]. Kenneth Bean has yielding ICs, the yield would be essentially also describe s epochi d h researc n dielectrio h c independent of the chip size and the number of isolatio r Bipolafo n s witIC rh Paul Gleid man chip r waferspe . With this realization stage s th , ewa Runyan [268,269]. The advent of epitaxial structures, set for the 1C explosion. Ross [4] has quoted Kilby however, offered a new design flexibility in in discussing the buildup of 1C production [34]. component isolation exampler Fo . coule on , d utilizea thin n-type epitaxial layer (sa jimy 3 exampler fo , n )o t shoul"I e greae noteth b d f tdo e thaon t a p-type substrate wafer. Component isolation could strengths of the integrated circuit concept has readily be achieved by boron diffusion through the always been that it could draw on the mainstream e semiconductoth effort f o s r epitaxial layer. Additionally, the fabrication of structures wit hhiga h concentratio f dopanno e th n i t industry. It was not necessary to develop collector decreaso t , e transistor collector resistance, crystal growing or diffusion processes to s achieve localizee wa th y db d diffusio n-typn a f o ne build the first circuits, and new techniques dopant int a p-typo e substrate wafere prioth o t r such as epitaxy would be readily adapted to growth of an n-type epitaxial layer [166-169]. integrated circuit fabrication. Similarly, new device S transistorsMO d sucs a an hs Schottky barrier diodes woul phasee db n di Integrated Circuit Fabrication as they became available. Even todays i t i , difficul o identift t a procesy s tha s usei t d Although the bipolar transistor exhibited better only for integrated circuits. performance characteristics suc s switchinha g speed tha MOSFEe nth T transistor procese th , s simplicity Another strength of the concept was that it and smaller 1C chip size of the latter made it the could dra existinn wo g circuit technologo yt preferred choice for implementation of leading edge produc broaea d rang usefuf eo l devices.... design rule applications [270-272]. The first mass produced commercial MOS DRAM design was Becaus e commonalitth f o e y with existing Intel's 3-transistor silicon-gate PMOS, IK DRAM processes, integrated circuits moved rapidly announce 1970n di . Terman [273 Hodged an ] s [274] into a production status." have reviewe a numbed f o thesr e memory developments prio 1972o t r , oftene referreth s a o dt It might be appropriate, however, to note that small-scale integration (SSI) era (see Table 2 for an developments in 1C fabrication to enhance device approximate taxonom evolvine th f yo g DRAM). performance and scaling have significantly expanded the spectrum of processes uniquely developed for 1C
23 TABL E: DRA2 M Proces 1d C san Evolutio n (circa 1992) Parameter Units ULSI VLSI LSI MSI
Bits/chip Number 10' -10* Vf - 10' 10j - 10' 102 - 103 Design Rule |Lim <1 1-3 3-5 5-10 Power-delay PJ <10'2 10'1 2- 1-10 10 -102 product Mask levels Number 15-20 8-15 6-10 5-6 Chip areaa mm2 50 - 280 25-50 10-25 10 Storage cell (nm) 3.5-12.5 12.5-40 40-90 90-120 capacitor equivalent oxide thickness Junction depth |nm 0.04 - 0.2 0.2-0.5 0.5-1.2 1.2-2
Chi) a p are morr a(o e specifically, active device area) significantly impacts 1C yiel conjunction di n wit defece hth t
densit criticar cmr ype pe l lithographic level (fo numbee rth criticaf ro l levels). 2
e e transitioTh th self-aligne o t n d C oxGat= e oxide capacitanc unir epe t area aluminum d gate thean self-aligneth en d §F= Bulk Fermi energy relative to the the phosphorus doped polysilicon gate adjaceno t t intrinsic Fermi energy (for 10 3 the source and drain junctions via ion holes/cm 0.2- $) = F9V implantation of the junctions, reducing the Miller capacitance [275-279 transitioe th d an ] n Wor= k function difference betweee th n e silicidth o t e metalization scheme [280] were phosphorus doped polysilicon gate and significant achievements enhancing 1C the p-type silicon substrate (taking the performance. An additional device innovation Fermi energe phosphoruth n i y s doped s Heiman'wa s utilizatio a four-termina f o n l polysilicon at the edge of the conduction configuration for the MOSFET by applying a band,
VT)
24 Physically, the substrate near the surface is was the first semiconductor company exclusively reverse biased by the negative VBB body bias, devote fabricatioe th o dt f MOSFEno T ICs. Shortly thereby negating, somewhat influencthe , the of e Id Kthereafteran DRA6 25 Me th ,MOSFE Ts 1Cwa electrons donated by the fixed positive charge, Qf at introduced by Texas Instruments in 1970 and 1972, the interface and increasing VT to the desired range. respectively. Intel introduced the IK PMOSFET t shoulI notee db d tha20e th tF term doe t scalsno e DRA M197n i 0 [291]. Indeed, Intel's IK p-channel with device scaling. (PMOS) DRAM (polysilicon gate), based on a e largeTh r numbe f devico r e functiona n o s three-transistor cell design, initiated the beginning given MOSFET 1e largeCth chid r pan numbe f o r of the MOS memory take-over of the ferrite core MOSFET 1C chipgivea r sfo n wafer diameter were memory marke s implementatioit y b t t computena r instrumenta ensurinn i l eventuae gth l dominancf eo maker Honey well, Inc. [292]. the MOSFET 1C. Fairchild announced a 64 bit The MOSFET 1C revolution, however, really SRAM (six transistor cell design), enhancement- exploded when IBM chose the n-channel silicon mode p-channel MOSFE 196Tn i 4 [44] followey db MOSFET (NMOS), instea slowee th f do r p-channel RCA's annoucemen d productioan n ta f o n silicon MOSFET, for its mainframe memory enhancement mode n-channel MOSFET, alsn i o computer (IBM-370/158) that was delivered in 1964, base n Hofsteio d d Heiman'an n s research 1973. The access time of the NMOS was in the [283]. Frank Wanlass and Sah of Fairchild range of nsec while magnetic core memory's access Semiconductor Corporation disclosed the tims abou e |iswa e. on t InteMOSTEd an l K were Complementary MOS (CMOS) 1C in 1963 early suppliers followed by TI in 1974. TFs design [284,285] followed by RCA Corporation later in the was based on the one-transistor DRAM cell year [286]. Wanlass's initial demonstration circuit, a structure of Bob Dennard [45] and described by transistoo tw r inverter, consume nanowattw fe da s others [293,294], also summarize h [44]Sa .y b d of standby power, compare o t milliwattd f o s Texas Instrument MOSTEd an s K utilize dsinglea - standby power for equivalent bipolar and PMOS metal-word-line/single-diffused-bit line [44,295- gates [287]. Interestingly, Wanlass utilized 297], where the metal was Al and the source and Heiman's back-bias methodology [281] to achieve drain were forme diffusiony db . Texas Instruments an n-channel enhancement mode device e (duth o et utilized POC1 forminn i 3 e diffuseth g d sourcd an e difficult f uncontrolleo y d surface charge t thaa s t drain. The 4K NMOS DRAM cell built by Intel was stag f o technologe o t fabricaty n n-channea e l a single-poly-word-line/single-metal (Al)-bit line enhancement-mode MOS transistor) to work in [44,295-297]. conjunction e witth conventionah l PMOS The 16K DRAM was announced in 1976, with enhancement-mode transistor [287]. three significant changes made compareK 4 e th o dt CMOS eventually became the ultimate DRAM, noted by Sah [44]. These were a reduction of MOSFFET technology, since both p-and n-channel e desigth n rul 8 jaeK m 7- 4 fro e regime mth th r efo enhancement-mode transistor e normallar s y off, DRAM to about the 5 Jim range for the 16K DRAM; drawing only quiescent power; that is, only during e remova th e sourcth f o el diffusion which became the switching process is significant power dissipated knowmergee th s na d one-transistor DRAM celd an l [286,288-290] DRAe Th . M memory arra CMOn yi S an overlapping double polysilicoe th r n fo gate e on , ICs was fabricated in NMOS while the peripheral sourceless transistor (the pass gate) and the second drivers were fabricated in CMOS. U.S. companies for the charge storage capacitor, thereby forming the e samth e tende us desig o t d n rulr bote fo e th h merged one-transistor DRAM cell [44,295-297]e Th . NMOS memory array and the CMOS peripheral wafer diamete s alswa or subsequently increaseo t d devices, accentuatin e latch-uth g p phenomenon, three-inches and, later, change largeo t s r diameters thereb yf epitaxia o requirin e us e l gth structure o t s became commonplace when the number of DRAM minimize latch-up (the coupling of an n-p-n MOS chips became less than about 100 per wafer [298]. transistor with an adjacent p-n-p MOS transistor The subsequent transition to the 64K DRAM around formin n-p-n-n ga r p-n-p-po n thrysistor [289,290]. 1979 did not result in any change in the cell design, t appearI Japanese sth e use largeda r design rulr efo althoug desige hth Ji3 nm 2- reduces rul e ewa th o dt e CMOth S circuitry, therebf yo avoidine us e th g parsubsequentls e rangth wa t d ean y implementen do epitaxial wafers e JapanesTh . e approac s leswa sh four-inch diameter wafers [298]. Four significant 1C costly to fabricate since polished, rather than process changes were discussed by Sah [44]. These epitaxial, silicon wafers were used. Although there include paralleda l plate storage capacitor, rather than were less chips per wafer due to the larger chip size, storag surfaca n ei e inversion layer givo t , higheea r increased yields often negate e geometricath d l charge storage capacitance (about 32 fF to store «106 limitation. MOSTEK, Incorporated, formed in 1968, electron VV DD5 t )sa fro smale mth onele areth f -ao
25 transistor DRAM cell, since higher capacitancs wa e case trence th , h dept spatiae s abouth hi jud 0 lm1 an t require reduco dt sofe eth t noiserroro t e es du electron s area is about 6-9 Jim2. Chatterjee and colleagues at generated by alpha particles from the package materials Texas Instruments introduced a structure which placed of the chip, cosmic rays and other noise sources [44]; a the pass transistor inside the trench to further conserve dual dielectric for the charge storage capacitor, utilizing silicon real estate [300,301]. highee th r dielectric constan f silicoo t n nitride formed DRAM 4 introducea e Mer Th sub-microe dth n by chemical vapor deposition (CVD) on thermally design rule regim8 ju,0. m t a ewitD storag 3- h e grown silicon dioxid enhanco et composite eth e storage capacitors e type d featureTh . an s f storago s e cell medium's dielectric constan reduco t d ean t pinholen si designs have subsequently proliferated [44,302,303]. the thinner silicon dioxide (not all DRAM The decreasing design rules result in higher speed manufacturers utilized this option); plasma etch and reduced power-delay produc resula s a tlowef o t r technology to produce steeper walls or trenches to capacitanc d currenan e t e [44]power-delaTh . y reduce tapered structures which take up silicon real produc additionalls ti y reduce reduciny db g VDD [44]. estate (chi poptican a area d )lan wafer steppe reduco rt e The DRAM became the test vehicle par the design rules from three to less than two microns. excellenc o t advance e silicoth e n 1C process Rideout [296 Chatterjed an ] e [299] have also reviewed technology because of its repetitive memory these DRAM advances. structure morn I . e recent years, however, especially The 256K DRAM further reduced the design rule aftee U.Sth r . makers retreated fro ma significan t 1.5-e th o 2t |nm rang introduced ean d refractory metal e positiomanufacturth n i n f o DRAMSe , their silicides to reduce the interconnect wiring delay [44] expertise in the fabrication of microprocessors has aluminud an m meta r doublfo l tripld ean e polysilicon propelled the logic and microprocessor family as test technologies. The M-bit DRAM era, initially a shrink vehicle drivers. Nevertheless DRAe th , M continues of the original 2 u.m 256K DRAM design, approached to drive the extendibility of personal computers (PCs) |ii1 m design rules (see Tabl ; mor2) e e importantly, vis-a-vi memore sth y content. however, was the introduction of two three- dimensional (3-D) trench charge storage capacitors Integrated Circuit Scaling (see Figures 9 and 10). Sah has noted that the goal of Gordon Moore's remarkedly prescient assessment thes capacitoD e3- r designreduco t s planae eth wa s r of memory component growth in 1965, initially based area of the storage capacitor while maintaining the on bipolar and then MOS memory density, observed storage capacitanc t morea e tha fholo 2 Ft n3 d more that a semilog graph of the number of bits on a memory 6 than 10 electronlimio t V t Va 5 sof Dt f sa Do t errors 1C versus the date of initial availability was a straight [44]. In the stack capacitor design, multilayers of line, representing almos doublina t r yeagpe r [50-53]. conductors r d insulatorAlo (polan )i S y s (silicon Accordingly, a quadrupling was deduced every two dioxide and silicon nitride) are stacked on top of the years (consistent with the needs of the system houses) pass transistor. In the trench capacitor design, a trench and subsequently modified to ~ 3 years around the mid- storagS isMO etcheesilicon e a capacito th d n di nan r later 1970 currentld san y year 4 take3- s n a base a n do is fabricated in the trench, adjacent to the pass 1995 assessment [53]. This analysis became enshrines da transistor which remain planae th n rso surface thin I . s
Figure 9. One Mbit CMOS DRAM chip, courtesy of Texas Instruments Incorporated.
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