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High Performance Power Distribution Networks with On-Chip Decoupling Capacitors for Nanoscale Integrated Circuits

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High Performance Power Distribution Networks with On-Chip Decoupling Capacitors for Nanoscale Integrated Circuits High Performance Power Distribution Networks with On-Chip Decoupling Capacitors for Nanoscale Integrated Circuits by Mikhail Popovich Submitted in Partial Ful¯llment of the Requirements for the Degree Doctor of Philosophy Supervised by Professor Eby G. Friedman Department of Electrical and Computer Engineering The College School of Engineering and Applied Sciences University of Rochester Rochester, New York 2007 ii It has become appallingly obvious that our technology has exceeded our humanity. | Albert Einstein iii Dedication This work is dedicated to my parents, Mr. Evgeniy Antonovich and Mrs. Lyud- mila Mikhailovna, my wife Oksana, and my daughter Elizabeth Michelle. iv Curriculum Vitae Mikhail Popovich was born in Izhevsk, Russia in 1975. He received the B.S. degree in electrical engineering from Izhevsk State Technical University, Izhevsk, Russia in 1998, and the M.S. degree in electrical and computer engineering from the University of Rochester, Rochester, NY in 2002, where he is completing the Ph.D. degree in electrical engineering. He was an intern at Freescale Semiconductor Corporation, Tempe, AZ, in the summer 2005, where he worked on signal integrity in RF and mixed-signal ICs and developed design techniques and methodologies for placing distributed on-chip de- coupling capacitors. His professional experience also includes characterization of sub- strate and interconnect crosstalk noise in CMOS imaging circuits for the Eastman Kodak Company, Rochester, NY. He has authored a book and several conference and journal papers in the areas of power distribution networks in CMOS VLSI circuits, placement of on-chip decoupling capacitors, and the inductive properties of on-chip v interconnect. His research interests are in the areas of on-chip noise, signal integrity, and interconnect design including on-chip inductive e®ects, optimization of power distribution networks, and the design of on-chip decoupling capacitors. Mr. Popovich received the Best Student Paper Award at the ACM Great Lakes Symposium on VLSI in 2005 and the GRC Inventor Recognition Award from the Semiconductor Research Corporation in 2007. Publications Book 1. M. Popovich, A. V. Mezhiba, and E. G. Friedman, Power Distribution Networks with On-Chip Decoupling Capacitors, Springer Publishing Company (in press). Journal Papers 2. M. Popovich, R. M. Secareanu, E. G. Friedman, and O. L. Hartin, \E±cient Placement of Distributed On-Chip Decoupling Capacitors in Nanoscale ICs," IEEE Transactions on Very Large Scale Integration (VLSI) Systems (in sub- mission). 3. M. Popovich, M. Sotman, A. Kolodny, and E. G. Friedman, \E®ective Radii of On-Chip Decoupling Capacitors," IEEE Transactions on Very Large Scale Integration (VLSI) Systems (in submission). 4. M. Popovich, E. G. Friedman, M. Sotman, and A. Kolodny, \On-Chip Power Distribution Grids with Multiple Supply Voltages for High Performance Inte- grated Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems (in submission). vi 5. M. Popovich and E. G. Friedman, \Decoupling Capacitors for Multi-Voltage Power Distribution Systems," IEEE Transactions on Very Large Scale Integra- tion (VLSI) Systems, Vol. 14, No. 3, pp. 217{228, March 2006. Conference Papers 6. M. Popovich, R. M. Secareanu, E. G. Friedman, and O. L. Hartin \Distributed On-Chip Decoupling Capacitors," ACM International Conference on Nano- Networks (in submission). 7. M. Popovich, R. M. Secareanu, E. G. Friedman, and O. L. Hartin, \E±cient Placement of Distributed On-Chip Decoupling Capacitors in Nanoscale ICs," Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, November 2007 (in press). 8. M. Sotman, A. Kolodny, M. Popovich, and E. G. Friedman, \On-Die Decoupling Capacitance: Frequency Domain Analysis of Activity Radius," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 489{492, May 2006. 9. M. Popovich, E. G. Friedman, M. Sotman, A. Kolodny, and R. M. Secareanu, \Maximum E®ective Distance of On-Chip Decoupling Capacitors in Power Dis- tribution Grids," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 173{179, April/May 2006. 10. M. Sotman, M. Popovich, A. Kolodny, and E. G. Friedman, \Leveraging Sym- biotic On-Die Decoupling Capacitance," Proceedings of the IEEE Conference on Electrical Performance of Electronic Packaging, pp. 111{114, October 2005. 11. M. Popovich, E. G. Friedman, R. M. Secareanu, and O. L. Hartin, \On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits," Proceedings of the IEEE International SOC Conference, pp. 309{312, September 2005. vii 12. M. Popovich and E. G. Friedman, \Noise Coupling in Multi-Voltage Power Distribution Systems with Decoupling Capacitors," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 620{623, May 2005. 13. M. Popovich, E. G. Friedman, M. Sotman, and A. Kolodny, \On-Chip Power Distribution Grids with Multiple Supply Voltages for High Performance Inte- grated Circuits," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 2{7, April 2005 (received the best student paper award for GLSVLSI 2005). 14. M. Popovich and E. G. Friedman, \Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems," Proceedings of the IEEE Interna- tional Symposium on Quality Electronic Design, pp. 334{339, March 2005. 15. M. Popovich and E. G. Friedman, \Impedance Characteristics of Decoupling Capacitors in Multi-Power Distribution Systems," Proceedings of the IEEE In- ternational Conference on Electronics, Circuits, and Systems, pp. 160{163, De- cember 2004. 16. M. Popovich and E. G. Friedman, \Decoupling Capacitors for Power Distribu- tion Systems with Multiple Power Supplies," Proceedings of the 28th Annual IEEE EDS/CAS Activities in Western New York Conference, p. 9, November 2004. 17. M. Popovich and E. G. Friedman, \Decoupling Capacitors for Power Distribu- tion Systems with Multiple Power Supply Voltages," Proceedings of the IEEE International SOC Conference, pp. 331{334, September 2004. 18. M. Margala, R. Alonzo, G.-Q. Chen, B. J. Jasionowski, K. Kraft, M. Lay, J. Lindner, M. Popovich, and J. Suss, \Low-Voltage Power-E±cient Adder De- sign," Proceedings of the IEEE Midwest Symposium on Circuits and Systems, pp. 461{464, August 2002. viii Patent Disclosures 19. M. Popovich, R. M. Secareanu, E. G. Friedman, and O. L. Hartin, \Distributed On-Chip Decoupling Capacitor Network," US patent pending. 20. M. Popovich and E. G. Friedman, \Method and Design Flow for E®ective Place- ment of On-Chip Decoupling Capacitors Determined by Maximum E®ective Radii," US patent pending (received 2007 GRC Inventor Recognition Award from the Semiconductor Research Corporation). 21. M. Popovich, E. G. Friedman, R. M. Secareanu, and O. L. Hartin, \Method and Apparatus to Reduce Noise Fluctuations in On-Chip Power Distribution Networks," US patent pending. 22. R. M. Secareanu, M. Popovich, W. Parmon, and O. L. Hartin, \Design of a Distributed On-Chip Decoupling Capacitor Network { Correlation between a Distributed Capacitor and Circuit Demands," Freescale defensive patent, Au- gust 11, 2006, http://www.ip.com/pubview/IPCOM000138959D. ix Acknowledgments The unforgettable memory and experience that I have had at the University of Rochester will greatly embellish the rest of my life. It is impossible to acknowledge all those people who have made my life in Rochester joyful and meaningful. If your name is not listed, rest assured that my gratitude is not less than for those listed below. First of all, I would like to express my deepest appreciation to my academic advisor, Professor Eby G. Friedman, for his generous mentorship in my academic and personal growth. He was the one who gave me a chance to perform this research and believed in my success. His professionalism, commitment, and kindness have brought the best out of me. Thank you for making my research experience fruitful and highly enjoyable. I thank Professors Paul Ampadu, Michael Huang, and Daniel Stefankovic for serving on my proposal and defense committees and for their valuable advice and comments regarding this dissertation. I would also like to thank Professor David x H. Albonesi for his support. I would express my appreciation to the University of Rochester and the Department of Electrical and Computer Engineering for providing a unique environment which encourages high quality research. I would also like to thank all of the department secretaries and computer sta® for their active support. Special thanks to Prof. Avinoam Kolodny and Michael Sotman from Technion { Israel Institute of Technology for their collaboration and support. Their generous feedback has greatly improved my work. I am grateful to Olin L. Hartin, Marie Burnham, and Radu M. Secareanu for giving me the opportunity of a summer internship in Freescale Semiconductor Corporation and for their collaboration and suggestions. I would like to thank those previous and current members in the High Performance VLSI/IC Design and Analysis Laboratory: Andrey Mezhiba, Dimitris Velenis, Volkan Kursun, Boris Andreev, Weize Xu, Magdy El-Moursy, Junmou Zhang, Guoqing Chen, Vasilis Pavlidis, Jonathan Rosenfeld, Emre Salman, Renatas Jakushokas, and Ioannis Savidis for their help, advise, and companionship. I would also like to thank RuthAnn Williams for administrative support and for giving a spark to routine life in the lab. Last, but not least, I want to thank my wife Oksana and my daughter Elizabeth for all of the support that they give me and happiness
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