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University of Cincinnati UNIVERSITY OF CINCINNATI Date:___________________05/22/2006 I, _________________________________________________________,Yajun An hereby submit this work as part of the requirements for the degree of: Master of Science in: Electrical Engineering It is entitled: Device Modeling Study of Vertical Channel SiGe MOSFETs This work and its defense approved by: Chair: _______________________________Dr. Kenneth P. Roenker _______________________________Dr. Marc Cahay _______________________________Dr. Punit Boolchand _______________________________ _______________________________ Device Modeling Study of Vertical Channel SiGe MOSFETs A thesis submitted to the Division of Graduate Studies and Research of the University of Cincinnati in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE in the Department of Electrical and Computer Engineering and Computer Science of the College of Engineering May, 2006 by Yajun An B.E.(Mechanical and Electronics), Department of Mechanical and Electronics Engineering, Beijing Institute of Technology, Beijing, China, 1995. Thesis Advisor and Committee Chair: Dr. Kenneth P. Roenker Committee Members: Dr. Marc Cahay, Dr. Punit Boolchand Abstract Silicon planar MOSFETs are fast approaching their scaling limitations and new device structures are being investigated with the intention to replace the current planar silicon-only MOSFET. One of the possible alternatives to traditional Si planar MOSFET structure that is being explored is the vertical channel MOSFET. The recent development of graded Silicon-Germanium is a useful additional tool that has made shorter vertical channel MOSFETs attractive. Fabrication of a graded Silicon-Germanium vertical channel MOSFET has been explored in recent years that does not need sophisticated lithography and whose fabrication is compatible with a standard CMOS process. The transistors exhibited better performance than Si control device, and so is a possible candidate for extending the evolution of CMOS technology. In this study, we investigated both SiGe and Si vertical channel MOSFETs using device modeling. The fabrication of the transistors was modeled using commercial fabrication process simulator DIOS and the device characteristics were simulated with a commercial device simulator DESSIS. The electrical characteristics of the SiGe vertical channel MOSFET and Si control vertical channel NMOSFET were examined and compared. The SiGe vertical NMOSFET shows high transconductance both in the linear and saturation regions, better drive capability, and reduced subthreshold swing than that of Si control vertical MOSFET. However, it shows a worse DIBL (drain induced barrier lowering) than that of Silicon control MOSFET because SiGe MOSFET has a lower barrier at the source end of channel due to the peak Ge concentration. Both the SiGe MOSFET and Si control MOSFET show good RF characteristics; the SiGe MOSFET has a higher cutoff frequency than Si control MOSFET because of the enhancement of the electron mobility by the Ge. A peak cutoff frequency of about 51 GHz was obtained when the gate oxide thickness was reduced to 4 nm for the optimized SiGe transistor. Channel length scaling was also investigated for the transistors; the channel length was scaled by changing process simulation conditions, both devices showed very good characteristics for the channel length greater than 0.1um. But both transistors show severe short channel effects after the channel was shrunk to less than 0.1um, due to increased background doping from the source and drain in the channel, the RF characteristics of transistors also became worse when the channel was shortened, where the degraded mobility of the electron in the channel suppressed the transistor’s speed. Acknowledgements I would like to express my gratitude to the faculty and students of the University of Cincinnati for making my stay here a pleasant experience. In particular, I would like to thank Dr. Kenneth. P. Roenker for guiding and helping me complete this work. Thanks are due to Dr Cahay and Dr Boolchand for agreeing to be part of my thesis defensecommittee and for their help in clarifying a lot of questions I had during my period of stay here. I would like to thank my former and present lab members, Aniket, Aravind,Yuba, Joe ,Subu and Martin for the various discussions we had, both technical and otherwise. It was fun to be part of this research group and share the time in the laboratory. Special thanks to my parents and my wife for helping me successfully overcome some difficult times during the period of my stay here. Contents 1. Introduction 14 1.1 Planar MOSFET Fabrication and Design Considerations 15 1.1.1 Planar MOSFET Fabrication 16 1.1.2 MOSFET Design Considerations 22 1.2 Silicon Vertical Channel MOSFET and Strained Silicon- 30 Germanium Vertical Channel MOSFET 1.3 Reported Results for Vertical Silicon MOSFET and 35 Strained SiGe Vertical MOSFET 1.4 Purpose of Thesis 36 1.5 Organization of Thesis 37 2. Material Properties of Silicon-Germanium and Simulation 44 Software 2.1 Introduction To ISE TCAD Simulation Procedure 44 2.2 DIOS and Relative Procedures and Models of Process 46 Simulation 2.2.1 Etching 48 2.2.2 Deposition 49 2.2.3 Masking and Lithography 49 2.2.4 Implantation 50 2.2.5 Diffusion 52 1 2.2.6 Oxidation 53 2.3 DESSIS and Device Physics Models for Device Simulation 54 2.3.1 Basic Equations for Semiconductor Device 55 Simulation 2.3.2 Transport Models 57 2.3.2.1 Drift-Diffusion Model 57 2.3.2.2 Hydrodynamic Model 58 2.3.3 Generation-Recombination Models 59 2.3.3.1 Shockley-Read-Hall Recombination 59 2.3.3.2 SRH Recombination Doping-dependent 60 Model 2.3.3.3 Auger Recombination 61 2.3.4 SiGe Mobility and Mobility Models in DESSIS 62 2.3.4.1 SiGe Mobility 62 2.3.4.2 Mobility Models in DESSIS 64 2.3.4.3 Doping-Dependent Mobility Degration 67 2.3.4.4 High Field Saturation 70 2.3.4.5 Mobility Degradation at Interfaces 71 2.3.5 SiGe Band Structure and Bandgap Model in 73 DESSIS 2.3.5.1 SiGe Bandgap 74 2.3.5.2 SiGe Bandgap Models in DESSIS 80 2.3.5.3 Electron Affinity 82 2 2.3.5.4 Energy Bandgap Narrowing and Electron Affinity Changes with Doping 83 2.3.6 Mechanical Stress Modeling 84 3. 3.1 Fabrication Simulation Results and Comparisons 94 3.1.1 MOSFET Design Considerations 95 3.1.2 Fabrication Designs and Simulation 96 3.1.3 Strained SiGe vertical channel NMOSFET 100 Fabrication and Si control vertical NMOSFET Fabrication Steps 3.1.4 Final Structure of Strained SiGe Si Vertical Channel 104 NMOSFETs 3.1.4.1 Structure of Transistors 104 3.1.4.2 Doping Profile in the Channel and Source 108 Regions 3.1.4.3 Germanium Mole Fraction Channel 112 3.1.4.4 Bandgap and Band Structures of SiGe 114 MOSFET Channel 3.1.4.5 Electron Mobility in the Channel 118 3.2 Device Simulation Results 118 3.2.1 Threshold Voltage(VT) 119 3.2.2 Transconductance 121 3.2.3 Output Current – Voltage Characteristics 124 3 3.2.4 Subthreshold Characteristic 124 3.2.5 Drain Induced Barrier Lowering (DIBL) 129 3.2.6 RF Simulation Results 131 4. Optimization of Device Fabrication and Device Design for 136 Vertical Graded Channel Silicon-Germanium MOSFETs 4.1 Channel Impurity Ion Implantation and Gate Oxide Thickness 137 Optimization 4.1.1 Threshold Voltage Optimization 137 4.1.2 Gate Oxide Optimization 146 4.1.3 Comparison of Optimized SiGe MOSFET and Si Control 155 MOSFET 4.2 Effect of Variation in Germanium More Fraction on 162 Simulation Results of SiGe MOSFET 4.3 Channel Length Scaling of SiGe MOSFET 172 4.4 Summary and Conclusions 184 5. Conclusions and Future Work 186 5.1 Generalized Conclusions 186 5.2 Future Work 187 4 List of Figures 1.1 MOSFET Channel Length vs. Power Supply, Threshold Voltage (V) and Gate-Oxide Thickness 1.2 A typical sub-0.5 µm planar CMOS front-end-of-the-line fabrication flow 1.3 Modern MOSFET structure 1.5 Short-channel, threshold roll-off for N-channel (a) and P-channel (b) MOSFETs versus channel length 1.6 Short-channel, threshold roll-off for N-channel (a) and P-channel (b) MOSFETs band structures DIBL effect 1.7 Log Id vs Vg when Vds is change 1.8 Comparison of long-channel MOSFET and short-channel MOSFET Id-Vd curves 1.9 Drift and diffusion current components of current in an Id-Vgs plot. The sum of these two components is the total drain current represented by a solid line 1.10 FN tunneling and direct tunneling 1.11 Three dimensional views of a FinFET (a) TriGate (b) Ω-gate (c) and Quadruple-gate (d) device 1.12 out of the vertical double gate MOSFET N type Silicon Control Vertical MOSFET (left) and Strained Silicon-Germanium Control MOSFET (right) 2.1 The simulation flow used in this thesis under GENESISe 2.2 List of primary distribution functions for ion implantation 5 2.3 Hierarchy of semi-classical transport approaches 2.4 Variation of the electron mobility as a function of increasing Germanium content 2.5 Majority and minority carrier electron mobilities as a function of Germanium content in Silicon-Germanium thin films on Silicon substrate for different impurity concentrations 2.6 Inversion layer mobility for electrons in silicon as a function of the magnitude of the transverse electric field 2.7 Equivalent conduction band minima in Germanium (8) and Silicon (6) 2.8 Energy bandgap for Si1-xGex alloy as a function of the composition for the bulk semiconductor. The solid line is from the measurement results; the broken line is obtained from analytical expression. 2.9 Splitting of the valence band due to biaxial stress (a) and conuction band (b) 2.10 Energy bandgap for strained and unstrained Silicon-Germanium with increasing Germanium mole fraction 2.11 Effective bandgap reductions in p-type SiGe as a function of the Germanium mole fraction for several doping levels 2.12 Bandgap reductions in n-type Si1-xGex 3.1 Schematic view of the strained vertical channel SiGe MOSFET of Chen et al.
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