UNIVERSITY OF CINCINNATI
Date:______05/22/2006
I, ______,Yajun An hereby submit this work as part of the requirements for the degree of: Master of Science in: Electrical Engineering
It is entitled: Device Modeling Study of Vertical Channel SiGe MOSFETs
This work and its defense approved by:
Chair: ______Dr. Kenneth P. Roenker ______Dr. Marc Cahay ______Dr. Punit Boolchand ______Device Modeling Study of Vertical Channel
SiGe MOSFETs
A thesis submitted to the
Division of Graduate Studies and Research of
the University of Cincinnati
in partial fulfillment of the
requirements for the degree of
MASTER OF SCIENCE
in the Department of
Electrical and Computer Engineering and Computer Science
of the College of Engineering
May, 2006
by
Yajun An
B.E.(Mechanical and Electronics), Department of Mechanical and
Electronics Engineering,
Beijing Institute of Technology, Beijing, China, 1995.
Thesis Advisor and Committee Chair: Dr. Kenneth P. Roenker
Committee Members: Dr. Marc Cahay, Dr. Punit Boolchand
Abstract
Silicon planar MOSFETs are fast approaching their scaling limitations and new device structures are being investigated with the intention to replace the current planar silicon-only MOSFET. One of the possible alternatives to traditional Si planar MOSFET structure that is being explored is the vertical channel MOSFET. The recent development of graded Silicon-Germanium is a useful additional tool that has made shorter vertical channel MOSFETs attractive. Fabrication of a graded Silicon-Germanium vertical channel MOSFET has been explored in recent years that does not need sophisticated lithography and whose fabrication is compatible with a standard CMOS process. The transistors exhibited better performance than Si control device, and so is a possible candidate for extending the evolution of CMOS technology. In this study, we investigated both SiGe and Si vertical channel MOSFETs using device modeling. The fabrication of the transistors was modeled using commercial fabrication process simulator DIOS and the device characteristics were simulated with a commercial device simulator DESSIS. The electrical characteristics of the SiGe vertical channel MOSFET and Si control vertical channel NMOSFET were examined and compared. The SiGe vertical NMOSFET shows high transconductance both in the linear and saturation regions, better drive capability, and reduced subthreshold swing than that of Si control vertical MOSFET. However, it shows a worse DIBL (drain induced barrier lowering) than that of Silicon control MOSFET because SiGe MOSFET has a lower barrier at the source end of channel due to the peak Ge concentration. Both the SiGe MOSFET and Si control MOSFET show good RF characteristics; the SiGe MOSFET has a higher cutoff frequency than Si control MOSFET because of the enhancement of the electron mobility by the Ge. A peak cutoff frequency of about 51 GHz was obtained when the gate oxide thickness was reduced to 4 nm for the optimized SiGe transistor. Channel length scaling was also investigated for the transistors; the channel length was scaled by changing process simulation conditions, both devices showed very good characteristics for the channel length greater than 0.1um. But both transistors show severe short channel effects after the channel was shrunk to less than 0.1um, due to increased background doping from the source and drain in the channel, the RF characteristics of transistors also became worse when the channel was shortened, where the degraded mobility of the electron in the channel suppressed the transistor’s speed.
Acknowledgements
I would like to express my gratitude to the faculty and students of the
University of Cincinnati for making my stay here a pleasant experience.
In particular, I would like to thank Dr. Kenneth. P. Roenker for guiding and helping me complete this work. Thanks are due to Dr Cahay and Dr Boolchand for agreeing to be part of my thesis defensecommittee and for their help in clarifying a lot of questions I had during my period of stay here.
I would like to thank my former and present lab members, Aniket,
Aravind,Yuba, Joe ,Subu and Martin for the various discussions we had, both
technical and otherwise. It was fun to be part of this research group and share
the time in the laboratory.
Special thanks to my parents and my wife for helping me successfully
overcome some difficult times during the period of my stay here.
Contents
1. Introduction 14
1.1 Planar MOSFET Fabrication and Design Considerations 15
1.1.1 Planar MOSFET Fabrication 16
1.1.2 MOSFET Design Considerations 22
1.2 Silicon Vertical Channel MOSFET and Strained Silicon- 30
Germanium Vertical Channel MOSFET
1.3 Reported Results for Vertical Silicon MOSFET and 35
Strained SiGe Vertical MOSFET
1.4 Purpose of Thesis 36
1.5 Organization of Thesis 37
2. Material Properties of Silicon-Germanium and Simulation 44
Software
2.1 Introduction To ISE TCAD Simulation Procedure 44
2.2 DIOS and Relative Procedures and Models of Process 46
Simulation
2.2.1 Etching 48
2.2.2 Deposition 49
2.2.3 Masking and Lithography 49
2.2.4 Implantation 50
2.2.5 Diffusion 52
1 2.2.6 Oxidation 53
2.3 DESSIS and Device Physics Models for Device Simulation 54
2.3.1 Basic Equations for Semiconductor Device 55
Simulation
2.3.2 Transport Models 57
2.3.2.1 Drift-Diffusion Model 57
2.3.2.2 Hydrodynamic Model 58
2.3.3 Generation-Recombination Models 59
2.3.3.1 Shockley-Read-Hall Recombination 59
2.3.3.2 SRH Recombination Doping-dependent 60
Model
2.3.3.3 Auger Recombination 61
2.3.4 SiGe Mobility and Mobility Models in DESSIS 62
2.3.4.1 SiGe Mobility 62
2.3.4.2 Mobility Models in DESSIS 64
2.3.4.3 Doping-Dependent Mobility Degration 67
2.3.4.4 High Field Saturation 70
2.3.4.5 Mobility Degradation at Interfaces 71
2.3.5 SiGe Band Structure and Bandgap Model in 73
DESSIS
2.3.5.1 SiGe Bandgap 74
2.3.5.2 SiGe Bandgap Models in DESSIS 80
2.3.5.3 Electron Affinity 82
2 2.3.5.4 Energy Bandgap Narrowing and
Electron Affinity Changes with Doping 83
2.3.6 Mechanical Stress Modeling 84
3. 3.1 Fabrication Simulation Results and Comparisons 94
3.1.1 MOSFET Design Considerations 95
3.1.2 Fabrication Designs and Simulation 96
3.1.3 Strained SiGe vertical channel NMOSFET 100
Fabrication and Si control vertical NMOSFET
Fabrication Steps
3.1.4 Final Structure of Strained SiGe Si Vertical Channel 104
NMOSFETs
3.1.4.1 Structure of Transistors 104
3.1.4.2 Doping Profile in the Channel and Source 108
Regions
3.1.4.3 Germanium Mole Fraction Channel 112
3.1.4.4 Bandgap and Band Structures of SiGe 114
MOSFET Channel
3.1.4.5 Electron Mobility in the Channel 118
3.2 Device Simulation Results 118
3.2.1 Threshold Voltage(VT) 119
3.2.2 Transconductance 121
3.2.3 Output Current – Voltage Characteristics 124
3 3.2.4 Subthreshold Characteristic 124
3.2.5 Drain Induced Barrier Lowering (DIBL) 129
3.2.6 RF Simulation Results 131
4. Optimization of Device Fabrication and Device Design for 136
Vertical Graded Channel Silicon-Germanium MOSFETs
4.1 Channel Impurity Ion Implantation and Gate Oxide Thickness 137
Optimization
4.1.1 Threshold Voltage Optimization 137
4.1.2 Gate Oxide Optimization 146
4.1.3 Comparison of Optimized SiGe MOSFET and Si Control 155
MOSFET
4.2 Effect of Variation in Germanium More Fraction on 162
Simulation Results of SiGe MOSFET
4.3 Channel Length Scaling of SiGe MOSFET 172
4.4 Summary and Conclusions 184
5. Conclusions and Future Work 186
5.1 Generalized Conclusions 186
5.2 Future Work 187
4 List of Figures
1.1 MOSFET Channel Length vs. Power Supply, Threshold Voltage (V)
and Gate-Oxide Thickness
1.2 A typical sub-0.5 µm planar CMOS front-end-of-the-line fabrication flow
1.3 Modern MOSFET structure
1.5 Short-channel, threshold roll-off for N-channel (a) and P-channel (b)
MOSFETs versus channel length
1.6 Short-channel, threshold roll-off for N-channel (a) and P-channel (b)
MOSFETs band structures DIBL effect
1.7 Log Id vs Vg when Vds is change
1.8 Comparison of long-channel MOSFET and short-channel MOSFET Id-Vd
curves
1.9 Drift and diffusion current components of current in an Id-Vgs plot. The
sum of these two components is the total drain current represented by a
solid line
1.10 FN tunneling and direct tunneling
1.11 Three dimensional views of a FinFET (a) TriGate (b) Ω-gate (c) and
Quadruple-gate (d) device
1.12 out of the vertical double gate MOSFET N type Silicon Control Vertical
MOSFET (left) and Strained Silicon-Germanium Control MOSFET (right)
2.1 The simulation flow used in this thesis under GENESISe
2.2 List of primary distribution functions for ion implantation
5 2.3 Hierarchy of semi-classical transport approaches
2.4 Variation of the electron mobility as a function of increasing Germanium content
2.5 Majority and minority carrier electron mobilities as a function of Germanium
content in Silicon-Germanium thin films on Silicon substrate for different impurity
concentrations
2.6 Inversion layer mobility for electrons in silicon as a function of the magnitude of
the transverse electric field
2.7 Equivalent conduction band minima in Germanium (8) and Silicon (6)
2.8 Energy bandgap for Si1-xGex alloy as a function of the composition for the
bulk semiconductor. The solid line is from the measurement results; the
broken line is obtained from analytical expression.
2.9 Splitting of the valence band due to biaxial stress (a) and conuction band (b)
2.10 Energy bandgap for strained and unstrained Silicon-Germanium with increasing
Germanium mole fraction
2.11 Effective bandgap reductions in p-type SiGe as a function of the Germanium
mole fraction for several doping levels
2.12 Bandgap reductions in n-type Si1-xGex
3.1 Schematic view of the strained vertical channel SiGe MOSFET of Chen et
al.
3.2 SiGe MOSFET fabrication flow
3.3 Process steps and device profiles of the SiGe vertical Channel MOSFETs
fabrication process
3.4 Schmetic diagram of SiGe vertical MOSFET fabrication including (a)
transistor profile with contacts and grids and (b) close-up of Channel, gate
6 oxide and ploysilicon gate
3.5 Transistor structure for (a) SiGe MOSFET and Si control MOSFET and (b)
reported strained vertical channel SiGe MOSFET of Chen et al.; the
shading of source, drain,substrate and channel in Figure 3.5(a) means net
doping level of impurities, darker area means heavier impurity doping in
this area, the right hand side legend is the shading and net impurity
concentration contrast.
3.6 (a) Net doping in channel for SiGe MOSFET and Si control MOSFET and
(b) Ge two dimensional profile in the SiGe MOSFET. The legend of (a)
shows the net doping. The legend of (b) shows the contrast of color and
Ge mole fraction.
3.7 Cross-section of the device for the gate region showing the about 10nm
gate oxide thickness for the SiGe MOSFET and Si control MOSFET
3.8 Arsenic (a) and Boron (b) distributions in SiGe MOSFET and Si control
MOSFET channels. Where y=0.012 is the top surface of the source
region.
3.9 Boron and Arsenic impurity distributions in channels of both transistors
3.10 SIMS profiles along the vertical channel for the SiGe PMOSFET reported
by Chen et al.
3.11 Germanium distributions along the channel of SiGe MOSFET shown using
a logarithmic scale (a) and a linear scale (b)
3.12 Energy Bandgap along the channel of SiGe MOSFET
7 3.13 Conduction band (a) and valence band (b) profile along the channel of
SiGe MOSFET and Si control MOSFET
3.14 Conduction band profile of the Si and SiGe vertical channel MOSFET
along the channel reported by Chen et al.
3.15 Electron mobility profile along the channels of SiGe and Si transistors
3.16 Id vs Vg curves of SiGe and Si transistors
3.17 Id vs Vg curves of SiGe and Si MOSFET reported by Chen et al.
3.18 Transconductance of SiGe MOSFET and Si control MOSFET at VDS=0.1v
(a) and VDS=2.5v (b)
3.19 Transconductance comparison of the SiGe NMSOFET and Si control
MOSFET reported results: (a) VDS=0.1v ;(b) VDS=2.5v
3.20 OutSiGe MOSFET and Si control MOSFET IDS vs VDS curves for our
devices (a) and results reported by Chen et al.
3.21 Log Id vs Vg for SiGe MOSFET and Si control MOSFET
3.22 Subthreshold characteristics of SiGe and Si MOSFET reported by Chen
et al.
3.23 SiGe and Si transistors Subthreshold characteristics for Vds=0.1V and
1.1V
3.24 Electrical fields along the channels of SiGe MOSFET and Si control
MOSFET
3.25 Cutoff frequency fT for SiGe MOSFET and Si control MOSFETs as a
function of gate bias
4.1 Threshold voltages of SiGe MOSFET vs BF2 implant dose for a fixed
8 implanted energy of 200KeV
4.2 Drain current versus gate bias for a SiGe MOSFET with a dose
14 2 1.65×10 / cm for a VD of 2V
4.3 Doping profiles along the channels of the original SiGe MOSFET and the
optimized SiGe MOSFET
4.4 Id vs VD for the original SiGe and the threshold voltage optimized
MOSFET
4.5 gm vs VG for the original SiGe and the threshold voltage optimized
MOSFET
4.6 Log ID vs VG for the original SiGe and the threshold voltage optimized
MOSFET
4.7 Cutoff frequency comparisons of the original SiGe MOSFET and the
optimized SiGe MOSFET
4.8 Threshold voltage vs gate oxide thickness Tox for SiGe vertical channel
MOSFET
4.9 Transconductance of SiGe MOSFET vs gate oxide thickness Tox
4.10 Subthreshold characteristics of the SiGe MOSFETs with different gate
oxide thickness
4.11 Subthreshold slop of SiGe MOSFET vs gate oxide thickness Tox
4.12 Profile of SiGe MOSFET with 4nm gate oxide
4.13 Channel profile comparison of 4nm gate oxide SiGe MOSFET and 10nm
gate oxide SiGe MOSFET (Left hand side: 4nm, right hand side: 10nm)
9 4.14 LogId vs Vg for 4nm gate oxide SiGe MOSFET for various BF2 channel
implants
4.15 15 VT vs BF2 implant dose for 4nm gate oxide SiGe MOSFET
4.16 Dopant profiles for SiGe MOSFET and Si control MOSFET
4.17 Output characteristics of the graded SiGe vertical NMOSFET and Si
control MOSFET for Vg-Vt from 0 to 2V in 0.5V step
4.18 Id vs Vg for SiGe MOSFET and Si control MOSFET
4.19 Transconductance vs Vg for SiGe MOSFET and Si control MOSFET when
Vd=0.1V
4.20 Comparison of Si MOSFET and SiGe MOSFET subthreshold ID vs VD
characteristics for a VD =0.1V
4.21 DIBL of 4nm gate oxide SiGe MOSFET and Si control MOSFET
4.22 Peak cutoff frequency vs Vg for SiGe MOSFET and Si control MOSFET
4.23 Ge Mole fraction distributions along the channel in different SiGe
MOSFETs
4.24 Energy bandgap along the channel in different SiGe MOSFETs
4.25 SiGe MOSFET Id vs Vg curves with Vd=0.1V
4.26 SiGe threshold voltage vs Ge implant dose
4.27 27 Transconductance variation with Ge dose for the SiGe MOSFETs
when Vd = 0.1v (a) and 2.5v (b)
4.28 SiGe MOSFET peak transconductance in saturation region vs Ge implant
dose
4.29 Subthreshold characteristic of SiGe MOSFET with different Ge implant
10 4.30 SiGe MOSFET subthreshold slope vs Ge dose
4.31 fT vs VG for SiGe MOSFET with different Ge dose with Vd=2.5V
4.32 SiGe MOSFET peak cutoff frequency vs Ge dose for fixed implant energy
of 200KeV and fixed Boron implant of 55KeV and dose of 3.5×1015 cm2
4.33 Channel profiles of SiGe MOSFETs with different channel lengths
4.34 Id vs Vg curves of SiGe MOSFET with different channel length
4.35 Gm vs Vg of SiGe with different channel length
4.36 Dopant profiles for 0.15 µm (a), 0.12 µm (b), 0.10 µm (c) and 0.08 µm (d)
SiGe MOSFETs
4.37 Log Id vs. Vg for SiGe MOSFETs with different channel lengths when Vd
is 2v
5.1 Concept of the dielectric pocket vertical MOSFET
List of Table
1.1 MOSFET Key Parameter Change with scaling from 1972 to 2000 (the
TDDB is time dependent break down)
2.1 Parameters of RSH Doping-Dependent Models for Silicon
2.2 Coefficients of Auger Recombination for Silicon
2.3 Constant Mobility Coefficients for Silicon and Germanium
2.4 Constant Mobility Coefficients for Si1− xGex alloy
2.5 Coefficients of Masetti Model for Si , Ge and SiGe
11 2.6 Coefficients of Lombardi for Silicon
2.7 Parameters of Bandgap Narrowing with Temperature for Silicon
2.8 Parameters of Bandgap Narrowing with Temperature for Silicon
2.9 Parameters of Bandgap Narrowing with Temperature for Germanium
2.10 Parameters of Bandgap Narrowing with Temperature for Si1-xGex
2.11 Electron affinity of Silicon, Germanium and Si1-xGex
2.12 Parameters of Bandgap Narrowing Oldslotboom Model for Silicon
4.1 DOE of SiGe MOSFET Channel BF2 Implant Dose and VT
4.2 Threshold voltage comparison of the SiGe MOSFET with different Tox
4.3 The peak gm comparison of SiGe MOSFET with different Tox
4.4 Subthreshold Slop Comparison of SiGe MOSFET with Different Tox
4.5 Threshold Voltage vs Channel BF2 Implant Dose for 4nm Gate Oxide
SiGe MOSFET
4.6 Threshold voltage as a Function of Channel Germanium Implant Dose
DOE
4.7 Subthreshold Slope of SiGe MOSFET with Different Ge Implant Dose
4.8 Peak Cutoff Frequencies of SiGe MOSFETs for Various Ge Implant
Doses
4.9 Channel BF2 Doping and Threshold Voltages for Different Channel
Length SiGe MOSFETs
4.10 Target and Measured Channel Lengths of SiGe MOSFETs
4.11 Comparison of DIBL for SiGe MOSFETs with Different Channel
Lengths when Vd=0.1V and Vd=1.1V
12 4.12 Comparison of DIBL for SiGe MOSFETs with Different Channel
Lengths when Vd=0.1V and Vd=0.5V
4.13 SiGe MOSFET Peak fT for Vd= 2.5V with Various Channel Lengths
13 Chapter 1
Introduction
It has been forty eight years since the invention of the bipolar transistor
[1], almost forty years since the invention of the MOSFET and more than fifty years since the invention of the integrated-circuit (IC) [2]. For the last four decades, Silicon has been the dominant material in the field of semiconductor electronics. Although bipolar transistors are still playing important roles in the semiconductor industry, the MOSFET (Metal-Oxide-Silicon Field-Effect-
Transistor) is the prevailing device for most applications, such as microprocessors, RF application and memory circuits. In addition, the MOSFET is increasingly used in areas as diverse as mainframe computers and power electronics. The MOSFET’s long standing advantages over other types of devices are its mature fabrication technology, its successful scaling characteristics and the combination of complementary the N and P-channel
MOSFETs yielding CMOS circuits. In the past twenty years, the evolution of
CMOS technology has followed the path of device enhancement through downscaling for achieving density, speed, and power improvements. MOSFET scaling has been significantly propelled by the rapid advancement of lithographic techniques enabling the definition of smaller features from about 10mm in the
1960’s to less than 0.1 micron meter today. During the early years of transistor scaling, Gordon Moore et al (in 1965) predicted that the number of transistors per
14 square inch on integrated circuits would double every 18 months which has
become known as Moore’s law [3] [4]. While this trend has been followed for
decades, even according to Moore himself, “no exponential is forever” [5]. The
key technical challenge for continued transistor scaling following Moore’s law in
the future is scaling the planer MOSFET below a gate length of approximately
several tens nanometers (nm). However, there are significant challenges that
must be overcome such as lithography, channel doping fluctuation, short channel
effects and hot carrier effect. Although some researchers have demonstrated 30
nanometer planer gate length MOSFET [6], the devices do not appear practical.
Nevertheless, researchers will continue to explore ways to change the materials
and structural design for these novel tiny transistors and overcome barriers to the
MOSFET’s operation at very short gate length progress can continue.
One of the possible alternatives to traditional Si planar MOSFET structure
that being explore is the Vertical channel MOSFET [7][8]. The recent
development of strained Silicon-Germanium is a good additional tool that has
made shorter channel MOSFETs attractive. Recently, fabrication of a strained
Silicon-Germanium vertical channel MOSFET has been developed that does not need sophisticated lithography and whole fabrication is compatible with a standard CMOS process [8]. The transistors exhibited better performance than Si control planar devices, and so is a possible candidate for extending the evolution of CMOS technology. This thesis describes the results of a simulation study of the fabrication and physics of operation of the strained Silicon-Germanium
15 vertical MOSFET aimed at better understanding the device’s performance in
order to facilitate improvement in the device’s design.
In this chapter, we will briefly review the current planar MOSFET’s
fabrication, discuss design considerations and examine the problems with
continued downscaling of planar MOSFET. We also briefly describe the vertical
channel MOSFET including its fabrication and performance.
1.1 Planar MOSFET Fabrication and Design Considerations
1.1.1 Planar MOSFET Fabrication
Many important semiconductor technologies have been derived from
processes invented decades ago. The planar process which utilized on oxide
layer formed on a semiconductor surface was originally developed by Hoerni [10]
in 1960. This MOSFET fabrication technology has dramatically control over the last three decades. Starting with a ten-micron gate length PMOS process with an aluminum gate and a single metallization layer around 1970, the technology has moved to n channel , polysicide gate MOSFET with MOSFET channel length scales down to sub-micron dimensions. Table 1.1 shows the scaling of MOSFET key parameters from 1972 to 2000 [11]. As described in table 1.1, with the development of MOSFET downscaling, the power supply (Vdd) and threshold
Voltage (VT) values get smaller and the Gate-oxide thickness becomes thinner,
Figure 1.1 shows the relationships among these parameters [10].
16 Table 1.1 MOSFET Key Parameter Change with scaling from 1972 to
2000 (the TDDB is time dependent break down).
Figure 1.1: MOSFET Channel Length vs. Power Supply, Threshold Voltage (V) and Gate-Oxide Thickness [10].
17 Currently, the fabrication technology has evolved into a less tenth-micron
self-aligned-gate CMOS process with up to several metallization levels.
Fabrication technology is more and more precise, dopant diffusion is replaced by
ion implantation, thermal oxidation is replaced by oxide deposition, a metal gate
is replaced by a poly-silicon gate, dry etching is dominating the etching
processes and from aluminum wiring to copper wiring has provided vastly
superior analog and digital CMOS circuits. Many processing steps of MOSFET
fabrication require appropriate masks. Consequently, the integrated circuit is looked as a set of patterned layers of doped silicon, polysilicon, metal and insulating silicon dioxide. In general, a layer must be patterned before the next layer of material is applied on chip. The process used to transfer a pattern to a layer on the chip is called lithography which is a very critical technique when the device is smaller and smaller. The lithographic sequence is repeated for different layers, using different masks, each mask introduces some changes in the surface features. With further shrinking of dimensions, MOSFET processes become more stringent [12]. A typical MOSFET fabrication flow includes diffusion, oxidation, photolithography, ion implantation, metallization, wet etching, dry etching, thin film deposition. These processes appear alternately in the flow.
The following figures are a typical simplified front-end-of –the-line fabrication flow of planar CMOS FETs which channel length is less than 0.5 µm . a) Starting material P-type substrate or p- epi on P+ substrate for latch-up prevention, grow pad oxide and deposit CVD nitride.
18 (a)
b) Lithography to cover the active region with photoresist and reactive ion etching (RIE) nitride and oxide in the filed region, shallow trench is formed.
(b) c) Grow thick pad oxide by CVD, thick oxide layer grows on the surface.
(c)
d) CMP (chemical-mechanical polishing) is used for surface planarization.
(d)
e) N-well lithography and implant and both n-channel and p-channel doping.
(e)
f) Grow gate oxide, deposit polysilicon, gate lithography.
(f) g) RIE polysilicon gate.
19
(g) h) Side wall reoxidation, n+ source/drain lithography and implant, p+ source/drain lithography.
(h)
i) Oxide spacer formation by RIE, source/drain anneal, self aligned silicide process.
(i)
Figure 1.2 A typical sub-0.5 µm planar CMOS front-end-of-the-line fabrication flow [13].
Shown below in Figure 1.3 is schematic drawing of a realistic MOSFET structures and highlighting some of critical issues associated with its fabrication.
20
Figure 1.3 Modern MOSFET structure [14].
Copper and low k dielectric materials have replaced the traditional Al as interconnect metal for low RC delay although that will increase metal etching problems. STI (shallow trench isolation) has replaced LOCOS (Local Oxidation of
Silicon) for smooth surface by using CMP (chemical mechanical polishing) technology. When the device dimension is deep submicron, the poly silicon gate depletion and resistance will degrade the performance of MOSFET, Ti or Co silicide has replaced poly silicon as the gate, this kind of structure can decrease the gate resist and gate depletion effect. To get lower source and drain resistance, sicide is used for source and drain metal connection. Silicon dioxide has been the gate dielectric for decades, but with the development of the device scaling, higher integrity dielectric is needed as the alternative of the gate silicon oxide. Even epi wafer may be used to decrease the defects in the substrate for high yield. Short channel effect is a serious problem of scaling, retrograde well implant, anti-puchthrough and Halo or pocket implants are used to decrease the
21 short channel effect. LDD implant process helps prevent hot carrier effect. All the
technologies above are used or will be used in the industry in future to extend the
Moore’s law [10] [11].
1.1.2 MOSFET Design Considerations
MOSFET technology evolution has followed the path of device down
scaling for decades to achieve density, speed and power improvements [15]. The
primary goal of device design is to obtain devices with high performance, low
power consumption, low cost and high reliability while maintaining the same
physics of device operation [161]. To understand the challenges facing deep sub-
micron device design, we must understand the design parameters and challenge
facing a device designer and their significance. The main MOSFET parameters
we will discuss include the threshold voltage, transconductance, Drain Induced
Barrier Lowering (DIBL), Subthreshold Swing, cutoff Frequency. When the gate
length dimension of device is very small, the short channel effect, hot carrier
effects and tunneling effect will also affect these characteristics [15].
The threshold voltage VT is one of the key parameters for the MOSFET.
With the development of scaling down of MOSFET’s dimensions, the power supply voltage is simultaneously reduced and the VT must be reduced. A complication that arises is the gate length is scaled down is that the threshold voltage will decrease with decreasing channel length [17]. This short-channel effect is an important challenge in device design. If the transistor gate length dimension is less than one micron, the short-channel effect is very serious as
22 shown in Figure 1.4 [15]. In the long-channel device, the surface potential is
mainly controlled by the gate voltage and the source and drain fields only affect
the very ends of the channel. In the short-channel device, the source and drain fields penetrate deeply into the middle of the channel, which lowers the potential barrier between the source and drain. For this reason, the subthreshold current increases, which means the threshold voltage becomes lower than the long- channel value as it is illustrated in Figure 1.4 [15]. A significant challenge for
MOSFET designers is how to modify the MOSFETs doing for minimizing this threshold variation with channel length.
23 Figure 1.4 Short-channel, threshold roll-off for N-channel (a) and P-channel (b)
MOSFETs versus channel length [15].
When the high drain voltage applied to a short-channel device is increased, the barrier height is lowered, resulting in a decrease of the threshold voltage. Shown in Figure 1.5 is the energy band structure of long-channel
NMOSFET and short-channel MOSFET when the drain bias has been added bias.This effect is referred to as drain-induced barrier lowering (DIBL). DIBL increases the off-state leakage current and causes drain-to-source punch- through; it is one of the main limiting factors in the scaling of short-channel transistors.
(a) (b)
Figure 1.5 Short-channel, threshold roll-off for N-channel (a) and P-channel (b)
MOSFETs band structures DIBL effect.
24
Figure 1.6 Log Id vs Vg when Vds is change [15].
Figure 1.6 is an example which shows the DIBL, when the gate length L is
0.35 µm , Vds changes from 50mv to 3v, the transistor current increases much
both in linear and saturation regions. Figure 1.7 is the current vs Vd curve of
short-channel MOSFET and long-channel MOSFET when their gates are biased
by the same Vg. Because of the DIBL effect, the short-channel device current
curve has an obvious slope in the saturation region that is worse than that of
long-channel device. This corresponds to a lower ourput resistance which
degrades the transistors’s current performance.
25
Figure1.7 Comparison of long-channel MOSFET and short-channel MOSFET
Id-Vd curves [14].
The MOSFET’s subthreshold behavior is very important for small devices and in particular for low-voltage, low power applications such as digital logic and memory circuits [18]. Because it describes how a MOSFET device switches off.
When the gate voltage is several tenths of a volt below threshold voltage, the device operates in the weak inversion region. For short channel MOSFET the drain current is not negligible, because the inversion charge density does not drop to zero abruptly [15]. Unlike strong inversion region, subthreshold conduction is dominated by carrier diffusion and not by the drift. Figure1.8 shows the drift and diffusion current components of the drain current in a logId-Vgs plot
[15]. The subthreshold swing S given in units of mv per decade means how large a reduction in the gate voltage is needed to reduce the drain current by an order of magnitude. A smaller S indicates a MOSFET that turns off with a smaller gate voltage swing, which is desired.
26
Figure 1.8 Drift and diffusion current components of current in an Id-Vgs plot. The sum of these two components is the total drain current represented by a solid line
[15].
For VLSI circuits, a steep subthreshold S swing is desirable for ease of switching the transistor’s drain current off; therefore, small values of subthreshold swing are desired. From Figure 1.6 we can also observe the subthreshold swing is increased when the channel length is scaled down. However, reducing the gate oxide thickness and/or the substrate concentration causes the subthreshold swing to decrease [15].
The MOSFET’s Transconductance gm is a key device parameter, determining the gain of MOSFET amplifiers. It quantifies the drain current variation with a gate-source voltage variation while keeping the drain-source
27 voltage constant and is of crucial importance because it describes the ability of the device to drive a load [19]. The tranconductance plays a large part in determining the switching speed of a circuit. High transconductance devices yield circuits capable of high speed operation. With the scaling of MOSFET, we can get higher transconductance.
Since the transconductance goes up as the gate length goes down, in conjunction with downscaling of the gate length for modern MOSFETs, the gate oxide thickness has been reduced to the order of a few atomic layers and alternative gate dielectrics to silicon dioxide have been investigated to resolve problems such as the short effects described above as well as excessive gate leakage [20]. As the oxide thickness decreases, the gate current increases exponentially and becomes more important. It eventually dominates the off-state leakage current of the drain and arises from electron tunneling between the drain and gate. There are two kinds of tunneling: Fowler-Nordheim(FN) tunneling and direct tunneling as shown in Figure 1.9. For normal MOSFET operation, FN tunneling is negligible. But for down scaled MOSFETs, when the oxide layer is very thin, electrons from the inverted silicon surface tunnel directly through the forbidden energy gap of the oxide layer. This gate leakage current can become important for low power and portable applications since it can drain battery power.
28
Figure 1.9 FN tunneling and direct tunneling.
For small-signal applications, the MOSFETs cutoff frequency is an important figure for a transistor. For MOSFET, the cutoff frequency is the frequency where the MOSFET is no longer amplifying the input signal under optimum conditions; that is, it is the frequency where the absolute value of the output current to input current ratio is unity. While III-V compound semiconductor based FETs have widely used for high frequency applications [21]. With the scaling of MOSFET’s, to 0.1 micron gate length, Silicon is playing a more important role in RF area. The advent of deep-submicron CMOS technologies has made possible the implementation of RF circuits in standard CMOS processes, offering the twin advantages of high levels of integration and low cost solutions. As channel lengths continue to shrink, then faster MOSFETs can be realized [22]. A MOSFET with cutoff frequency beyond 140 GHz has been recently reported [23]. Although the continual evolution of silicon MOSFET faces these kinds of difficulties, it is still considered among the best choices for the modern semiconductor industry. Developing MOSFET structures with even
29 smaller dimensions and better performance continues to be the good driving the
CMOS industry.
1.2 Silicon Vertical Channel MOSFET and Strained Silicon-
Germanium MOSFET
Over the past four decades, the channel length of MOS transistors has halved at intervals of approximately every eighteen months, which has led to a virtuous circle of increasing packing density (more complex electronic products), increasing performance (higher clock frequencies) and decreasing costs per unit silicon area [11]. However, to continue this progress, the downscaling of the
MOSFET is facing a growing list of technical problems. To continue on this path, research is underway at some research labs to investigate an alternative method of fabricating short-channel MOS transistors. A number of variation in the
MOSFET’s design have been reported including the FinFET [24], the TriGate
MOSFET [25], the π-Gate or Omega-Gate MOSFET [26] and the Quadruple-
Gate MOSFET [27] , Figure 1.10 shows a 3D views of these four transistors.
30
Figure 1.10 Three-dimensional views of a FinFET (a) TriGate (b) Ω-gate (c) and
Quadruple-gate (d) device [28].
These MOSFETs have already exhibited superior scaling behavior such as reduced short channel effect, reduced DIBL and better S as compared to the traditional MOSFET [24-27], however, they are have to be built on the SOI(silicon on insulator) substrates and very difficult to fabricate. Some alternative new transistor structures which are fit for standard MOSFET fabrication technology have also been explored including the vertical channel MOSFET. Vertical channel MOSFETs are divided in 3 groups: single gate, double gate MOSFET and surrounding gate MOSFET [9]. Because the fabrication of double gate
31 MOSFET is easier than other two and double gate devices double the channel
width per unit area, thus increasing the current drive per unit area of the
transistors, we only discuss the double gate vertical MOSFET in this thesis.
Similar to the FinFET and related devices shown in Figure 1.10, the
double gate of the vertical channel MOSFET provides better immunity to short
channel effects and devices featuring better subthreshold swings can be
obtained. If the transistor’s body is thin enough, the short channel effects are
better controlled by the gate voltage in double gate MOSFETs so that it is not
necessary to increase the body doping while reducing the channel length as is
done in planar, single gate MOSFETs. This allows bypassing the problem of the
increased leakage currents due to body/drain tunneling with an increasing body
doping. In Figure 1.11 the concept of the vertical double gate MOSFET is shown.
In this device the current flow and the silicon / oxide interface are perpendicular
to the wafer surface instead of in the plane of the surface.
Figure 1.11 Layout of the vertical double gate MOSFET.
32 Silicon vertical MOSFETs have three main advantages [28]: First, the channel length of the vertical MOS transistor is not defined by the lithographic process. This means that there is no requirement for post-optical lithography techniques such as x-ray, extreme ultra-violet, electron projection lithography, ion projection lithography or direct write e-beam, which can be possibly prohibitively expensive. Second, Vertical MOS transistors are easily made with two vertical gates called front and back gates. Using this technology doubles the channel width per transistor area. Combined with easier design rules, this leads to an increase of packing density of at least a factor of four as compared to horizontal transistors. In this way, fully depleted transistors can be produced which have all the advantages of SOI transistors. An advantage of the vertical MOSFET is the possibility to prevent short channel effects from dominating the transistor by adding processes that are not easily realized in horizontal transistors, such as a nonuniform channel doping along the channel length a polysilicon source to reduce parasitic bipolar effects or a dielectric pocket to reduce drain induced barrier lowering (DIBL). In the vertical channel MOSFET fabrication flow, since the gate length is controlled by nonlithographic methods, this allows a smaller channel length to be realized than with photolithography. As a result, the gate length is decoupled from the packing density. In addition, long channel transistors (with lower off currents) can be produced without decreasing the number of devices per unit area.
The switching speed of a MOSFET can be increased primarily by two ways [17]: physical gate length scaling and carrier mobility enhancement.
33 Strained silicon-germanium is a technology which increases the switching speed
solely by enhancing the carrier mobility. Here the carrier mobility is enhanced by the strain which reduces the effective mass and/or the scattering rate. Strained silicon-germanium can also be incorporated in vertical MOSFETs. These transistors have not only all advantages of vertical structures, but also the merits of the better performances of strained silicon-germanium. The mobility of carriers of the direction normal to the growth plane of strained silicon-germanium over that of bulk silicon has been demonstrated [29][30]. Carriers flow in the out-of- plane direction. So both the electron and hole mobilities are improved in compressively strained silicon-germanium layers [31]. The strained silicon- germanium vertical MOSFET can be fabricated in two ways: one way is to grow the strained silicon-germanium layers by solid phase epitaxy, the other one is by using germanium ion implantation [31]. The advantages of epitaxy are well known for creating novel electronic properties. However, epitaxy until now has not been implemented into a mainstream logic technology, which is based on low cost and simplicity of the CMOS structure. Simulation of germanium ion implantation is used to form the doped channel of strained silicon-germanium devices investigated in this thesis. In this study, we compare the performances of a vertical channel Si control MOSFET and SiGe MOSFET, where a strained silicon-germanium MOSFET is the formed by nonuniform doping both impurity and the germanium. Figure 1.12 shows the cross-sectional profiles of N type vertical silicon control MOSFET and the silicon-germanium linear channel
MOSFET.
34 Boron Boron and doped linearly Channel distributed Germanium doped Channel
Figure 1.12 N type Silicon Control Vertical MOSFET (left) and Strained Silicon-
Germanium Control MOSFET (right)
1.3 Reported Results for Silicon-Germanium Vertical Channel
MOSFET
Strained planar SiGe MOSFETs have attracted much attention recently
because of the mobility enhancement achieved in the channel and because its
fabrication is compatible with typical Silicon technology [31-33]; Vertical
MOSFETs have also received much attention as alternative MOSFET for future
architectures for DRAM, SRAM, EEPROM, and conventional CMOS applications
[34]. The Silicon-Germanium vertical channel MOSFET combines the
advantages of both the strained channel with enhanced carrier mobility with
attractive features of vertical channel MOSFETs. Since 2000, some fabrication
and modeling work has been done by the Solid-State Electronics group of the
University of Texas at Austin. They have fabricated vertical graded channel
MOSFETS with a channel length below 0.2 µm and 0.1 µm without sophisticated
lithography while keeping the process compatible with a regular CMOS process
35 [35-36]. Both the hole and electron mobility enhancement have been observed in
their experiments. The drain current for the vertical SiGe PMOSFETs has been
found to be enhanced by as much as 100% over the silicon control devices and
the drain current for the vertical silicon-germanium NMOSFETs has been
enhanced by 50% compared with the silicon control devices on the same wafer
[35].
In a graded doped channel, drain induced barrier lowering (DIBL) and off-
state leakage current were reduced significantly. In addition, lower longitudinal
electric field in the drain end can be achieved without lightly doped drain (LDD),
and hot carrier effects were reduced substantially with vertical graded channel
device [33].
1.4 Purpose of Thesis
In this study, numerous fabrication and device simulations of vertical
channel MOSFETs including the strained SiGe channel devices have been done
by ISE TCAD simulators DIOS and DESSIS, respectively. The results of our
simulation were compared with the previous reportes as a starting point. We
observed good DC and RF characteristics for both the SiGe MOSFET and the Si
control MOSFET when the transistor channels were greater than 0.11 µm , short channel effects were small in both transistors, and DIBL of 48.63mv/v and
45.59mv/v were observed in SiGe MOSFET simulation and Si control MOSFET simulation, respectively. When the channel is scaled under 0.1 µm , we also found
36 serious short-channel effect too, some fabrication processes need to be optimized if we want to scale the device’s dimension less than 100nm.
TCAD simulations including both the fabrication and physics of device physical operation were employed using ISE simulators instead of physical experimentation. Silicon control vertical channel MOSFETs and silicon- germanium vertical graded channel MOSFETs were modeled and a large number of electrical characteristics were investigated. Threshold voltage, transconductance, subthreshold slop and other key electrical characteristics for each device design were extracted and compared. The subject of this thesis is the study of the implementation of strained silicon-germanium vertical MOSFET structures in order to improve their performances and solve the problems related with device geometry. We discuss the advantages and disadvantages of the device designs using process simulations and study the variation on the process conditions to explore the design of better short channel MOSFET.
1.5 Organization of Thesis
This thesis is organized into 5 chapters. Chapter 1 has provided a brief
introduction to vertical channel MOSFETs and the issues with downscaling
MOSFETs to short channel length. Chapter 2 describes the structure of the
commercial fabrication simulator DIOS, the device simulator DESSIS and
important simulation materials and device physics models that are used in our
simulations. The properties of silicon-germanium and how these properties vary
with the change of germanium content can also be found in chapter 2. Chapter 3
37 describes the basic fabrication process and process modeling for the vertical channel MOSFET and its simulation including small signal AC simulation ,the full range of DC simulation results including threshold voltages, saturation currents,
DIBL, subthreshold swing. The results are compared with the previous experimental results reported as a starting point for this study. Chapter 4 investigates variations in the device fabrication process including channel length, channel impurity dose, germanium dose, and how the variations affect the performance parameters of vertical channel of strained SiGe MOSFET. Finally,
Chapter 5 provides conclusions and some suggestions for future.
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43 Chapter 2
Simulation Software and Materials
Properties of Silicon-Germanium
2.1 Introduction to ISE TCAD Simulation Procedure
ISE-TCAD is Technology Computer Aided Design software that specializes in semiconductor process, device, and circuit simulation. So far it is the most successful commercial TCAD software in the market. The package includes simulation environment software, a fabrication process simulator, a device simulator, a device structure simulator, visualization software and a parameter extraction tool. In this thesis, we describe building vertical Silicon control
MOSFETs and vertical strained Silicon-germanium graded channel MOSFETs using the ISE 2D fabrication simulator DIOS, and examine the results of our simulation of the device performances by DESSIS. The ISE-TCAD software we used for this thesis mainly consists of following parts:
1. GENESISe: ISE’s primary user interface and environment software for
TCAD simulation, providing access to all ISE software components. It has
the function of Design of Experiments (DOE) for setting up a series of
related simulations.
44 2. DIOS: multidimensional fabrication process simulator for Silicon and
Silicon-Germanium devices. It allows simulations of complete fabrication
sequences including etching and deposition, ion implantation, and
diffusion and oxidation with models in one dimension and two dimensions.
Some of the capabilities are also available for simulations in three
dimensions. If we use DIOS to simulate the fabrication of the device, the
ISE TCAD program uses fully automatic meshing through highly adaptive
grids that does not require user intervention. In addition to analytical
implantation models, it includes the 1D and 2D Monte Carlo simulator
Crystal-TRIM and an interface to the 3D Monte Carlo simulator MCimpl.
Diffusion is simulated on the basis of state-of-the-art point defect models
that are calibrated to a large number of experiments. In this thesis, we use
2D DIOS to simulate fabrication of all of the devices; the third dimension of
device is 1um by default [1].
3. DESSIS: a multidimensional, electrothermal, mixed-mode device and
circuit simulator for 1D, 2D, and 3D semiconductor device modeling. It
incorporates advanced physical models and robust numerical methods for
the simulation of most types of semiconductor devices ranging from very
deep submicron Silicon MOSFETs to large bipolar power structures. In
addition, Silicon-carbon and III–V compound homostructure and
heterostructure devices are fully supported. In this thesis, all device
simulations for 2D Silicon and Silicon-germanium devices are done by
DESSIS [2].
45 4. TECPLOT: a graphics tool that is used to view the structure of the 2D and
3D devices and the results of device simulations. It can plot solutions and
derived variables (like potential, carrier density, mobility, electrical field,
etc). We use it to plot one and two dimensional device profiles and extract
data of device structures, such as carrier, impurity, electrical field,
Germanium mole fractions and energy band profiles.
5. INSPECT: a very versatile tool that can be used to view graphical data,
extract data from the plotted curves and also to simply perform
mathematical manipulations on the data. In this study, all data for device
electrical characters are prepared using INSPECT.
In this study, the tools of DIOS, DESSIS, TECPLOT and INSPECT are
used within the structure of GENESISe. Figure 2.1 shows the basic flow of
simulation:
Figure 2.1 The simulation flow used in this thesis under GENESISe
46
2.2 DIOS and Relative Procedures and Models of Process
Simulation
The fabrication of semiconductor devices involves an extensive set of processes that require the use of sophisticated facilities that are expensive to run and maintain. The equipment alone costs millions of dollars, not including the cost of the consumable materials, and the need for proper disposal procedures for chemical wastes. For state-of-the-art silicon devices these processes are prohibitively expensive for university laboratories. Fortunately, the ISE process simulator DIOS can do the virtual fabrication in computers precisely. The results of the process simulation program can then be used as the input file for a device simulator DESSIS and the device characteristics can be simulated and performance parameters extracted. This provides a useful way of studying the effects of process parameters on the device performance and both the device structure and the fabrication process can thus be optimized. The device simulator can become a powerful tool for understanding the physical operation of electronic devices, such as MOSFETs and BJTs. DIOS is a multidimensional semiconductor device process simulator which allows simulations of complete fabrication sequences with identical models in one dimension and two dimensions. Some of the capabilities are already available in three dimensions but only two dimensional device fabrications are simulated in this thesis, DIOS can be run in an interactive mode or with a command file as the input. A high
47 level of control is achieved through the interactive visualization during the simulation of individual process steps. DIOS can also be used with the ISE workbench GENESISe in computer experiments designed to run and optimize complete simulation flows from device fabrication through simulation of device performance.
In this study, it is not possible for us to discuss all the procedures employed in the fabrication process for the vertical channel MOSFET; we only highlight several key processes, namely etching, deposition, implantation, masking, oxidation and diffusion.
2.2.1 Etching
In general, etching technology consists of both dry and wet etch methods.
Dry etching methods include plasma etching, reactive ion etching, sputtering, ion beam etching, and reactive ion beam etching [3]; wet etching is liquid chemical etching. In DIOS we do not do rigorous physical/chemical simulation of etching, instead a set of geometry operations is provided which allows defining local etching rates that can be used to approximate the modifications of the structure during the etching process. In a rigorous sense DIOS can not predict the shapes after etching, they are entirely determined by the user supplied etching parameters and by the discretization of the layer structure. Etching rate, materials, selectivity rate, etching time, regions, and boundaries can be specified; the direction and the size of the displacement depend on the chosen models, that is, on the specified rates. Etch stop and selected material remove are also
48 defined in DIOS; the isotropic and nonisotropic components of the etching rates can be specified in DIOS. In this study, we used both the isotropic etching model and anisotropic model.
2.2.2 Deposition
Thin film deposition can be done by epitaxy, chemical vapor deposition
(CVD) and sputtering. DIOS provides flexible simulation of the deposition of thin films in up to three dimensions based on a purely geometrical set of models. In
DIOS we need not attempt to simulate the various physical and chemical processes which are involved in real thin film deposition steps. That means the influences of physical and chemical processes on the shape of the deposited layers are not modeled. Instead, model parameters and local deposition rates can be specified to construct a geometry which is similar to the one observed in reality. DIOS offers isotropic deposition, anisotropic deposition and selective deposition. In this study, all depositions use only the isotropic deposition model.
2.2.3 Masking and Lithography
Lithography is the key technology in semiconductor manufacturing industry, because it is used repeatedly in a process sequence that depends on the device design. It is used in the device fabrication process every time a pattern must be transferred to the substrate surface. It also allows one to perform ion implantation or etch materials in selected areas. Ultimately it determines the device dimensions [4]. In DIOS regions composed of photo resist (or other
49 materials) can be defined with the Mask command. The beginning and end positions of a mask region can be defined by the user or be read from an external input file. The materials, thickness and the lateral position of the mask corners can be specified in the Mask command. The mask contours are constructed by default with a planar top surface, the thickness parameter determines the minimum thickness. In this study, four masks are used for different processes in vertical channel MOSFET’s fabrication.
2.2.4 Implantation
The ion implantation technique allows for the introduction of doping impurities in Silicon with a high level of accuracy. An ion implanter is basically a particle accelerator in which Ions are accelerated by the implanter into the Silicon and stop at a given depth in the crystal depending on the chosen implant energy
[5]. In DIOS, the simulation of implant steps is achieved by using either an analytical distribution functions or Monte Carlo simulation to compute the distribution of implanted ions and of implantation damage. Algorithms for the analytical implantation into 1D and 2D structures are an integral part of the simulator DIOS, whereas the algorithm for analytical implantation into 3D structures was developed and implemented at FHG Erlangen [6]. The Monte
Carlo simulation for 1D and 2D structures is done with the program Crystal-TRIM
[7], which was developed at FZ Rossendorf and is linked into the DIOS binary, whereas the Monte Carlo simulation for 3D structures is done with the external tool MCimpl, which uses an algorithm developed at TU Vienna [8]. DIOS controls
50 both external algorithms for 3D analytical and Monte Carlo simulation. In this study, because of the limits of software and for saving time, the various impurity channel implants are simulated using analytical distribution functions with dose matching techniques and lateral integration. There are eight ion distribution functions in DIOS; they are Gauss, Pearson, P4, P4S, JHG, GK, P4K and JHGK as shown in Figure 2.2.
Function Distribution
Gauss Gaussian Pearson Pearson-I,-IV or –VI distribution P4 Pearson-IV distribution P4S Pearson-IV distribution with ‘linear’ exponential tail JHG Jointed half-Gaussian GK Gaussian with general exponential tail P4K Pearson-IV distribution with exponential tail JHGK Jointed half-Gaussian with general exponential tail
Figure 2.2 List of primary distribution functions for ion implantation [1]
The default vertical analytical distribution function is primary distribution function
Pearson-IV with a lateral Gaussian distribution functions. We only used these default distribution functions. For arsenic, phosphorus, antimony, gallium, indium, aluminum and germanium, the Gibbons tables [9] are used. The data for boron
51 has been obtained from experimental values fitted with the 1D simulator TESIM-4
[10] and from reference [11].
2.2.5 Diffusion
Diffusion and ion implantation are the two key methods of impurity doping.
Here diffusion includes rapid thermal processing (RTP) and conventional thermal
diffusion. Dopant redistribution is caused by dopant and point defect diffusion, by
chemical reactions at the interfaces and inside the layers and by convective
dopant transport due to internal electrical fields as well as due to material flow
and moving material interfaces when the substrate is in any high temperature
process. In DIOS a set of diffusion models can be selected and uses a block
Gauss-Seidel iteration to resolve the equations. During the diffusion process, the
segregation effect will be simulated for all diffusion steps too. For each of the
dopants, all materials can select the diffusivity model. In Silicon, we assume
active dopants are electrically singly charged and to be the only mobile dopant
species. The diffusion equation is given as:
∂c tot + ∇j = 0 ∂t (2.1)
where the dopant flux j is defined as
j = −D(∇cact + qcact∇ϕ) (2.2)
Here ctot is the total concentration of the dopant species; cact is the active concentration of the dopant species; D denotes the diffusion coefficient, q the charge state (q=+1 for donors; q=-1 for acceptors) and ϕ the suitably scaled electrostatic potential. The material Silicon–Germanium has been introduced to
52 allow separate user-defined values in the silicon and Silicon-Germanium mixed
layers. A sophisticated modeling of germanium diffusion and interaction with
dopants requires germanium to be introduced as a species with a concentration
profile similar to a dopant such as boron. In this case the silicon–germanium
layer should be modeled in DIOS as a silicon layer containing a local
concentration of germanium. In the Silicon-Germanium material the model will
not only depend on the germanium content, but when there is strain in Silicon-
Germanium layer, the dopant diffusivity is modified by strain, caused by the
presence of Ge in the strained SG layer. In DIOS, no special model of diffusivity
for strained SiGe, the modification of the dopant diffusivities is done as an
empirical function of the concentration of germanium [12].
− 0.042 ⋅Q ⋅Getotal D = Dexp(− * ) (2.3) k ⋅T ⋅ c ni where D is the diffusivity according to the chosen basic diffusion model, without taking into account the germanium content and D the modified value used in the
simulation with germanium. The values of Q can be specified for each dopant
species like Boron and Arsenic which are described in pervious references [13].
2.2.6 Oxidation
The thermal oxidation process is used to form Silicon dioxide and simulate
impurity redistribution during the oxidation process. Oxidation is divided into wet
oxidation and dry oxidation; wet oxidation grows oxide much quicker but lower
quality than dry oxidation. Several simplified oxidation models are implemented in
53 DIOS. They differ mainly with respect to the complexity and coupling of the
physical models involved. The model we use in this thesis is the default model
which allows all materials to be simulated as nonlinear viscoelastics. In this
model, the local shear stress at that spatial position decides the viscosity of the
material. The result of this dependency is that in regions of large shear stress,
often near mask edges, the material flow is enhanced. The model also allows the
coupling between oxidant diffusion and reaction [1]. In this study, the Massoud
model [14] is used for all oxidation processes.
2.3 DESSIS and Device Physics Models for Device Simulation
In our study of Silicon vertical MOSFETs control structure and strained
Silicon-Germanium control vertical MOSFETs, we use ISE’s Device Simulator
DESSIS to predict the results of electrical characteristics of the devices. DESSIS is a multidimensional, electrothermal, mixed-mode device and circuit simulator for semiconductor devices. Only the 2D function of DESSIS is used in this study.
DESSIS simulates numerically the electrical behavior of a single semiconductor device in isolation or several physical devices combined in a circuit. Terminal currents [A], voltages [V], and charges [C] are computed based on a set of physical device equations that describes the carrier distribution and conduction mechanisms. A real semiconductor device, such as a transistor, is represented in the simulator as a ‘virtual’ device whose physical properties are discretized onto a nonuniform ‘grid’ (or ‘mesh’) of nodes [2]. To get accurate simulation results and in a short time, choosing appropriate models is very important. In this thesis,
54 we highlight the relative transport models, generation-recombination models and
carrier mobility models which were used to simulate our vertical MOSFETs.
2.3.1 Basic Equations for Semiconductor Device Simulation
The three governing equations for charge transport in semiconductor
devices are the Poisson equation and the electron and hole continuity equations.
The Poisson Equation is given by
∇ε × ∇ϕ = −q( p − n + N D + − N A− ) (2.4)
where ε is the electrical permittivity, q is the elementary electronic charge, n
and p are the electron and hole densities, respectively N D + is the number of
ionized donors, and N A− is the number of ionized acceptors.
The electron Continuity Equation is:
→ ∂n ∇ × J n = −qR + q ∂t (2.5)
The hole Continuity Equation is:
→ ∂p − ∇ × J p = qR + q ∂t (2.6)
→ where R is the net electron–hole recombination rate, J n is the electron current
→ density, and J p is the hole current density.
Depending on the device under investigation and the level of modeling
accuracy required, the user can select four different simulation modes. First, the
55 drift-diffusion isothermal simulation model described by basic semiconductor equations given above is suitable for low power density devices with long active regions. Second, the thermodynamic simulation model accounts for self-heating and is suitable for devices with low thermal exchange, particularly, high-power density devices with long active regions. Third, the hydrodynamic simulation model accounts for energy transport by the carriers as well as charge transport and is suitable for very small devices. Finally, the Monte Carlo simulation model allows for full band Monte Carlo device simulation in the selected window of the device. The equations for the drift-diffusion and hydrodynamic simulation modes are presented in this section since they were two ones used in this thesis. The equations of the transport models are formulated initially under the assumption of
Boltzmann statistics for electrons and holes. The transport model can be selected independently for either carrier in DESSIS (drift-diffusion only or with thermal transport), or transport can be neglected by assuming a constant quasi-Fermi level for a nonselected carrier. The same applies for the energy balance equation. If it is solved for the temperature of one carrier only, the temperature of the other carrier is assumed to be equal to the lattice temperature. In this study, because the Monte Carlo model is too time consuming, we only use Drift-
Diffusion Model and Hydrodynamic Models. The characteristics of the various transport models are summarized in Figure 2.3.
56
Figure 2.3 Hierarchy of semi-classical transport approaches. [2]
2.3.2 Transport Model
2.3.2.1 Drift-diffusion Model
The drift-diffusion model is the simplest model and so it is often used. The
current equations of this model can be easily derived directly from the Boltzmann
equation. The assumptions of the drift-diffusion model are: Full impurity ionization; Non-degenerate statistics (the Fermi energy is assumed to be at least
3kT below/above the conduction/valence band edge); Steady state (All variables are independent of time) and constant temperature (The temperature is constant throughout the device) [2]. The drift-diffusion model is widely used as a starting point for the simulation of carrier transport in semiconductors and is defined by the set of basic semiconductor equations. But it is not very accurate for
57 simulating deep submicron devices. In this study, all devices are n-channel
MOSFET, where hole transport is modeled by drift-diffusion model.
2.3.2.2 Hydrodynamic Model
With continued scaling into the deep submicron regime, neither internal nor external characteristics of state of-the-art semiconductor devices can be described properly using the conventional drift-diffusion transport model [2]. In particular, the drift-diffusion approach cannot reproduce velocity overshoot and often overestimates the impact ionization generation rates. The Monte Carlo method for the solution of the Boltzmann kinetic equation is the most general approach; but because of its high computational requirements, it cannot be used for the routine simulation of devices in an industrial setting. The hydrodynamic model incorporates velocity overshoot and ballistic effects missing in the drift- diffusion model. Based on the work of Stratton [15] and Bløtekjær [16], the hydrodynamic equations consist of a set of nonlinear conservation laws for particle number, momentum, and energy, plus Poisson’s equation for the electric potential [2]. In DESSIS, the electron, hole, and lattice temperatures are solved by specifying the keywords ElectronTemperature, HoleTemperature, and
LatticeTemperature, respectively. A Scharfetter–Gummel like discretization scheme is used for the discretization of the continuity equations and energy balance equations. The hydrodynamic model is the best choice for us because it has the advantages of both good accuracy and reasonable computation time.
The full formulation, including the so-called convective terms [17], consists of
58 eight partial differential equations (PDEs) [18-20], while the simpler form (no
convective terms) includes six PDEs [21-24]. In this study, we selected
hydrodynamic transport models for electron only since the device studied is a
majority carrier MOSFET.
2.3.3 Generation-Recombination Models
There are 11 kinds of Generation-Recombination Models in DESSIS, but
we only need to consider Shockley-Read-Hall Recombination, Auger
Recombination and Avalanche Generation models because only these three
models are useful in this study.
2.3.3.1 Shockley-Read-Hall Recombination
Recombination through deep levels in the gap is usually labeled
Shockley–Read–Hall (SRH) recombination. Electron-hole recombination is an
important mechanism for returning carrier concentrations to their equilibrium
values. Phonon emission can occur during this recombination process in the
presence of a trap (or defect) within the forbidden gap of the semiconductor. This
is essentially a two-step process, the theory of which was first derived by
Shockley and Read and then by Hall [2]. The recombination rate is given by
2 SRH np − ni,eff Rnet = (2.7) τ p (n + n1) +τ n ( p + p1) where n and p are the electron and hole concentration at the site and
59 Etrap kT n1 = ni,eff e (2.8)
and
−Etrap kT p1 = ni,eff e (2.9)
where Etrap is the difference between the defect level and the intrinsic level. For
the semiconductor, the Silicon default value is Etrap = 0 , and ni is the intrinsic
concentration, the electron and hole τ n and τ p lifetimes, respectively, are
modeled as a product of doping-dependent, field-dependent and temperature-
dependent factors.
2.3.3.2 SRH (Shockley-Read-Hall) Recombination Doping-dependent Model
The doping dependence of the SRH lifetimes is modeled in DESSIS with the
Scharfetter relation:
τ −τ τ (N ) = τ + max min (2.10) dop i min N 1+ ( i )γ N ref
where the dependence arises from D. Kendall’s experimental data [25] and the theoretical conclusion that the solubility of a fundamental, acceptor-type defect or a vacancy complex) is strongly correlated to the doping density [26-28]. In
DESSIS the coefficients of SRH model for Silicon are given in Table 2.1 [2]; for
Germanium and SiGe, the same parameters were used.
60 Table 2.1 Parameters of RSH Doping-Dependent Models for Silicon
Symbol Parameter name Electrons Holes Unit
taumin 0 0 s τ min
taumax −5 −6 s τ max 1×10 3×10
Nref 16 16 −3 N ref 1×10 1×10 cm
γ gamma 1 1 1
2.3.3.3 Auger Recombination
Auger recombination is a process in which an electron and a hole
recombine in a band-to-band transition, but the resulting energy is given off to another electron or hole. It occurs through a three particle transition whereby a mobile carrier is either captured or emitted when electron-hole recombination occurs. The underlying physics for such processes is unclear and normally a more qualitative understanding is sufficient [29]. This effect is explained as
resulting from exciton decay: at lower carrier densities, excitons which are
loosely bound electron–hole pairs increase the probability for Auger
recombination. Auger recombination is typically important at high carrier densities
such as in heavily doped regions or cases of high injection.
A The rate of band-to-band Auger recombination R is given by:
A 2 R = (Cn n + C p p)(np − ni eff ) (2.11) with temperature-dependent Auger coefficients [30][31][32]:
61 n ⎛ T T ⎞ ⎛ − ⎞ C (T ) = ⎜ A + B ( ) + C ( )2 ⎟.⎜1 + H e N0,n ⎟ (2.12) n ⎜ A,n A,n A,n ⎟ ⎜ n ⎟ ⎝ T0 T0 ⎠ ⎝ ⎠ p ⎛ − ⎞ ⎛ T T ⎞ N C (T) = ⎜ A + B ( ) + C ( )2 ⎟.⎜1+ H e 0, p ⎟ (2.13) p ⎜ A, p A, p T A, p T ⎟ ⎜ p ⎟ ⎝ 0 0 ⎠ ⎝ ⎠
where T0 = 300K . Default coefficients of Auger recombination model for Silicon are listed in Table 2.2[2], for Ge and SiGe , the same parameters were used.
Table 2.2 Coefficients of Auger Recombination for Silicon
Symbol 6 6 6 H(1) −3 AA[cm / s] BA[cm / s] C A[cm / s] N0[cm ]
Parameter Name A B C H N0
Electrons 0.67 ×10−31 2.45×10−31 − 2.2×10−32 3.4667 1×1018
Holes 0 .72 × 10 − 31 4.50×10−33 2.63×10−32 8.25688 1×1018
2.3.4 SiGe Mobility and Mobility Models in DESSIS
2.3.4.1 SiGe Mobility
High Mobility is critically important for semiconductor device; enhanced mobility means improved device performances: larger transconductance, faster device speed, higher cutoff frequency, faster buildup of source drain current with gate voltage for MOSFET. In this study, improved electron mobility by
Germanium mole fraction has been observed.
The electron mobility is an inverse parabolic function of the composition due to the presence of alloy scattering. The following curve Figure 2.4 shows the
62 mobility data for the unstrained alloy going to the values for the pure Silicon or
Germanium a the extremes at the composition range and the decreasing due to
alloy scattering at intermediate composition.
Figure 2.4 Variation of the electron mobility as a function of increasing Germanium
content [33]
For device applications, the SiGe layer is often doped and strained. The electron mobility decreases with an increase of impurity doping in Silicon-
Germanium, which is described in the subsequent section. The electron mobility in strained Silicon-Germanium exhibits an interesting behavior. Jiann S. Yuan ‘s paper has reported the minority and majority electron mobilities for unstrained and strained Si1-xGex alloys up to 30% in the Germanium content [34]. Figure 2.5
below shows the low-field majority drift electron mobilities for four different doping
17 18 19 20 levels (Nd=1×10 , 1×10 , 1×10 , 1×10 ) at 300K for the case of parallel and perpendicular transport. For SiGe HBTs, the perpendicular results are import. But
63 for the vertical channel SiGe MOSFET, the Ge concentration varies along the
channel length, which is perpendicular to the wafer surface so the results to
employ are not obvious.
Figure 2.5 Majority and minority carrier electron mobilities as a function of
Germanium content in Silicon-Germanium thin films on Silicon substrate
for different impurity concentrations [36].
The solid lines represent the unstrained Silicon-Germanium case, the
dashed lines represent the mobility parallel to the Silicon and Silicon-Germanium
interface µxx; the dot-dashed lines represent the mobility perpendicular to the
Silicon and Silicon-Germanium interface µzz. As a general trend, the mobility is
64 reduced with increasing Germanium content at low doping concentrations by
alloy scattering, which dominates over impurity scattering in this regime. The
importance of alloy scattering in the total scattering rate is reduced when the
impurity doping concentration is higher. For the transverse mobility µzz, the strain- induced reduction of the average effective mass in the z-direction increases µzz ; on the other hand , the increasing alloy scattering decreases µzz. We also can
see that on comparing with the mobility in unstrained Silicon-Germanium, µxx in
strained SiGe has less reduction [36]. At low doping, the out-of-plane electron
mobility in strained Silicon-Germanium is also lower than that in Silicon. At higher
doping levels, where ionized impurity scattering is expected to dominate, the out-
of-plane electron mobility in strained Silicon-Germanium is expected to exhibit an enhancement [37] [38].
For Silicon-Germanium vertical MOSFETs, the channel is perpendicular to
the surface of substrate; hence, the current between source and drain is
perpendicular to the surface of the wafer, the enhanced electron’s µzz mobility will induce a higher drive current. How ever, when the MOSFET is operating, the electrons are moving in the inversion layer under the gate, where the electrical field which is perpendicular to gate is very strong, especially for the deep submicron MOSFET. This transverse field causes increased scattering off the surface, due to surface roughness and interface charge scattering, so the
mobility in inversion layer will be reduced very much as shown in Figure 2.6.
65
Figure 2.6 Inversion layer mobility for electrons in silicon as a function of the
magnitude of the transverse electric field [39].
2.3.4.2 Mobility Models in DESSIS
The constant mobility model is switched on by default in DESSIS. In
general, DESSIS uses a modular approach for the description of the carrier
mobilities. In the simplest case, the mobility is a function of the lattice
temperature. But the constant mobility should only be used for undoped
materials. For doped materials, the carriers scatter increasingly with the addition
of impurities. This leads to a degradation of the mobility with increased doping.
The mobility also degrades at interfaces, in high electric fields and by carrier–
carrier scattering. If more than one mobility model is activated, the different
mobility contributions are combined according to the following scheme –following
Mathiessen’s rule [1]:
1 1 1 1 1 = + + .... + + ... (2.14) µ µb1 µb2 µs1 µs2
In this study, the substrate materials are not only silicon but also include
66 Germanium which will change the mobilities too. In DESSIS, the electron
mobilities for undoped Silicon and Germanium are 1417 cm2 / v.s and
3900 cm2 / v.s , respectively; the hole mobilities for undoped Silicon an Germanium
are 470.5 cm2 / v.s and 1900 cm2 / v.s respectively [2]. For SiGe, we use interpolation between these as described below.
2.3.4.3 Doping-Dependent Mobility Degradation
In doped semiconductors, scattering of the carriers by charged impurity ions leads to degradation of the carrier mobility. DESSIS supports two models for doping-dependent mobility. In this study, we used the default model. The default model used by DESSIS to simulate doping-dependent mobility in Silicon was proposed by Masetti [40] and is given by
Pc µconst − µmin 2 µ1 µdop = µmin1 exp(− ) + − N N a C β (2.15) i 1+ ( i ) 1+ ( s ) Cr Ni
where Ni is the ionized impurity concentration and µmin1,µmin 2 ,µ1 are reference
mobilities, Pc , Cr and Cs are the reference doping concentration, α and β are
exponent parameters, where µconst is given by
−ς ⎛ T ⎞ ⎜ ⎟ µconst = µL ⎜ ⎟ (2.16) ⎝ T0 ⎠
where µL is the mobility due to bulk phonon scattering, T is the lattice temperature, and T0 =300k. The values of µL and ς for Si and Ge are given in
67 Table 2.3.
Table 2.3 Constant Mobility Coefficients for Silicon and Germanium [2]
Symbol(material) Parameter Electrons Holes Unit name mumax 1417 470.5 2 µL (Silicon) cm /(Vs)
ς (Silicon) exponent 2.5 2.2 1
mumax 3900 1900 2 µL (Germanium) cm /(Vs)
ς (Germanium) exponent 1.6 2.3 1
For the Si1− xGex included in the MOSFET’s simulation, both electron and hole’s mobilites are dependent on the Germanium mole fractio. The constant mobility coefficients were caculated by using a linear interpolation applied between the two kinds of materials, i.e.
P = x ∗ P(Germanium) + (1− x) ∗ P(Silicon) (2.17) where P(m) is a parameter of the material m and x is the Germanium mole
fraction. We summarize the constant mobility coefficients for Si1− xGex in Table
2.4 below.
68 Table 2.4 Constant Mobility Coefficients for Si1− xGex alloy
Symbol(material) Parameter Electrons Holes Unit name mumax 1417(1- 470.5(1- 2 µL ( Si1-xGex) cm /(Vs) x)+3900x x)+1900x
ς ( Si1-xGex) exponent 2.5(1- 2.2(1- 1
x)+1.6x x)+1.3x
The corresponding values of Masetti model for both Silicon and Germanium are given in Table2.5 [2]:
Table 2.5: Coefficients of Masetti Model for Si , Ge and SiGe [2]
Symbol Parameter name Electrons Holes Unit
mumin1 52.2 44.9 2 µmin1 cm /(Vs)
mumin2 52.2 0 2 µmin 2 cm /(Vs)
Mu1 43.4 29.0 2 µ1 cm /(Vs)
Pc 0 16 −3 pc 9.23×10 cm
Cr 16 17 −3 Cr 9.68×10 2.23×10 cm
Cs 20 20 −3 Cs 3.34×10 6.10×10 cm
α Alpha 0.680 0.719 1
β beta 2.0 2.0 1
69 2.3.4.4 High Field Saturation
Because the channels of our devices are about 100nm long, the electric
fields along the channel are very high when the drain bias is several volts and the
devices are working. In high electric fields, the carrier drift velocity is no longer
proportional to the electric field strength; instead, the velocity saturates at a finite
speed. DESSIS supports different models for the description of this effect, we
chose the Canali model [41] in this study. The Canali model [59] originates from
the Caughey–Thomas formula [42], but has temperature-dependent parameters,
which were fitted up to 430 K by Canali et al. [42], and is given by
µlow µ(F) = 1/ β β (2.18) ⎡ ⎛ µ F ⎞ ⎤ ⎢1+ ⎜ low ⎟ ⎥ ⎜ v ⎟ ⎣⎢ ⎝ sat ⎠ ⎦⎥
where µlow denotes the low field mobility, F is the electric field strength and the
β exponent is temperature dependent according to:
β ⎛ T ⎞ exp ⎜ ⎟ β = β0 ⎜ ⎟ (2.19) ⎝ T0 ⎠ where T denotes the lattice temperature and T0 = 300 K. The Canali model parameters for Si, Ge and SiGe are the same and are listed in Table 2.6[2]:
70 Table 2.6: Canali Model Parameters
Materials Symbol Parameter Electrons Holes Unit name
Si,Ge,SiGe beta0 1.109 1.213 1 β0
Si,Ge,SiGe betaexp 0.66 0.17 1 βexp
If more than one mobility model is activated, the different mobility contributions
are combined together using (2.14) and (2.15).
2.3.4.5 Mobility Degradation at Interfaces
In the channel region of a MOSFET, the high transverse electric field from
gate bias forces carriers to interact strongly with the semiconductor–insulator
interface. Carriers are subjected to scattering by acoustic surface phonons and
surface roughness. The Lombardi model [43] describes the mobility degradation
caused by these effects. DESSIS enhances the standard Lombardi model with
an additional equation to include a free carrier and doping dependence in an
exponent [44]. In Lombardi model, the surface contribution due to acoustic
phonon scattering has the form:
λ B C(Ni / N0 ) µac = + 1/ 3 K (2.20) F⊥ F (T /T0 )
where T is lattice temperature , T0 is 300k, F is the electric field along the
channel, F⊥ is the perpendicular electric field due to the gate bias, Ni is the total
71 concentration of ionized n-type and p-type impurities, N0 is reference doping
3 concentration which is 1/ cm , B,C,λ and K are modeling parameters.
The contribution attributed to surface roughness scattering is given by [2]
∗ −1 ⎛ (F / F ) A F 3 ⎞ µ = ⎜ ⊥ ref + ⊥ ⎟ sr ⎜ ⎟ (2.25) ⎝ δ η ⎠
where F⊥ is the perpendicular electric field due to the gate bias, Fref is the
* reference electric field which is 1V / cm , A ,η andδ are modeling parameters.
According to another study [44], an improved fit to measured data is achieved if
∗ A is instead given by
∗ α⊥ (n + p) A = A + (2.21) ((Ni + N1)/ Nref )
The mobilities of carriers are combined according to Mathiessen’s rule:
1 1 1 1 = + + (2.22) µ µb µac µsr
where µb is the bulk mobility. Coefficients of Lombardi for silicon are given in
Table 2.7.
72 Table 2.7 Coefficients of Lombardi for Silicon
Symbol Parameter Electrons Holes Unit
B B 7 6 4.75×10 9.925×10 cm/ s
C C 2 3 (5 / 3) 5 / 3) 5.80×10 2.947 ×10 cm (V s)
N0 N0 1 1 1
λ Lambda 0.125 0.0317 1
K K 1 1 1
delta 14 14 2 δ 5.82×10 2.0546×10 cm (Vs)
A A 2 2 1
alpha 0 0 3 α⊥ cm
N1 n1 1 1 −3 cm
ν nu 1 1 1
η eta 30 30 2 5.82×10 2.0546×10 V /(cms)
1_crit −6 −6 cm icrit 1×10 1×10
These parameters are used for Germanium except the bulk mobility is
different. For SiGe alloy, the mobility is formed as described above by linear
interpolation using (2.17).
2.3.5 SiGe Band Structure and Bandgap Model in DESSIS
In device simulation, the energy bandgap, the intrinsic carrier
73 concentration, the band edge density of states and the carrier effective masses are some of the most crucial properties of a semiconductor material. In doped semiconductors, the effective bandgap is a function of the doping concentration, which causes it to decrease with increasing doping. DESSIS supports four models of bandgap narrowing for Silicon: BennettWilson, OldSlotboom,
Slotboom, and delAlamo [2]. Because these models descrive the effects on the intrinsic carrier concentration, they are known as effective intrinsic density models.
2.3.5.1 SiGe Bandgap
Both Silicon and Germanium are indirect bandgap; Silicon has six equivalent minima in conduction band and Germanium has eight equivalent minima in conduction band. We can see the difference from Figure 2.7.
Figure 2.7 Equivalent conduction band minima in Germanium (8) and Silicon (6).
[45]
74 Germanium has an energy bandgap of about 0.7eV so that Germanium is doped into the bulk Silicon, the energy bandgap will be lower. This is a very important reason for Germanium incorporation in the channel of the Silicon
MOSFETs, as the reduced bandgap provides a lower barrier at the source end of the channel that improves device performance. The bandgap reduction with increasing Germanium based on a set of material parameter measurements has been given by C. Penn et. al. [46]. The bandgap variation with Germanium can be described by the two equations which are only fits for the unstrained Silicon-
Germanium (x is the mole fraction of Germanium in Silicon) case:
E ()x = 1.155 − 0.43x + 0.206x2 for x < 0.25 g (2.23) Eg ()x = 2.010 −1.27x for 0.85 < x < 1.00
The Figure 2.8 shows the two regions. From the Figure 2.8, we can see the experimental results and the equations devised to describe the behavior of bandgap with increasing Germanium concentration fit each other very well.
75 Figure 2.8 Energy bandgap for Si1-xGex alloy as a function of the composition for
the bulk semiconductor [46]. The solid line is from the measurement
results; the broken line is obtained from analytical expression.
When SiGe is grown epitaxially on silicon, it is compressively strained.
Silicon-Germanium is cubic semiconductor; the biaxial stress causes a lifting of degeneracy in the conduction and valence bands, [47, and 48]. For the valence band, the effect of the stress is to remove the coincidence of the light and heavy hole bands at k=0(г) as shown in Figure 2.9, for Silicon-Germanium grown lattice matched on Silicon. The heavy hole band moves above the light hole band.
Similarly, the strain causes a splitting of the degenerate bands in the conduction band. Because the strain causes splitting of the degenerate subbands in both the valence and conduction band, it causes an additional reduction in the energy bandgap as shown in Figure 2.10. It can be seen that the reduction in the energy bandgap is therefore a result of both the composition (germanium content) and the formation of strain due to the larger lattice constant of Silicon-Germanium with respect to Silicon. The behavior of the energy bandgap in strained Silicon-
Germanium for a mole fraction (X<0.25) can be given as follows [46]
2 Eg ()x = 1.171−1.01x + 0.835x (2.2)
76
(a)
(b)
Figure 2.9 Splitting of the valence band due to biaxial stress (a) and conuction band
(b)[47]
77
Figure 2.10 Energy bandgap for strained and unstrained Silicon-Germanium with
increasing Germanium mole fraction [47].
In addition, when we dope n and p type impurities in Silicon and
Germanium, both exhibit a reduction in the energy bandgap with heavy doping.
Because the semiconductor materials used for devices are not intrinsic, we will
discuss both n-type and p-type Si1-xGex. For heavily doped P-type, Z. Matutinovic
Krystelj, et. al. [34] have given a empirical mathematical formula to explain the behavior of bandgap variation not only with increasing Germanium concentration, but also including heavy doping effects (bandgap shrinkage), which is given by
⎛ N B ⎞ ∆Eg,eff ()x, N B = 28.6 + 27.4log10 ⎜ ⎟ + 688x (meV ) (2.24) ⎝1x1018 / cm3 ⎠
In this equation, x is the Germanium mole fraction, so that the effect of the
Germanium addition is given by
∆Eg,eff (x) ≈ 688x(meV) (2.4) [49]
78 We have incorporated this equation in our device modeling. For the SiGe
strained channel vertical MOSFET, this will be important at the source end of the
channel due to the BF2 implant used to dope the p-type channel region.A graph
demonstrating the effective bandgap narrowing for different doping levels p-type
Si1-xGex as calculated by the above equation and related experimental data is shown below in Figure 2.11
Figure 2.11 Effective bandgap reductions in p-type SiGe as a function of the
Germanium mole fraction for several doping levels [34, 49]
For heavily doped n-type Silicon-Germanium, the Figure 2.12 shows the
bandgap reduction with both increasing doping and Germanium content, where
the dashed line corresponds to the dependence on Germanium content for the
undoped Silicon-Germanium. This will have some effect on the bandgap in the
source and drain regions for the vertical channel MOSFETs studied here.
79
Figure 2.12 Bandgap reductions in n-type Si1-xGex [50].
The total energy bandgap reduction for the Si1-xGex alloy grown on Silicon is given by the sum of the contributions due to Germanium incorporation and strain effect plus the effects of heavy doping.
2.3.5.2 SiGe Bandgap Models in DESSIS
In DESSIS, several models of the bandgap are offered. The bandgap of semiconductor is not a constant but varies temperature can be expressed by the function [51]:
αT 2 E (T) = E − (2.25) g g0 (T + β )
80 where T is the lattice temperature and Eg0 is the bandgap energy at 0 K. The
temperature variation of the bandgap is equally distributed between the
conduction and valence bands. Each effective intrinsic density model has a
different default value for Eg0 . To support this variation, a correction termδEg,0 is
introduced, and the following modification to Eg0 is applied:
Eg0 = Eg,0 + δEg,0 (2.30)
In DESSIS, the default of Silicon energy bang gap is 1.1696ev and that of
Germanium is 0.744ev when the temperature is 0k. The intrinsic SiGe bandgap is Germanium mole fraction dependent. The parameters of bandgap narrowing with temperature for Silicon are described in Table 2.8 and for Germanium in
Table 2.9.
Table 2.8 Parameters of Bandgap Narrowing with Temperature for Silicon
Symbol Parameter name Default Unit
Eg,0 Eg0 1.696 eV
α alpha 4.73×10−4 eV/K
β beta 636 K
81 Table 2.9 Parameters of Bandgap Narrowing with Temperature for Germanium
Symbol Parameter name Default Unit
Eg,0 Eg0 0.744 eV
α alpha 4.77×10−4 eV/K
β beta 235 K
For Si1-xGex, all parameters have been linearly computed to vary Germanium as shown in Tabel 2.10. ISE can only change the bandgap of SiGe linearly; it does not offer the model for the bandgap of the strained SiGe. This model gives
∆Eg (x) = 952x (meV) versus the experimentally reported value
∆Eg (x) = 688x (meV) reported above so our modeling results may overestimate the effects of the incorporation on the bandgap.
Table 2.10 Parameters of Bandgap Narrowing with Temperature for Si1-xGex
Symbol Parameter name Default Unit
Eg,0 Eg0 0.744x+1.696(1-x) eV
α alpha 4.77×10−4 x+ 4.73×10−4 (1-x) eV/K
β beta 235x+636(1-x) K
2.3.5.3 Electron Affinity
The electron affinity is defined as the energy separation between the
82 conduction band and the vacuum level and defaults to the value for Silicon of
4.05 eV and for Ge is 3.5988 eV. The bandgap Eg, and values of for each model
are accessible in the BandGap section of the parameter file, in addition to the
electron affinity and the thermal bandgap narrowing parameters. In DESSIS, all
parameters can be specified at any reference temperature. By default, the band
parameters are defined at absolute zero. The electron affinities of Silicon,
Germanium and Si1-xGex are shown in Table 2.11.
Table 2.11 Electron affinity of Silicon, Germanium and Si1-xGex
Symbol Parameter name Default Unit
Electron affinity χ (Silicon) Chi0 4.05 eV
Electron Chi0 3.96 eV/K affinity χ (Germanium) Electron affinity χ (Si1-xGex) Chi0 3.96x+4.05(1-x) eV
2.3.5.4 Energy Bandgap Narrowing and Electron Affinity Changes with
Doping
As described above, the doping level increases, a decrease in the energy
bandgap occurs. The modification of density of states by heavy doping effects is
modeled by assuming a rigid downward shifting in the energy bandgap. In
DESSIS, the distribution of the band edge shift can be controlled by the parameter Bgn2Chi [2]:
χ = χ0 + Bgn2Chi*∆Eg (2.26)
Where χ denotes the electron affinity, χ 0 is the default electron affinity, ∆Eg is
83 the change of bang gap. For Silicon and Ge, the value of Bgn2Chi is 0.5; the same 0.5 is used for SiGe here. Bandgap narrowing is considered to be a
function of the total doping concentration N A + N D .
DESSIS supports four models of bandgap narrowing for silicon, in this study; we used OldSlotboom Model which is based on an empirical formula for the bang gap narrowing,
⎡ 2 ⎤ ⎛ N ⎞ ⎛ ⎛ N ⎞⎞ ∆E = E ⎢ln⎜ ⎟ + ⎜ln⎜ ⎟⎟ + 0.5⎥ (2.27) g bgn ⎢ ⎜ ⎟ ⎜ ⎜ ⎟⎟ ⎥ ⎝ N ref ⎠ ⎝ N ref ⎠ ⎣⎢ ⎝ ⎠ ⎦⎥
This formula was established by Slotboom and de Graaff [52-55] who suggested using it on P-type materials. In DESSIS, it is used in both N type and P type materials for Silicon. Parameters for Oldslotboom are shown in table 2.12. There is no bandgap narrowing model for Germanium in DESSIS; for SiGe, we chose
Oldslotboom model too, so all of the parameters are the same as those of
Silicon.
Table 2.12 Parameters of Bandgap Narrowing Oldslotboom Model for Silicon
Symbol Parameter name Default Unit
Ebgn Ebgn 0.009 eV
−17 −3 Nref Nref 1×10 1/ cm
2.3.6 Mechanical Stress Modeling
Band structure changes when mechanical distortion of semiconductor
84 microstructures happens. This effect of the change in the strain-induced band structure is based on the deformation potential theory [56]. The model for mechanical stress model in DESSIS is based on the data and approaches presented in the literature [56-59]. In the deformation potential theory, the change in energy of each valley, caused by the deformation of the lattice, is a linear function of the strain. Strain tensor can be computed using the generalized Hook law from the appropriate stress tensor. Both conduction and valence energy level can be calculated in DESSIS. The default model for Silicon was used in the vertical channel SiGe MOSFETs studied here.
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93
Chapter 3:
Comparison of the Simulation
Results for a Vertically Strained
SiGe N-Channel MOSFET with a
Silicon MOSFET
The first part of this chapter discusses the simulation of the construction of the MOSFETs and the dimensions of the final device structures. It summarizes the fabrication process design and simulation of the Silicon control vertical channel MOSFET and the strained SiGe vertical channel MOSFET using the
DIOS simulator from ISE (Synopsis). It illustrates the important processes of fabrication and compares the results with published experimental results [1][2].
The second part of the chapter gives both DC and microwave small signal simulation results for the two devices and compares them with published experimental results [1][2]. We also investigate and discuss the advantages in performance that are achieved due to Germanium incorporation in the channel region of an otherwise Silicon control MOSFET. In this study, we only focus on
94 the N channel MOSFET, comparing the performance of the strained SiGe vertical
channel MOSFET with a Si control MOSFET.
3.1.1 Device Design Considerations
The device geometry and doping profiles determine the final structure of a
device which influences the device’s performance. For Silicon MOSFET, the
electrical characteristics are determined by the device’s physical parameters,
such as the gate oxide thickness, the channel length and the source/drain
impurity distribution. For the SiGe MOSFET, Germanium distribution in channel
is also an important factor. In this study, we model the performance of the SiGe
vertical channel MOSFET reported by Chen et al. [1] [2] shown in Figure 3.1,
where the height of the transistor is 0.25 µm , the channel lengths of both
transistors are about 0.15 µm and the channel width is 1 µm . If the distance between the two vertical gates is too large, then the channel will not be full depleted and there may be a kink effect [3]. To avoid the kink effect, the thickness of the region between the two gates is selected to 0.2 µm . The
Source/Drain series resistance also affects the transistor performance. As shown
in Figure 3.1, in this study, the source is on the top of channel and its resistance
is fixed. In practice, they are formed by lateral diffusion of the drain’s doping
beneath the channel region. The drain contacts are at the bottom of the vertical
FET, if they are too far from the channel, the performance of transistors will be degraded. The distance between Drain contacts and the edge of channel was chose to be 0.2 µm . According to the published papers [1][2], for the SiGe vertical
95 channel MOSFET, a peak value of the Germanium mole fraction of 15% was
used in the channel where the Ge peak was located 1500 Å below the top
surface.
Figure 3.1 Schematic view of the strained vertical channel SiGe MOSFET of
Chen et al. [1, 2].
3.1.2 Fabrication Designs and Simulation
The fabrication of the two devices is compatible with the standard planar
CMOS fabrication process, so the fabrication steps are mainly designed from the desired transistor structure described by the previous papers [1][2]. For the SiGe vertical channel NMOSFET, the starting substrate is <100> Si with a resistivity of
10 ohm-cm p-type (For NMOSFETs) wafer. Summarized in Figure 3.2 is the
96 simulated flow of the fabrication process used in the DIOS simulator. Initially,
photoresist covers the wafer and is patterned for masking for reactive ion etching
(RIE) to form the mesa region for the vertical channel MOSFET. The width of the
mesa is 0.1 µm and the height of the mesa is 250nm. After RIE, a Silicon
polishing etch and a sacrificial oxide are used to remove the RIE-induced
damage. This was followed by 10 nm rapid thermal oxidation (RTO) for gate
oxide growth and then polysilicon deposition. An anisotropic etch was used to
form a self-aligned side-wall polysilicon gate on the vertical two sides of the
mesa. Germanium with a dose 7×1016 / cm2 at 200 keV was implanted into the
wafer for the SiGe channel vertical MOSFET. The solid phase epitaxy (SPE) of
the SiGe films was done by subsequent furnace annealing at 590 degree for 60
min after the Germanium implant. The following step is the channel BF2 implant,
this process is two stages, 85kev, 7×1013 / cm2 and 55keV,5×1013 / cm2 conditions
were used. As implant with dose of 1×1016 / cm2 at 15 keV was used to form the source and drain. Channel Boron and source & drain Arsenic implantation are done after that. RTA (rapid thermal annealing) follows the implants to anneal the implant damage. The processes after annealing are the same as the standard
CMOSFET processes: SiO2 is deposited on the surface of wafer for isolation, contact windows are etched by RIE, Aluminum metallization is achieved by sputtering the metal, and the last photoresist layer is used for metal patterning which is done by RIE. In this study, the DIOS files of the final structures of the transistors with their impurity distributions are saved after the fabrication simulation is finished as input files for the device simulation. The silicon control
97 NMOSFET fabrication flow has the same fabrication processes except it does not
have the Germanium implantation process. This minimizes the possibility of
differences in the channel length and thermal budget between the Silicon and
SiGe transistors.
The process simulation flow of strained SiGe vertical channel NMOSFET is described in figure 3.2:
98
Figure 3.2 SiGe MOSFET fabrication flow.
99 3.1.3 Strained SiGe vertical channel NMOSFET Fabrication and Si Control
Vertical NMOSFET Fabrication Steps
The key steps and profiles of SiGe MOSFET fabrication are shown in the
Figure 3.3. We explain processes on the left hand side, the consequent profiles
of fabrication are shown on the right.
Step 1: Mesa etch
Anisotropic etching model is used to etch any area which is not covered by photo resist. Etching stop model is set after 250nonameter of the Si substrate has been etched.
(a)
Step 2: Gate oxidation
After the sacrificial oxidation and sacrificial oxide etching, 10nm of high quality silicon dioxide is grown on the surface by dry oxygen oxidation process.
(b)
Step 3: Polysilicon deposition
Polysilicon is deposited by isotropic chemical vapor deposition (CVD) process on the surface of wafer.
(c)
100 Step 4: Gate polysilicon etch
Poly silicon is etched by self-align etching process. Etch stop is set when oxide appears on the surface of substrate, and 30% over etch is set to make sure that there is no resident except the sidewalls of the mesa.
(d)
Step 4: Channel Germanium implant and Germanium solid state epitaxy
Channel Germanium implant: Dose= 7×1016 / cm2 , energy=200keV, tilt=0
The following thermal treatment process is annealing 60 minutes under the temperature of 590 degree.
(e)
Step 5: Channel BF2 implant and Source/Drain implant
Channel BF2 implant step1: Dose= 7×1013 / cm2 ,energy=85keV,tilt=0
Channel BF2 implant step2: Dose=5×1013 / cm2 ,energy=55keV,tilt=0
Source/Drain As implant: Dose=1×1016 / cm2 ,energy=15keV,tilt=0 (f)
101
Step 6: Isolation Oxide Deposition
After channel and source/drain diffusion process, 500nm isolation oxide is gown on the surface of substrate by CVD.
(g)
Step 7: Metallization
A metal Masking process has been done; the metal Al is etched by dry etch process, only Al of 2 drains and source electrode are left .When the metallization is done, the device fabrication process is over.
(h)
Figure 3.3 Process steps and device profiles of the SiGe vertical Channel
MOSFETs fabrication process.
102
The SiGe MOSFET process simulation results are shown in Figure 3.4.
Drain Source Drain
Polysilicon Polysilicon Gate Gate
Substrate
(a)
Source Polysilicon Gate
Gate Oxide Channel
Drain
(b)
Figure 3.4 Schmetic diagram of SiGe vertical MOSFET fabrication including (a) transistor profile with contacts and grids and (b) close-up of Channel, gate oxide and ploysilicon gate.
103 The processes of silicon vertical channel NMOSFET are identical to that of
Silicon-Germanium MOSFET expect that the silicon control device has no
Germanium implantation process.
3.1.4 Final Structure of Strained SiGe and Si Vertical Channel NMOSFETs
3.1.4.1 Structure of Transistors
After the fabrication process simulation is completed using the software
DIOS, the data structure file for the transistor is loaded into TECPLOT so that the structures of the transistors can be observed. Figure 3.5 (a) (all units of the coordinates are µm ) shows the physical dimensions of the strained SiGe vertical channel NMOSFET, which is the same as the Si control vertical MOSFET. Figure
3.5 (b) shows the schematic structure for the SiGe vertical MOSFET reported by
Chen et al. [1][2]. Figure 3.6(a) shows both transistors’ metallurgical channel lengths are about 0.14 µm , which is 0.01 µm shorter than we expected. The junction depth of source is about 0.1 µm . Figure 3.6 (b) shows the two
dimensional Germanium profile in the SiGe MOSFET. As a result of the implant process, the Ge concentration is large near the source end of the channel. The average gate oxide thickness is about 10nm as seen from Figure 3.7, which is the same for both devices.
104 Drain Source Drain
Polysilicon Polysilicon Gate Gate
Substrate
(a)
105
(b)
Figure 3.5 Transistor structure for (a) SiGe MOSFET and Si control MOSFET and (b) reported strained vertical channel SiGe MOSFET of Chen et al. [1, 2]; the shading of source, drain,substrate and channel in Figure 3.5(a) means net doping level of impurities, darker area means heavier impurity doping in this area, the right hand side legend is the shading and net impurity concentration contrast.
In Figure 3.5(a), we cannot see the gate contacts and electrodes; the reason is because our simulators are two dimensional. If we show the gate contacts, we will not see one of the drain contacts and the process and device simulation will be more complicated. For simplicity, we assume the polysilicon gates have good ohmic contact with the unseen gate electrodes of transistors.
106 Source
Gate Oxide Polysilicon Gate
Channel
Channel Length
Drain
(a)
Source Polysilicon Gate
Gate Oxide
Channel
Drain
(b)
Figure 3.6 (a) Net doping in channel for SiGe MOSFET and Si control MOSFET and (b) Ge two dimensional profile in the SiGe MOSFET. The legend of (a) shows the net doping. The legend of (b) shows the contrast of color and Ge mole fraction.
107
Source
Gate Oxide
Polysilicon Gate
Channel
Figure 3.7 Cross-section of the device for the gate region showing the about
10nm gate oxide thickness for the SiGe MOSFET and Si control MOSFET.
3.1.4.2 Doping Profile in the Channel and Source Regions
The MOSFET’s electrical characteristics are influenced by the device’s
structure and the distribution of impurities in channel. We drew a cutline at x=0 in
Figure 3.5(a) (center of the device) and obtained the profile data along this line
shown in this section. Figure 3.8 shows the Boron and As concentration
distributions are the same in the SiGe MOSFET and Si control MOSFET
108 because both transistors have the same Boron and As implantation processes
and thermal treatment history. The peak Boron concentration is
1.52×1019 / cm3 located a the depth of 0.0505 µm where the Boron profile is the results of a two step Boron implant at energy of 85kev and 7×1013 / cm2 dose followed by a 55kev implant at 5×1013 / cm2 dose. Figure 3.8(b) shows the As
profile due to a 15kev implant at 1×1016 / cm2 dose where the peak concentration is 1.44×1021 / cm3 located at a depth of 0.012 µm .
As Distribution Along Channel
1.00E+22 1.00E+21 SiGe 1.00E+20 MOSFET Si Control
) 1.00E+19 MOSFET
m3 1.00E+18 c / 1.00E+17 ms
to 1.00E+16 A ( 1.00E+15 1.00E+14 1.00E+13 1.00E+12 0 0.05 0.1 0.15 0.2 0.25 0.3 Y Direction Distance from the top of Source to Drain
(a)
109 Boron Distribution Along Channel 1.00E+20
1.00E+19 SiGe MOSFET Si Control ) 1.00E+18
3 MOSFET m /c
s 1.00E+17 m to
(a 1.00E+16
1.00E+15
1.00E+14 0 0.05 0.1 0.15 0.2 0.25 0.3 Y Direction Distance from the top of Source to Drain
(b)
Figure 3.8 Arsenic (a) and Boron (b) distributions in SiGe MOSFET and Si control MOSFET channels. Where y=0.012 is the top surface of the source region.
Figure 3.9 shows the combination of B and As profile and the location of the source junction. From the figure, we find the junction depth of the sources in both transistors is about 0.11 µm where Boron and Arsenic have the same concentration of 8×1018 / cm3 . From Figure 3.6(a), we can observe that the channel drain metallurgical junction is located at 0.25 µm . After the mesa was etched in the fabrication process, the goal of the height which is determined by the mesa dry etch process is 0.25 µm . Because there is lateral diffusion, the As in drain diffuses into the channel. Where the channel B concentration reaches the
110 concentration of As near the drain region, that is the location of the channel drain
junction.
Impurites Distribution Along Channel
1.00E+22 1.00E+21 As in SiGe 1.00E+20 MOSFET Channel
) 1.00E+19 As in Si 3 Control
m 1.00E+18 MOSFET c / Source Drain Boron in s 1.00E+17 SiGe m MOSFET
to 1.00E+16 Boron in Si
(A 1.00E+15 Control 1.00E+14 1.00E+13 1.00E+12 0 0.1 0.2 0.3 0.4 Y Direction Distance from the top of Source to Drain
Figure 3.9 Boron and Arsenic impurity distributions in channels of both
transistors.
For the vertical NMOSFET, the doping profiles were not reported by Chen
et al. [1][2] for the N channel device, but only for the PMOSFET. The Boron and
Phosphorus SIMS profiles they reported are shown in Figure 3.10. Although they are for a different type transistor (p-channel instead of n-type), they are very similar in structure to our transistors because they are fabricated using the same fabrication process except that the doping of the regions were interchanged.
Comparing our profiles to theirs, we find that the junction depths of the source
111 and the channel length of our transistors are almost the same as the transistors reported by Chen et al. [1][2].
Figure 3.10 SIMS profiles along the vertical channel for the SiGe PMOSFET reported by Chen et al. [1]
3.1.4.3 Germanium Mole Fraction in Channel
For the SiGe MOSFET, Germanium in the transistor channel has been implanted using Ge atoms at 200kev with a dose of 7×1016 / cm2 . As a result, the
Germanium mole fraction is largest near the source end of the channel and almost linearly distributed along the channel after the solid phase epitaxy process. Figure 3.11 shows the Germanium mole fraction distribution logarithmically (a) and on a linear scale (b) along the channel from the top of source to the bottom of the channel at the drain (The cut line of profile is at x=0 in
Figure 3.5 (a)). The peak point of the mole fraction is about 10.9% and the Ge decreases to 0.3% at the drain junction.
112 Log Ge Mole Fraction Distribution Along Channel 1 00.00.0 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.2 0.2 0.2 0.2 0.2 0.3 2 4 6 8 2 4 6 8 2 4 6 8
n 0.1 o i t c a Fr e r 0.01 o M
e Source Channel Drain
0.001 Log G
0.0001 Y Direction Distance from the top of Source to Drain
(a)
Ge Mole Fraction Distribution Along Channel 0.12 0.11 0.1 0.09 n o i 0.08
act 0.07 r F 0.06 e Channel r Source Drain
o 0.05 M
e 0.04
G 0.03 0.02 0.01 0 00.00.0 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.2 0.2 0.2 0.2 0.2 0.3 2 4 6 8 2 4 6 8 2 4 6 8 Y Direction Distance from the top of Source to Drain
(b)
Figure 3.11 Germanium distributions along the channel of SiGe MOSFET shown using a logarithmic scale (a) and a linear scale (b).
113 3.1.4.4 Bandgap and Band Structure of SiGe MOSFET Channel
Germanium and strain both change the material properties as we have discussed in Chapter 2. Shown in Figure 3.12 is the energy bandgap along the channel of the SiGe MOSFET. The source junction is located at 0.11 µm and the drain junction at 0.25 µm , so the banggap of SiGe increases along the channel
as Germanium mole fraction decreases. In this study, we used the OldSlotboom
bandgap narrowing model for SiGe Bandgap, when the default Si bandgap is
1.10812eV when the device is at 300K. In the SiGe MOSFET channel, the
smallest bangap is about 1.032eV at the source end of the channel and the
difference in the bandgap along the channel is about 0.076eV. So for a channel
length of 0.14 µm , the strength of the quasi-electric field along the channel is about 0.076eV/q*0.14 µm =5.47×103V / cm .
114 SiGe MOSFET Channel Bandgap Along Channel 1.12 1.11 1.1 )
V 1.09 e
p ( 1.08 Source Channel Drain ga 1.07 nd a
B 1.06 1.05 1.04 1.03 00.00.0 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.2 0.2 0.2 0.2 0.2 0.3 2 4 6 8 2 4 6 8 2 4 6 8 Y Direction Distance from the top of Source to Drain
Figure 3.12 Energy Bandgap along the channel of SiGe MOSFET.
Shown in Figure 3.13(a) and (b) are the conduction band profiles and
valence band profiles comparing the SiGe and Si control MOSFETs. From the
figures, we can see that the conduction band level in the channel of SiGe
MOSFET is lower than those of Si control NMOSFET. While the valence band
profile is nearly unchanged. This conduction band change is very similar to the results reported by Chen et al. [2] as shown in Figure 3.14. The change in conduction band profile illustrates the variation in the barrier height between source and channel is smaller in the SiGe MOSFET than that in Si control
MOSFET.
115 Conduction Band Along the Channel 1.2 V)
e 1
( SiGe
gy MOSFET 0.8
er Si Control
n MOSFET E
d 0.6
n Source Channel
a Drain B 0.4 on i t a 0.2
onduc 0 C 00.0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. -0.2 02 04 06 08 1 12 14 16 18 2 22 24 26 28 3 Y Direction Distance from the top of Source to Drain
(a)
Valance Band Along the Channel
0 00.0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. ) SiGe V -0.2 02 04 06 08 1 12 14 16 18 2 22 24 26 28 3
e MOSFET (
y Si Control g -0.4 MOSFET er n E
d -0.6 n
a Source Channel Drain B -0.8 ce n a l
a -1 V
-1.2 Y Direction Distance from the top of Source to Drain
(b)
Figure 3.13 Conduction band (a) and valence band (b) profile along the channel of SiGe MOSFET and Si control MOSFET.
116
Figure 3.14 Conduction band profile of the Si and SiGe vertical channel MOSFET along the channel reported by Chen et al. [2].
3.1.4.5 Electron Mobility in the Channel
Figure 3.15 shows the mobility profile of electrons in the channel of the SiGe
MOSFET and Si control MOSFETs. The electron mobility is seen to be enhanced in the SiGe channel where the data are obtained under the condition of VDS=0.1v.
The electron mobility for the vertical SiGe NMOSFET has been found to be
enhanced by as much as 10% over the Si control transistor.
117 Electrcon Mobility Distribution 1200 )
.s 1000
/v SiGe
2 MOSFET
m Si Control c 800
( MOSFET y t ili
b 600 Mo
n 400
o Source r
t Channel Drain c e
l 200 E
0 00.00.0 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.2 0.2 0.2 0.2 0.2 0.3 2 4 6 8 2 4 6 8 2 4 6 8 Y Direction Distance from the top of Source to Drain
Figure 3.15 Electron mobility profile along the channels of SiGe and Si transistors.
Chen et al et al. [1][2] did not report the electron mobility data directly, but observed the mobility enhancement by the drain current which was improved about 50%[1]. The enhanced electron mobility arises from the combination of the
Germanium and the strain [1][2]. This enhanced electron mobility will help explain the large transconductance obtained for the SiGe MOSFET seen in the following section and reported in the literatures[1][2].
3.2 Device Simulation Results
The simulator DESSIS receives the data structure file from the DIOS process simulation results and uses it to perform the device performance simulation. INSPECT is used to extract the data for plots from the transistor
118 simulation results. In this section, we examine the results of our simulations for
the Si and SiGe vertical channel MOSFETs as well as compare them with
experimental results reported by Chen et al. [1][2].
3.2.1 Threshold Voltage (VT)
The threshold voltage is a key parameter of the MOSFET. In this study,
we defined the threshold voltage as the x axis intercept of max slope of the Id vs
Vg curve. Figure 3.16 shows the curves of IDS vs VDS under the condition of
VDS=0.1v for our device, we extracted the threshold voltages of SiGe MOSFET
and Si control MOSFET as 1.849v and 2.089v, respectively.
Id vs Vg Curves of SiGe MOSFET and Si control MOSFET
3.50E-04
3.00E-04 Si Control 2.50E-04 MOSFET
2.00E-04 ) SiGe (A 1.50E-04
Id MOSFET 1.00E-04
5.00E-05
0.00E+00 012345 -5.00E-05 Vg(v)
Figure 3.16 Id vs Vg curves of SiGe and Si transistors.
119 The SiGe NMOSFET’s VT is 0.24V lower than that of Si control NMOSFET
where the main reason of the difference is the smaller band gap of the SiGe
channel layer. The Germanium decreases the barrier height of the conduction
band at the source and of the channel, so that a lower voltage on gate can
produce electron injection from the source and formation of the inversion layer in
SiGe channel. Figure 3.17 is the IDS vs VDS curves from Chen et al’s paper [1].
From these curves, we can estimate the threshold voltage of this SiGe MOSFET is between 3-2.5V for a drain current10−6 A and the threshold voltage difference is about 0.3V. This is normally close to your results. Although we used nearly the same fabrication conditions as the published paper[1], the threshold voltages my transistors are not as large those reported by Chen et al. [1][2]. This difference is due to the fact that we cannot match the source/drain resistance, channel width and some experiment fabrication steps like the thermal treatments.
Figure 3.17 Id vs Vg curves of SiGe and Si MOSFET reported by Chen et al. [1].
120
3.2.2 Transconductance
Electrons in SiGe NMOSFET channel have a higher mobility than in the Si control NMOSFET as we observed in the previous section, which means SiGe
MOSFET can be expected to have a higher tranconductance. The calculated transconductance in the linear and saturation regions for the SiGe NMOSFETs and Si control NMOSFET are shown in Fig 3.18.
Transconductance of SiGe MOSFET and Si control MOSFET
) 2.50E-04 m m / 2.00E-04 s Si Control MOSFET 1.50E-04 ance (
1.00E-04 SiGe MOSFET 5.00E-05
ansconduct 0.00E+00 Tr 012345 -5.00E-05 Vg(v)
(a)
121 Transconductance of SiGe MOSFET and Si control MOSFET when Vds=2.5v 4.50E-03
4.00E-03
3.50E-03 Si Control
) MOSFET m 3.00E-03 m / s (
e 2.50E-03 SiGe nc a t 2.00E-03 MOSFET
duc 1.50E-03 on c s
n 1.00E-03 a r T 5.00E-04
0.00E+00 012345678 -5.00E-04 Vg(v)
(b)
Figure 3.18 Transconductance of SiGe MOSFET and Si control MOSFET at
VDS=0.1v (a) and VDS=2.5v (b).
The data of Figure 3.18(a) are extracted in the linear region of MOSFET
operation when the source to drain voltage is 0.1v. The SiGe MOSFET shows
better performance than the silicon control MOSFET, where the peak
transconductance for the graded SiGe NMOSFET is 0.199mS/mm, while it is
0.18 mS/mm for the Si control MOSFET. This is an improvement of about 10%
which is consistent with the about 10% imcrease in the electron mobility reported
above. At high transverse fields (large gate biases, the improvement in the
transconductance for the SiGe MOSFET becomes smaller because the
transconductance becomes surface-roughness-scattering limited. Shown in
Figure 3.19 are the reported results for the transconductance when VDS=0.1v where Chen et al reported that the SiGe MOSFET has about 50% improvement over the Si control MOSFET from 0.30ms/mm to 0.45ms/mm.
122 When the transistor is operated in the saturation region (VDS = 2.5v), the
simulated peak transconductance of the SiGe NMOSFET was found to be
3.89mS/mm compared to 3.62mS/mm for the control Si NMOSFETs as shown in
Figure 3.18(b). Again, this corresponds to an improvement of about 7.5%. Figure
3.19(b) shows Chen et al’s[1][2] transconductance for the comparison of SiGe
MOSFET and Si control MOSFET transconductance when VDS=2.5v. They reported again, a larger enhancement of about 50% from a peak transconductances of 4ms/mm to 6ms/mm.
(a)
123
(b)
Figure 3.19 Transconductance comparison of the SiGe NMSOFET and Si
control MOSFET reported results [1][2]: (a) VDS=0.1v ;(b) VDS=2.5v [1].
3.2.3 Output Current – Voltage Characteristics
Both the SiGe vertical channel NMOS and Si control NMOS show good output current performance. Figure 3.20 (a) shows the output current of SiGe
MOSFET compared with the Si control MOSFET in 0.5v gate voltage increments above the threshold voltage. In each case, the drive currents for the SiGe
NMOSFET are higher than those of the Silicon control device, which is expected from the larger electron mobility in the channel. When VDS=1.5v, VGS=VT+2v, the current of SiGe MOSFET is 5.2% higher than that of Silicon-control MOSFET.
Since the SiGe channel device and Si control device are fabricated in the same wafer and Germanium mole fraction in the drain and source layers are very low,
124 the difference of the source/drain series and contact resistance in the two
devices can only contribute a little to the current difference. The electron mobility
enhancement in the channel is the primary reason for the higher drive capability.
For comparison, Figure 20(b) shows the ID (VDS, VGS) characteristics reported by
Chen et al. [1]. The MOSFET shows better performance than the Si control
MOSFET. Comparing with pervious results, our transistor drive current improvement is smaller, which is constant with the smaller transconductance reported above.
125 Si and SiGe MOSFET Id vs Vd
3.00E-03 Dotted lines are Si MOSFET IDS vs VDS when VGS-Vt=0v, 2.50E-03 0.5v, 1v, 1.5v, 2v
2.00E-03 Solid lines are SiGe MOSFET IDS vs VDS when VGS - Vt=0, 0.5v, 1v, 1.5v, 2v 1.50E-03 ) A
( 1.00E-03 Id
5.00E-04
0.00E+00 00.511.522.5 -5.00E-04
-1.00E-03 Vd(v)
(a)
(b)
Figure 3.20 OutSiGe MOSFET and Si control MOSFET IDS vs VDS curves for our devices (a) and results reported by Chen et al. (b) [1].
126 3.2.4 Subthreshold Threshold Characteristic
The MOSFET’s subthreshold behavior is very important for short channel devices and particularly for low-voltage, low power applications such as digital logic and memory circuits [3]. The simulated subthreshold characteristics of the strained SiGe vertical channel MOSFET and Silicon control vertical MOSFET are shown in Figure 3.21. Both devices have good but not excellent on-off characteristics, which are due to an increased control on the channel from the two gates for the vertical channel MOSFETs. In our results, we find that the SiGe vertical channel NMOSFET has better performance, where the SiGe MOSFET subthreshold swing is 135mV/dec and that of Si MOFET is 136mV/dec, however, neither transistor’s subthreshold performance is not very good since 60mv/dec is the optimal result desired. One of the important reasons is the gate oxide thickness of our transistors is 10nm when the channel dimension is less than
0.2 µm . This is too thick to provide good subthreshold characteristics. We will investigate the improvement of the subthreshold performance by changing the gate oxide thickness in the following chapter.
127 LogID vs VGS Curves of SiGe MOSFET and Si control MOSFET
1.00E+00 1.00E-01 00.511.522.53 1.00E-02 1.00E-03 SiGe 1.00E-04 MOSFE 1.00E-05 T 1.00E-06 Si
(A) 1.00E-07
D Control 1.00E-08
LogI 1.00E-09 1.00E-10 1.00E-11 1.00E-12 1.00E-13 1.00E-14 1.00E-15 VGS(v)
Figure 3.21 Log Id vs Vg for SiGe MOSFET and Si control MOSFET.
Figure 3.22 shows the subthreshold characteristic curves reported by
Chen et al. [1][2]. We can observe the SiGe transistor shows nearly the same subthreshold characteristic as that of Si control transistor, but the curves are not very steep. Chen et al did not offer the data of the subthreshold swing of his transistors in the paper. We can choose several points of the curve from his paper and calculate the subthreshold slope when the VGS changes from 2V to 3V, the corresponding log Id changes are about 4-5, the subthreshold swing is about
200mv/dec. Our results (about 134mv/dec) are somewhat better those of the published papers [1][2].
128
Figure 3.22 Subthreshold characteristics of SiGe and Si MOSFET reported by
Chen et al. [1]
3.2.5 Drain Induced Barrier Lowering (DIBL)
Since the gate length dimensions of these MOSFETs are very small, short channel effects will affect the device performances. Shown in Figure 3.23 are the subthreshold characteristics for the SiGe and Si control MOSFETs for Vds=0.1v and 1.1v. The extracted DIBL data for the SiGe transistor is 123mv/V and that of
Si control transistor is 115mv/v. From Figure 3.23, we also found the off-state
current for the Silicon-Germanium device is increased slightly because of the
lower barrier of the channel. Using Figure 3.22, Chen et al. [2] reported a DIBL of
0.2V/(2.5-0.1)V=83mv/V, for the SiGe transistor, which is significantly larger than
that for the SI control device. While our results are somewhat higher, we also find
a larger DIBL for the SiGe MOSFET due to the Ge’s effect of reducing the
129 bandgap at the source end of the channel. Comparing with reported by Chen et al in 3.22, our device leak currents are very low.
SiGe and Si MOSFET DIBL(Drain induced barried lower)
1.00E+00 1.00E-01 012345 1.00E-02 1.00E-03 SiGe 1.00E-04 Vd=1.1v SiGe 1.00E-05 Vd=0.1v 1.00E-06 Si
) Vd=1.1v
A 1.00E-07 Si ( 1.00E-08 Id Vd=0.1v 1.00E-09 1.00E-10 1.00E-11 1.00E-12 1.00E-13 1.00E-14 1.00E-15 Vg(v)
Figure 3.23 SiGe and Si transistors Subthreshold characteristics for Vds=0.1V and 1.1V.
The graded doping of the channel in the vertical channel MOSFET also produces a lower longitudinal electric field near the drain. Therefore, hot-carrier related reliability is improved substantially with this type of device. We can observe the electrical field in channels of the two transistors in Figure 3.24. In the
SiGe MOSFET, the electric field is generally lower along the channel except for a small region of width 0.01um at the drain.
130 Electrical Field Distribution Along Channel 250000
) 200000 Vd=2v, Vg=Vt+1v SiGe m MOSFET c /
v Si MOSFET (
d 150000 e l Fi 100000 cal i r Source Channel Drain ect l
E 50000
0 00.0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 02 04 06 08 1 12 14 16 18 2 22 24 26 28 3 Y Direction Distance from the top of Source to Drain
Figure 3.24 Electrical fields along the channels of SiGe MOSFET and Si control
MOSFET.
3.2.6 RF Simulation Results
With decreasing the gate length of MOSFET, the MOSFET’s speed is
higher and the device has become more attractive for RF applications. For small-
signal applications, the cutoff frequency fT is the most important and often used figure of merit for a transistor. High cutoff frequency MOSFETs of 193 GHz have been reported by some researchers [5]. The mobility of strained silicon- germanium is higher than silicon in the channel so that the fT of the SiGe
MOSFET is excepted to be higher than that of Si control MOSFET. The cutoff
frequencies of both strained SiGe vertical channel NMOSFET and Si control
131 vertical NMOSFET have been simulated and the results are shown in Figure
3.25.
SiGe and Si Control MOSFET Maxmium Cut-off Frequency (Ftmax) 40
SiGe 35 MOSFET Si Control 30 MOSFET 25 Vd=2.5V ) z 20 H (G
T 15 F 10
5
0 0 5 10 15 20 25 -5 Vg(v)
Figure 3.25 Cutoff frequency fT for SiGe MOSFET and Si control MOSFETs as a function of gate bias.
The peak fT of Silicon control vertical NMOSFET is 34.1GHz, while that of
SiGe vertical NMOSFET is 36.8GHz when the gate voltage is about 2.6V. The
SiGe MOSFET’s cutoff frequency is about 8% higher than that of Si control vertical NMOSFET; due to the higher mobility seen in the SiGe channel. Chen et al. [1][2] did not report any cutoff frequency measurement for their devices.
Although both transistors got good AC performance, the high threshold voltages
132 and thick gate oxide limit the transconductance and cutoff frequency. In the next chapter we examine to improve the AC performance of the SiGe MOSFET.
3.3 Summary
In this chapter, we have described the simulation of the fabrication and device simulations of the vertical SiGe and Si control MOSFETs. The device structure files were subsequently used in the simulation of the operation of the strained SiGe vertical NMOSFET and the Si control vertical NMOSFET.
Investigated were the subthreshold DC, small signal RF characteristics of both transistors. The SiGe transistors showed a measurable improvement about 10% over than the Si control device in the transconductance and cutoff frequency. We have also compared our device simulation results with published experimental results with reasonable agreement found. Because the pervious papers only offered some performance results and a partial description of the fabrication conditions, there must be some differences between the simulated and experiment processes which can account for some of between the experimental differences device simulation results. In general, we found the simulation results agree qualitatively with the experimental results.
In the following chapter, we will focus on the optimization of the SiGe
MOSFET and describe the effects of various material and structural parameters on the performance of the device. We will change the channel Boron implant dose to adjust the threshold voltage to a reasonable range and examine the effect of the Germanium mole fraction and distribution on the device’s
133 performance. We also examine in the next chapter the effects of channel length on the RF performance of SiGe MOSFET.
134 Bibliography
[1] C.Xiangdong, “Hole and Electron mobility enhancement in strained SiGe
Vertical MOSFETs,” IEEE Transactions on Electron Devices, vol. 48, pp.
1975-1980, 2001.
[2] C.Xiangdong, “Electron mobility enhancement in strained SiGe vertical n-
type metal-oxide-semiconductor filed-effect transistors,” Applied Physics
Leters, vol. 78, N.3, 15 January, 1974.
[3] Taur and T. Ning, “Fundamentals of Modern VLSI Devices,” Chapter 3,
pp126 Cambridge University Press, Cambridge, UK, 1998.
[4] S. Narasimha, A. Ajmera, H. Park, and K.A. Jenkins, “High-performance
sub-40nm CMOS devices on SOI for the 70nm technology node,” IEDM
Technical Digest, pp. 625-628, 2001.
135
Chapter 4:
Optimization of Device Fabrication
and Device Design for Vertical
Graded Channel Silicon-
Germanium MOSFETs
Chapter 3 described the fabrication flow and the simulation results of both
the Silicon control and the SiGe vertical MOSFETs. But the simulated device
performances were not very good. Some of the key parameters of the devices such as threshold voltages were not in the reasonable range (<2V) for a submicron MOSFET. In this chapter, we vary and optimize the fabrication flow by starting with the channel BF2 implant to try to get better performance for the
SiGe transistor. The threshold voltage can be adjusted to be compatible with size
(2V) of the drain voltage Vdd. Second, the germanium amount in the channel can
be varied. Where the Germanium amount and distribution determines the
bandgap and electron mobility as well as other properties in the channel. An
136 increase in the Germanium content is accomplished though increasing the
germanium implant dose while keeping the implant energy fixed at 200KeV.
Since the channel length of the MOSFETs is a key parameter, we also do scaling
of the channel length and observe the change of the electrical characteristics of the devices when the channel of SiGe is smaller than 0.10um. For simplicity, in this chapter, we call the strained SiGe vertical chanel NMOSFET as the SiGe
MOSFET and the Si control vertical channel NMOSFET as the Si MOSFET. As a starting point and baseline for comparison we use the SiGe MOSFET structure defined in last chapter. In this chapter, since we need to analyze the profiles of many transistors, all the transistors will be cut from the line at x=0.07, which is
0.03um from the gate oxide of the transistors.
4.1 Effect of Variation in Channel Doping and Gate Oxide on Simulation
Results
4.1.1 Threshold Voltage Optimization
When the channel length is about 0.15 µm , the target threshold voltage of
MOSFET VT is about 0.5v, for a supply voltage Vdd of about 2 volts [1].
Otherwise, the transistor can not adequately switch between the on and off states or the leakage amount is too big. If the threshold voltage is too high, in addition the current drive capability will be too low. If the threshold voltage is very low, the leakage between source and drain will be too big when the device is turned off. This is a tradeoff with which we must be concerned. In the chapter 3, the SiGe vertical MOSFET threshold voltage was about 1.8v and that of the Si
137 control MOSFET was over 2v. Obviously, the threshold voltages of the
transistors described in chapter 3 were not reasonable in practice so that they
need to be adjusted to about 0.5V, which is the first task undertaken in this
chapter.
The simple MOSFET theory equation for VT for the N-channel MOSFET is given by [2]
4ε si qN a ΨB Vt = V fb + 2ΨB + (4.1) Cox
KT Na where ΨB = ln( ) and the equation shows the dependence of the threshold q Ni
voltage on the channel doping (Na and ΨB ), oxide thickness tox (since Cox=εox/tox) and gate electrode work function (through Vfb). Vfb is called the flatband voltage and is decided by the material properties of the metal, semiconductor and oxide.
So the easiest traditional and best way to adjust the threshold voltage is to change the channel doping. In chapter 3, the channel BF2 implant process was performed in two steps, which may not be necessary. Here we will simplify the
BF2 implant process to one step. We did some DOE (design of experiment) of the one step channel BF2 implant, which is described in this chapter. In the pervious chapter, we found that for both the both SiGe MOSFET and Si control
MOSFET the junction depth of the source is 0.1 µm and the channel length is
about 0.15 µm . In the optimization process, to keep the source channel junction depth the same, the peak point of the channel BF2 distribution should not be
changed, so we keep the BF2 implant energy condition the same. We then
examined the effect of varying the BF2 implant dose using seven different doses
138 of 1×1014 / cm2 ,1.2×1014 / cm2 , 1.4×1014 / cm2 , 1.6×1014 / cm2 , 1.65×1014 / cm2 ,
1.7 ×1014 / cm2 and 1.8×1014 / cm2 . For this study, all other process simulation conditions were not changed. After the process and device simulation, we obtained the corresponding threshold voltages shown in Table 4.1 where the relationship of channel implantation dose and threshold voltage is shown in
Figure 4.1.
Table 4.1 DOE of SiGe MOSFET Channel BF2 Implant Dose and VT
Experiment No. 1 2 3 4 5 6 7
Channel BF2 1×1014 1.2 ×1014 1.4 ×1014 1.6 ×1014 1.65×1014 1.7 ×1014 1.8×1014 Implant Dose
(#/ cm2 )
Threshold 0.206 0.301 0.393 0.486 0.510 0.533 0.741 voltage VT(v)
139 SiGe MOSFET Vt vs BF2 Implant Dose (tox=10nm)
0.8
0.7
0.6
0.5 ) 0.4 t(v V 0.3
0.2
0.1
0 7.00E+13 9.00E+13 1.10E+14 1.30E+14 1.50E+14 1.70E+14 1.90E+14 BF2 Implant Dose (#/cm2)
Figure 4.1 Threshold voltages of SiGe MOSFET vs BF2 implant dose for a fixed
implanted energy of 200KeV.
The threshold voltage is seen to increase rapidly with the increase of BF2
implant dose, particularly alone above1.7 ×1014 / cm2 . To get appropriate
threshold voltage of about 0.5V for the SiGe MOSFET, the channel BF2 implant
14 2 dose of 1.65×10 / cm was chosen. The corresponding VT is 0.5095 which is
suitable for a 0.15 µm MOSFET. The Id-Vg relationship for this choice of VT is shown in Figure 4.2.
140 SiGe MOSFET Id vs Vd when BF2=1.65E14
7.00E-04
6.00E-04
5.00E-04
) 4.00E-04 A (
Id 3.00E-04
2.00E-04
1.00E-04
0.00E+00 01234 Vg(v)
Figure 4.2 Drain current versus gate bias for a SiGe MOSFET with a dose
14 2 1.65×10 / cm for a VD of 2V.
We can compare the structure of this transistor with the adjusted threshold voltage SiGe MOSFET we simulated in Chapter 3. Figure 4.3 shows the simulation doping profiles of the two transistors, where the X axis is the distance along the channel and the left hand side Y axis is the concentration while the right hand side Y axis is Germanium mole fraction. For better comparison of the transistors, we named the SiGe MOSFET prototype which was simulated in the last chapter as the original transistor and named the SiGe MOSFET with 0.51V threshold voltage as the optimized transistor in this and the next sections.
Because the Germanium and Arsenic distributions of the two transistors are almost the same, we only need to compare the Boron concentrations in the two transistors.
141 B, As and Ge Distribution along channel in Original and Optimized Transistors 1.00E+22 12% OOptriginalimized B B 1.00E+21 As 1.00E+20 10% OptimizedOriginal B B 1.00E+19 Ge 1.00E+18 8% G e M o
1.00E+17 l e )
F r ac m3 1.00E+16 6% c / ti on (# 1.00E+15
1.00E+14 4% Source Channel Drain 1.00E+13
1.00E+12 2%
1.00E+11
1.00E+10 0% 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22 0.24 0.26 0.28 0.3 Y Direction along the channel(um)
Figure 4.3 Doping profiles along the channels of the original SiGe MOSFET and
the optimized SiGe MOSFET.
From Figure 4.3, we can observe that the two channel lengths are not
much different; the channel of the original transistor is 0.136 µm and that of the optimized transistor is 0.138 µm .The junction depths of the sources are nearly
the same at about 0.1 µm . The optimized threshold device has less BF2 in the
channel so that it is has a lower, more reasonable threshold voltage of about
0.5V.
Figure 4.4 shows the comparison of the drive current of the original
transistor and the optimized transistor, the optimized transistor shows better
142 output current performance. When VDS=1.5v, the current of optimized MOSFET is 15% higher than that of original MOSFET.
Comparison of Id vs Vd for original SiGe MOSFET and threshold optimized MOSFET
3.00E-03 Vt+2V(optimize d) Vt+2V(original) 2.50E-03 Vt+1.5V(optimiz ed) 2.00E-03 Vt+1.5V(original ) Vt+1V(optimize d) 1.50E-03 Vt+1V(original) ) Vt+0.5V(optimiz Id(A ed) 1.00E-03 Vt+0.5V(original ) Vt(optimized) 5.00E-04 Vt(original)
0.00E+00 00.20.40.60.811.21.41.61.82
-5.00E-04 Vg(V)
Figure 4.4 Id vs VD for the original SiGe and the threshold voltage optimized
MOSFET.
Figure 4.5 is the transconductance comparison for the original transistor and the optimized transistor when the transistors are operating in the linear region. The optimized transistor has a higher peak tranconductance that is about
36% higher than that of the original transistor. This is approximately three times the enhancement (10%) we saw in chapter 3 for the SiGe MOSFET over the Si
MOSFET.
143 Transconductance Comparison of original and optimized SiGe MOSFETs
3.00E-04
2.50E-04
2.00E-04 Vds=0.1V
1.50E-04 Original (s/mm)
m Optimized g
1.00E-04
5.00E-05
0.00E+00 0 0.5 1 1.5 2 2.5 3 3.5 4 Vg(v)
Figure 4.5 gm vs VG for the original SiGe and the threshold voltage optimized
MOSFET.
Subthreshold performances of the two transistors are shown in Figure 4.6.
The optimized transistor’s subthreshold slope is 98.2mv/dec, which is much better than the original transistor’s 136mv/dec subthreshold slope. Here, the optimized transistor has better on-off switching characteristics i.e., its drain current is more sensitive to the change of the gate voltage.
144 Subthreshold performance comparison of original and optimized SiGe MOSFETs
1.00E+00 1.00E-01 00.511.522.533.54 1.00E-02 1.00E-03 1.00E-04 1.00E-05 1.00E-06 ) A 1.00E-07 Original d ( 1.00E-08 Optimized LogI 1.00E-09 1.00E-10 1.00E-11 1.00E-12 1.00E-13 1.00E-14 1.00E-15 Vg(v)
Figure 4.6 Log ID vs VG for the original SiGe and the threshold voltage optimized
MOSFET.
We also compared the RF simulation results of the two transistors. The
optimized transistor has a peak cutoff frequency fT of 44.2 GHz, which is about
20% higher than the original SiGe MOSFET peak cutoff frequency of 36.8 GHz.
The cutoff frequency vs gate voltage comparison of the two transistors is shown in Figure 4.7. From this figure, we can find that the optimized transistor has much better RF performance than the original transistor over a wide range of gate voltage.
145 Cutoff frequency comparison of original SiGe and Threshold voltage optimized SiGe MOSFET 50
45 Optimized FT 40 Original FT 35 ) 30
cy (GHz 25 n e u q 20 fre ff 15 Cu-o
10
5
0 1.5 3.5 5.5 7.5 9.5 11.5 13.5 15.5 17.5 19.5 -5 Vg(v)
Figure 4.7 Cutoff frequency comparisons of the original SiGe MOSFET and the optimized SiGe MOSFET.
4.1.2 Gate Oxide Optimization
In the last section, we adjusted the threshold voltage of the SiGe MOSFET to about 0.5v by changing the channel BF2 implant process. To improve the performance of the transistor, we also need to consider changing other parameters of the device structure such as the gate oxide thickness. The original
10 nm gate oxide is very thick for a deep submicron transistor. If we decrease the gate oxide thickness, we can improve the device’s transconductance, cutoff frequnency and subthreshold swing. But decreasing it too much will cause
146 excessive direct tunneling to the gate. We change the gate oxide thickness by
changing the gate oxidation condition in DIOS.
We did a series of gate oxidation experiments by DIOS; Table 4.2 is the
threshold voltages of the transistors which have different gate oxide thicknesses
but the same channel doping conditions. We can observe the threshold voltages
have shifted a lot. The reason is we increased the Cox in the equation (4.1), which results in the threshold voltage decreasing dramatically. We can show the relationship of the threshold voltage and the gate oxide thickness in Figure 4.8.
Table 4.2 Threshold voltage comparison of the SiGe MOSFET with different Tox
Experiment No. 1 2 3 4 5
Tox(nm) 10 8 7 6 4
Vt(v) 1.849 1.501 1.0825 0.2485 No output
147 SiGe MOSFET with different Gate oixde thicknesses Vt vs Tox
2
1.8
1.6
1.4
1.2 (V)
t 1 V
0.8
0.6
0.4
0.2
0 456789101112 Tox(nm)
Figure 4.8 Threshold voltage vs gate oxide thickness Tox for SiGe vertical channel MOSFET.
The transistors with thinner gate oxide are expected to have a higher tranconductance, because under the same condition of Vdd, the output current of transistor is more sensitive to the changing of Vg. We can observe the relation of the peak transconductance of the transistors with different gate oxide thicknesses from in 4.3 and Figure 4.9. As can be seen, reducing tox from 10 nm to 4 nm produced approximately a ten fold increase in the peak gm.
148 Table 4.3 The peak gm comparison of SiGe MOSFET with different Tox
Experiment No. 1 2 3 4 8
Tox(nm) 10 8 7 6 4
Peak gm (ms/mm) 0.199 0.301 0.305 0.549 1.91
SiGe MOSFET with different Gate oixde thicknesses Transconductance vs Tox 0.0025
0.002
0.0015 (s/mm) m g 0.001
0.0005
0 45678910 Tox(nm)
Figure 4.9 Transconductance of SiGe MOSFET vs gate oxide thickness Tox.
The subthreshold characteristics of the SiGe MOSFETs for various oxide thicknesses are shown in Figure 4.10. We can observe that the transistors with thinner gate oxide have better subthreshold behaviors. But we can also see that when the oxide decreases, the threshold voltage decreases and the leakage current increases at the same time. We tried to measure the subthreshold slopes when the transistors’ gate oxide thickness is 6nm and 4nm, but there was
149 insignificant data. For the thinner oxide, because the leakage current of these
transistors was over the limit of the off-state current of 10−8 A when the Vd is 0.1V and Vg is 0.
SiGe MOSFET with different Gate oixde thicknesses Log Id vs Vg
1.00E+00 00.511.522.53 1.00E-01 1.00E-02
1.00E-03 1.00E-04 1.00E-05 1.00E-06 Tox=10n m )
A Tox=8n
( 1.00E-07
d m I 1.00E-08 Tox=7n
Log m Tox=6n 1.00E-09 m Tox=4n 1.00E-10 m 1.00E-11 1.00E-12
1.00E-13 1.00E-14 1.00E-15 Vg(V)
Figure 4.10 Subthreshold characteristics of the SiGe MOSFETs with different
gate oxide thickness.
The SiGe MOSFETs’ subthreshold slopes are shown in Table 4.4 and
Figure 4.11. As the gate oxide thickness decreases, the subthreshold slope
improves as we expected, for a reduction in Tox from 10 nm to 7 nm, the S goes
from 136 to 108 mv/dec, an improvement of about 21%.
150 Table 4.4 Subthreshold Slop Comparison of SiGe MOSFET with Different Tox
Experiment No. 1 2 3 4 5
Tox(nm) 10 8 7 6 4
Subthreshold 136 125 108 No output No output slope(mv/dec)
SiGe MOSFET with different Gate oixde thicknesses Subthreshold slop vs Tox 140
135
130 ) c e d /
v 125 m ( p o l
s 120 d l ho es
hr 115 bt Su 110
105
100 6789101112 Tox(nm)
Figure 4.11 Subthreshold slop of SiGe MOSFET vs gate oxide thickness Tox.
To get these better performances of SiGe MOSFET, we changed the gate oxide thickness from 10 nm to 4 nm. For completeness here, the profile of the new transistor is shown in Figure 4.12 and the comparison of the structure of the new transistor with the previous SiGe transistor in Figure 4.13.
151
Figure 4.12 Profile of SiGe MOSFET with 4nm gate oxide.
Figure 4.13 Channel profile comparison of 4nm gate oxide SiGe MOSFET and
10nm gate oxide SiGe MOSFET (Left hand side: 4nm, right hand side: 10nm)
We see that the structure of new transistor is not much different from the
SiGe MOSFET in chapter 3, though the gate oxide difference is obvious. As we have discussed previously in this section, when we decrease the gate oxide thickness tox of the MOSFET, because Cox=εox/tox, Cox will increase, and
152 4ε qN Ψ according to the equation (4.1), si a B will decrease, so the threshold Cox voltage will shift downward. To keep the threshold voltage at about 0.5v, we need
increase the channel BF2 implant dose Na . Similar to the earlier DOE for the 10
nm gate oxide SiGe MOSFET BF2 implant, we examined the various BF2
implant dose conditions for the 4nm gate oxide SiGe MOSFET. After running the
process and device simulations, we get the Id-Vg curves of the four different
SiGe MOSFETs seen in Figure 4.14.
Id vs Vg with Different Dose (Tox=4nm)
2.00E-03 1.80E-03 1.60E-03 1.40E-03 1.20E-03 BF2=2E15/cm2 ) BF2=3E15/cm2 A ( 1.00E-03 BF2=3.5E15/cm2 Id 8.00E-04 BF2=4E15/cm2 6.00E-04 4.00E-04 2.00E-04 0.00E+00 01234 Vg(v)
Figure 4.14 LogId vs Vg for 4nm gate oxide SiGe MOSFET for various BF2
channel implants.
The corresponding threshold voltages of four SiGe MOSFETs are given in
Table 4.5. According to the results above, we get the trend line of threshold
153 voltage vs channel BF2 dose for the 4nm gate oxide vertical channel SiGe
MOSFET shown in Figure 4.15.
Table 4.5 Threshold Voltage vs Channel BF2 Implant Dose for 4nm Gate Oxide
SiGe MOSFET.
Experiment No. 1 2 3 4
Channel BF2 Implant Dose 2E15 3E15 3.5E15 4E15
(#/ cm2 )
Vt(v) 0.2345 0.4562 0.5527 0.6317
SiGe Vt vs BF2 Implant Dose (tox=4nm)
0.7
0.6
0.5
) 0.4 t(v
V 0.3
0.2
0.1
0 1.50E+15 2.00E+15 2.50E+15 3.00E+15 3.50E+15 4.00E+15 4.50E+15 BF2 Implant Dose (#/cm2)
Figure 4.15 VT vs BF2 implant dose for 4nm gate oxide SiGe MOSFET.
154 When the BF2 implant dose is3.5×1015 / cm2 , the threshold voltage of this
SiGe MOSFET is 0.5527v, which is a reasonable threshold voltage for a
MOSFET which has 0.15 µm channel and 4nm gate oxide. This transistor will be the prototype for further optimization in the following sections.
4.1.3 Comparison of Optimized SiGe MOSFET and Si Control MOSFET
In the last section, we did a series of simulations for different SiGe
MOSFETs with different channel implant conditions and then a series of simulations for various gate oxide thicknesses. In this section, we choose the
SiGe transistor with BF2=3.5×1015 / cm2 channel implant with a 4nm gate oxide as the prototype. To compare the SiGe MOSFET and Si control MOSFET, another process flow for Si control MOSFET which has no Germanium in channel was also simulated by DIOS at the same time when we did SiGe MOSFET simulation.
The only difference between the two transistors is that the SiGe transistor has the Germanium implant process. The dopant profiles for both the SiGe transistor and the Si control MOSFET are shown in Figure 4.16. Because the SiGe
MOSFET and Si control MOSFET have almost the same Boron and As distributions, we only show one Boron and As profiles in the graph. From Figure
4.16, we can observe the Germanium in SiGe MOSFET is almost linearly distributed in the channel.
155 SiGe MOSFET and Si MOSFET Boron, Arsenic Concentration and Ge Mole Fraction Distribution Along Channel 1E+22 8%
1E+21 7%
1E+20 6% 1E+19 Ge 5% Fr 1E+18 ac
Mo ) t i on l e m3 1E+17 4% c
/ Si B (# 1E+16 3% Si As 1E+15 2% 1E+14 SiGe Ge 1% 1E+13
1E+12 0% 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22 0.24 0.26 0.28 0.3 Y Direction distance (um)
Figure 4.16 Dopant profiles for SiGe MOSFET and Si control MOSFET.
Subsequently, device simulations were done using DESSIS using the
process simulation data files for the two transistors. Shown in Figure 4.17 is the
output current comparison of the SiGe MOSFET and Si control MOSFET.
Because the electron mobility of SiGe MOSFET is higher than that of Si control
MOSFET, we expect the drive capability of the SiGe transistor to be larger than
that of the Si MOSFET. When Vd = Vg-Vt =2v, the drive current for the SiGe
NMOSFET is 28% higher than that for the Si control device. This arises from the larger electron mobility in SiGe since in the saturation region, the current equation is given by
2 W (V −V ) I = µ C g t (4.2) ds eff ox L 2m
156 where m is body effect coefficient. In addition, from (4.2) we also see that when
the gate oxide thickness is decreased, the Cox will increase, the corresponding current increases. We can compare the output current in Figure 4.17 with the output current of Figure 3.35 in chapter 3. When the Vg-Vt=2V and Vds =2v, the new SiGe MOSFET output current for the device with tox=4nm is 4.3mA, which is
2.2 times of SiGe MOSFET output current in chapter 3 where the tox=4nm.
SiGe MOSFET and Si Control MOSFET Id vs Vd Curves
7.00E-03
6.00E-03
5.00E-03
SiGe 4.00E-03
) MOSFET
Id(A 3.00E-03 Si control MOSFET
2.00E-03
1.00E-03
0.00E+00 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Vd(v)
Figure 4.17 Output characteristics of the graded SiGe vertical NMOSFET and Si control MOSFET for Vg-Vt from 0 to 2V in 0.5V step.
Figure 4.18 and Figure 4.19 show the comparison of threshold voltages of SiGe MOSFET and Si control MOSFET. Because of the channel bandgap differences, the Si control’s threshold voltage is 0.253V higher than that of the
157 SiGe MOSFET.
SiGe MOSFET and Si MOSFET Id vs Vg
8.00E-04
7.00E-04
6.00E-04
5.00E-04 ) SiGe MOSFET
(A 4.00E-04 Si MOSFET Id
3.00E-04
2.00E-04
1.00E-04
0.00E+00 0 0.5 1 1.5 2 2.5 3 3.5 4 Vg(v)
Figure 4.18 Id vs Vg for SiGe MOSFET and Si control MOSFET.
The transconductance of the SiGe MOSFET is expected to be higher than that of Si control MOSFET, due to the enhanced electron mobility in SiGe. We can observe the results of the tranconductance enhancement in the linear region in Figure 4.19. When Vd is 0.1V, the peak transconductance of the SiGe
NMOSFET was found to be 0.508mS/mm compared to 0.476mS/mm for the control Si NMOSFETs as shown in Figure 4.18. This corresponds to an improvement of about 7%, which is consistent with our previous enhancements seen due to the mobility.
158 SiGe and Si MOSFET Transconductance comparison
6.00E-04
5.00E-04
4.00E-04
mm) Si MOSFET 3.00E-04 SiGe MOSFET gm(s/
2.00E-04
1.00E-04
0.00E+00 0 0.5 1 1.5 2 2.5 3 3.5 4 Vg(V)
Figure 4.19 Transconductance vs Vg for SiGe MOSFET and Si control MOSFET
when Vd=0.1V.
Figure 4.20 shows the subthreshold slopes of both 4nm gate oxide Si
vertical MOSFET and 4nm gate oxide SiGe MOSFET. At a drain voltage of 0.1V
and the drain current is1×10−8 A, the SiGe MOSFET subthreshold slope is
86.73mv/dec while that for the Si MOSFET is 89.7mv/dec. Both of them are
much better than the subthreshold slope of the 10nm gate oxide transistors in
chapter 3, where the subthreshold slopes were about 135mv/dec.
159 SiGe MOSFET and Si MOSFET Subthreshold Swing
1.00E+00
1.00E-01
1.00E-02
1.00E-03
1.00E-04
1.00E-05
1.00E-06
1.00E-07 SiGe MOSFET (A) 1.00E-08 Si MOSFET Id
1.00E-09
1.00E-10
1.00E-11
1.00E-12
1.00E-13
1.00E-14
1.00E-15 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Vg(v)
Figure 4.20 Comparison of Si MOSFET and SiGe MOSFET subthreshold ID vs
VD characteristics for a VD =0.1V.
Figure 4.21 shows the subthreshold Id vs Vg characteristics for the two devices for a change in drain voltage of 1.0V. Similar to the transistors in chapter
3, the SiGe MOSFET has a slightly worst DIBL performance than that of Si
MOSFET because the SiGe channel has a smaller bandgap; the DIBLs of SiGe
MOSFET and Si MOSFET are 49.8mv/v and 48.6mv/v, respectively.
160 Si and SiGe DIBL
1.00E+00
1.00E-01
1.00E-02
1.00E-03
1.00E-04
1.00E-05
1.00E-06 Si MOSFET Vd=0.1v 1.00E-07 Si MOSFET Vd=1.1v (A) 1.00E-08 SiGe MOSFET Vd=0.1v Id SiGe MOSFET Vd=1.1v 1.00E-09
1.00E-10
1.00E-11
1.00E-12
1.00E-13
1.00E-14
1.00E-15 00.511.522.533.544.5 Vg(v)
Figure 4.21 DIBL of 4nm gate oxide SiGe MOSFET and Si control MOSFET.
The RF simulation results for the two transistors were also investigated using DESSIS. Figure 4.22 shows the comprison of SiGe MOSFET and Si control MOSFET when Vd=2.5V. The SiGe MOSFET’s and Si control MOSFET’s peak cutoff frequencies were 48.42 GHz to 44.71GHz, respectively. Both of these performances are better than the corresponding 10nm gate oxide transistors, which had cutoff frequencies of 34.1GHz and 36.8GHz. Based on the approximation relationship between the fT, the gm and gate source and gate-drain capacitances Cgs and Cgd given by [3],
g m f T ≈ (4.3) 2π (C gs + C gd )
161 we can see that the increased transconductance is the reason for the cutoff frequency enhancement, which arises from the electron mobility enhancement in the strained SiGe.
Cutoff frequency comparison of SiGe MOSFET and Si MOSFET
50
48
46
44
42 )
z Si MOSFET H 40 G
( SiGe MOSFET ft 38
36
34
32
30 1 1.2 1.4 1.6 1.8 2 2.2 2.4 Vg(V)
Figure 4.22 Peak cutoff frequency vs Vg for SiGe MOSFET and Si control
MOSFET.
4.2 Effect of Variation in Germanium Mole Fraction on the Simulation
Results for the SiGe MOSFET
We use the SiGe MOSFET which has a 0.55v threshold voltage as the prototype and vary the Germanium mole fraction by using different Germanium implant doses in the channel. We split the Germanium channel implant process into 7 different conditions: 7E16/ cm2 , 1.05E17/ cm2 , 1.4E17/ cm2 , 1.75E17/ cm2 ,
2.05E12/ cm2 , 2.45E17/ cm2 , 2.8E17/ cm2 and examine the effects on device performance.
162 For this study, the Ge implant energy was not changed. The process
simulations for the eight transistors with the different Ge implant conditions were
done by DIOS. Figure 4.23 shows the Ge distributions in the channel after the
fabrication simulations for the eight transistors. The peak Ge mole fraction is
located about 0.08 µm under the surface of the source near the source end of the channel so that the Ge content decreases approximately linearly along the channel from the source to the drain.
Germanium Mole Fraction Distribution Along Channel
0.35
0.3 Ge Dose:0
Ge Dose:7E16/cm2
on 0.25 ti
c Ge Dose:1.05E17/cm2 fra
Ge Dose:1.4E17/cm2
le 0.2 Ge Dose:1.75E17/cm2
m mo 0.15 Ge u Dose:2.05E17/cm2 Ge ani Dose:2.45E17/cm2 m 0.1 Ge Dose:2.8E17/cm2 Ger
0.05
0 0 0.05 0.1 0.15 0.2 0.25 0.3 Distance from top of souce (um)
Figure 4.23 Ge Mole fraction distributions along the channel in different SiGe
MOSFETs.
Since the energy bandgap in SiGe is a function of the Ge mole fraction,
Figure 4.24 illustrates the corresponding bandgaps along the channel in the
163 transistors. Because the bandgap decreases with increasing Ge content, the corresponding flat-band voltage also decreases and the threshold voltage will go down. After the device simulations using DESSIS, we get the threshold voltages of the transistors from Figure 4.25; the threshold voltages of different Ge implant conditions as shown in Table 4.6.
SiGe MOSFET Bandgap Along Channel
1.15
1.1
Ge Dose:0 V) 1.05 Ge Dose:7E16/cm2 Ge Dose:1.05E17/cm2 ap (e Ge Dose:1.4E17/cm2
ndg 1
a Ge Dose:1.75E17/cm2
B Ge Dose:2.05E17/cm2 Ge Dose:2.45E17/cm2
0.95 Ge Dose:2.8E17/cm2
0.9 0 0.05 0.1 0.15 0.2 0.25 0.3 Distance from top of souce Along channel(um)
Figure 4.24 Energy bandgap along the channel in different SiGe MOSFETs.
164 SiGe MOSFET Id vs Vg Curves
1.60E-03
1.40E-03
1.20E-03
Ge Dose:0 1.00E-03 Ge Dose:7E16/cm2
(A) 8.00E-04 Ge Dose:1.05E17/cm2 Id
Ge Dose:1.4E17/cm2 6.00E-04 Ge Dose:1.75E17/cm2
4.00E-04 De Dose 2.05E17/cm2
Ge Dose:2.45E17/cm2 2.00E-04 Ge Dose:2.8E17/cm2 0.00E+00 00.511.522.533.54 Vg(V)
Figure 4.25 SiGe MOSFET Id vs Vg curves with Vd=0.1V.
Table 4.6 Threshold voltage as a Function of Channel Germanium Implant Dose
DOE
Experiment No. 1 2 3 4 5 6 7
Channel Ge 7E16 1.05E17 1.4E17 1.75E17 2.05E17 2.45E17 2.8E17
Implant
2 Dose (#/ cm )
Vt(v) 0.5527 0.5207 0.4971 0.4645 0.4318 0.4091 0.3848
Figure 4.26 shows the downward trend of the SiGe MOSFETs’ threshold
voltages with increasing Ge dose. In particular, it shows the threshold voltage
does not change too much when we change the Ge dose from 7 ×1016 cm2 to
165 3.1×1017 cm2 , so we need not adjust the threshold voltages for the characteristic comparison among them.
Vt vs Germanium Implant Dose
0.9
0.8
0.7
0.6
0.5 t(v)
V 0.4
0.3
0.2
0.1
0 0 5E+16 1E+17 1.5E+17 2E+17 2.5E+17 3E+17 Germanium implant dose (#/cm2),(BF2 implant dose=3.5E15/cm2)
Figure 4.26 SiGe threshold voltage vs Ge implant dose.
The transconductance also changes with the Ge mole fraction, so we investigated the transconductance in both the linear and saturation regions.
Figure 4.27 (a) +(b) are the channel transconductances in the SiGe transistors for various Ge dose when Vd=0.1v and 2.5v,respectively. Because the mobility enhancement in the SiGe MOSFET channels, the transconductance increases with the Ge mole fraction.
166 SiGe MOSFET Transconductances vs Vg (Vd=0.1v)
7.00E-04
6.00E-04
m) 5.00E-04 m
/ Ge Dose:0 s ( Ge Dose:7E16/cm2 ce 4.00E-04 an
t Ge Dose:1.05E17/cm2 c u
d 3.00E-04 Ge Dose:1.4E17/cm2 n o
c Ge Dose:1.75E17/cm2 s 2.00E-04 Ge Dose:2.05E17/cm2 Tran Ge Dose:2.45E17/cm2 1.00E-04 Ge Dose:2.8E17/cm2
0.00E+00 0 0.5 1 1.5 2 2.5 3 3.5 4 Vg(v)
(a)
SiGe MOSFET Transconductances vs Vg (Vd=2.5v)
1.60E-02
1.40E-02
1.20E-02
Ge Dose:0 1.00E-02
ce(s/mm) Ge Dose:7E16/cm2
8.00E-03 Ge Dose:1.05E17/cm2 uctan
Ge Dose:1.4E17/cm2 ond 6.00E-03
Ge Dose:1.75E17/cm2 ansc
r 4.00E-03 T Ge Dose:2.05E17/cm2
2.00E-03 Ge Dose:2.45E17/cm2
0.00E+00 00.511.522.533.54 Vg(v)
(b)
Figure 4.27 Transconductance variation with Ge dose for the SiGe MOSFETs when Vd = 0.1v (a) and 2.5v (b).
167
Figure 4.28 shows the relationship of SiGe MOSFET’s peak transconductance in the saturation region with the Ge dose. The peak transconductance increases almost linearly with Ge implant dose. The trend can be understood from the fact that the transconductance is enhanced by the content of Ge. But this kind of enhancement is not as significant as in the linear region, because the transconductance is surface-roughness-scattering limited under high transverse electric field.
SiGe MOSFET Peak gm in saturation region vs Ge implant dose
0.015
0.014
0.013 ) m m
s/ 0.012 (m
e c
n 0.011 a uct
nd 0.01 sco n a 0.009 ak tr e P 0.008
0.007
0.006 0 5E+16 1E+17 1.5E+17 2E+17 2.5E+17 3E+17 Ge implant dose (#/cm2)
Figure 4.28 SiGe MOSFET peak transconductance in saturation region vs Ge implant dose.
168 The subthreshold characteristics for SiGe MOSFETs with different Ge
dopant levels are shown in Figure 4.29. We can observe the good on-off
characteristics of the devices. The subthreshold performance of transistors gets
better as the Ge dose increase. At the same time; we found the leakage current
increases with Ge dose too.
SiGe MOSFET logId vs Vg Curves
1.00E+00 00.511.522.533.54 1.00E-01
1.00E-02
1.00E-03
1.00E-04
1.00E-05 Ge Dose:0 1.00E-06
) Ge Dose:7E16/cm2 1.00E-07 d(A 1.00E-08 Ge Dose:1.05E17/cm2 LogI 1.00E-09 Ge Dose:1.4E17/cm2
1.00E-10 Ge Dose:1.75E17/cm2 1.00E-11 De Dose 2.05E17/cm2 1.00E-12 Ge Dose:2.45E17/cm2 1.00E-13
1.00E-14 Ge Dose:2.8E17/cm2
1.00E-15 Vg(V)
Figure 4.29 Subthreshold characteristic of SiGe MOSFET with different Ge implant.
We can observe the effect of the Ge content on the subthreshold characteristics of the SiGe MOSFETs quantitatively in Table 4.7. The subthreshold slopes are between 75 to 90mv/dec. The realationship of the subthreshold slope and Ge implant dose is shown in Figure 4.30. The
169 subthreshold slop almost linear increases with the decrease of the Ge implant
dose.
Table 4.7 Subthreshold Slope of SiGe MOSFET with Different Ge Implant Dose
Experiment No. 1 2 3 4 5 6 7
Channel Ge 0 7E16 1.05E17 1.4E17 1.75E17 2.05E17 2.45E17 2.8E17
Implant
2 Dose (#/ cm )
Subthreshold slop 89.76 86.73 85.51 83.4 82.01 78.90 77.27 76.64
(mv/dec)
SiGe MOSFET Subthreshold slop vs implanted Ge dose
92
90
88
86 dec) v/ m 84 d slop ( 82 eshol
80 ubthr S
78
76
74 0 5E+16 1E+17 1.5E+17 2E+17 2.5E+17 3E+17 Ge implant dose(#/cm2)
Figure 4.30 SiGe MOSFET subthreshold slope vs Ge dose.
170 Similarly, the RF performances of these transistors were also examined.
We show the cutoff frequency variation with Vg relationship in Figure 4.31;
Table 4.8 gives the peak cutoff frequency for different Ge implant doses. The trend line of peak cutoff frequency is illustrated in Figure 4.32. The SiGe
MOSFET peak cutoff frequency goes up and then saturates with increasing Ge dose. The reason is that when the channel is with doped with too much Ge, there is scattering limited mobility that is reduced where the alloy scattering will degrade the transistor mobility.
SiGe MOSFET Cutoff frequency vs Vg
52 Ge=1.05E17
Ge=1.4E17 50 Ge=1.75
Ge=2.05E17
) 48 z
H Ge=2.45E17 G ( y
nc Ge=2.8E17 46 equ fr ff to u
C 44
42
40 11.21.41.61.822.22.42.62.83 Vg(V)
Figure 4.31 fT vs VG for SiGe MOSFET with different Ge dose with Vd=2.5V.
171 Table 4.8 Peak Cutoff Frequencies of SiGe MOSFETs for Various Ge Implant doses
Experiment No. 1 2 3 4 5 6 7
Channel Ge Implant 7E16 1.05E17 1.4E17 1.75E17 2.05E17 2.45E17 2.8E17
2 Dose (#/ cm )
Ftmax (GHz) 48.42 49.93 49.97 50.21 50.74 50.68 50.59
Ftmax vs Germanium Implant Dose
52
51
50
49 z)
48
Ftmax(GH 47
46
45
44 0 5E+16 1E+17 1.5E+17 2E+17 2.5E+17 3E+17 Germanium implant dose (#/cm2);BF2 implant dose=3.5E15/cm2)
Figure 4.32 SiGe MOSFET peak cutoff frequency vs Ge dose for fixed implant energy of 200KeV and fixed Boron implant of 55KeV and dose of 3.5×1015 cm2 .
4.3 Channel Length Scaling of SiGe MOSFET
For the semiconductor industry, scaling is the driver of VLSI CMOS technology. The MOSFET’s structure, such as its channel length, device width,
172 oxide thickness and channel doping, decide its behavior. Shorter gate lengths
result in a higher transconductance; similarly a smaller gate thickness results in a
higher transconductance .Traditionally, there are two kinds of scaling: constant-
voltage scaling and constant-field scaling [4]. But these principles for planar
MOSFET are not fit for the vertical MOSFET since the channel doping
distribution of vertical MOSFET is very different from that of planar MOSFET. In
this study, the gate oxide thickness is set at 4nm. If we continue to decrease it,
the possibility exists of direct tunneling that can be too large. So we only examine
a decrease in the channel length and adjust the channel doping to keep an
appropriate threshold voltage of about 0.5v. In this section, we describe the
results when the process simulator DIOS was used to simulate the fabrication of
four transistors with different channel lengths. We change the fabrication
conditions of the mesa etch from etching 250nm to 220nm, 200nm, and 180nm.
Our corresponding goals for the channel length are 0.12 µm , 0.10 µm and
0.08 µm , respectively. After the process simulations, the profiles of the channels
are observed and the metallurgical channel lengths can be measured by ISE
Tecplot. We can compare the process simulation results of the three transistors
with the process simulation result of the SiGe MOSFET with 250nm mesa, which
was discussed in the last section, and observe the difference of mesa height
from the scales in Figure 4.33. The heights of the mesas are 0.26 µm , 0.23 µm ,
0.21 µm and 0.19 µm , which are a little bit larger than we expect, but acceptable.
173
Mesa height 250nm Mesa height 220nm
Mesa height 200nm Mesa height 180nm
Figure 4.33 Channel profiles of SiGe MOSFETs with different channel lengths.
In this study, the channel doping is not uniform; the region near to the source of the transistor has the higher Boron, Arsenic and Germanium concentrations. When the channel length is decreased, the threshold voltage will shift because the BF2 concentration between two gate oxide layers will increase severely, which will result in the increase of threshold voltage. We then have to adjust the channel BF2 implant dose to get reasonable threshold voltages close to 0.5V, similar to what we have done in the last section. We did a series of DOE simulation runs of BF2 implants to find a threshold voltage for the transistors in a
174 reasonable range. Figure 4.34 shows the relationship of Id and Vg, from which we get the threshold voltages for the transistors. Table 4.9 shows the channel
BF2 implant dose and corresponding threshold voltages for the SiGe MOSFETs with the different channel lengths.
SiGe MOSFET with different channel length Id vs Vg
1.40E-03
1.20E-03
1.00E-03
8.00E-04 L=0.09um (A) d I 6.00E-04 L=0.11um
L=0.15um
4.00E-04 L=0.06um
2.00E-04
0.00E+00 00.511.522.533.54 Vg(V)
Figure 4.34 Id vs Vg curves of SiGe MOSFET with different channel length.
175 Table 4.9 Channel BF2 Doping and Threshold Voltages for Different Channel
Length SiGe MOSFETs.
Experiment No. 1 2 3 4
Goal Channel length 0.15 0.12 0.10 0.08
( µm )
Channel BF2 Implant 3.5E15 1.3E15 4E14 2E14
Dose(#/ cm2 )
Threshold Voltage(v) 0.553 0.494 0.455 0.352
Figure 4.35 is the linear transconductance comparison of the SiGe
MOSFETs with different channel lengths. We can observe the peak
transconductance decreases when the channel length decreases. The mobility in
the channel is degraded when the channel is shorter due to the higher doping
(B+Ge) although the dose is reduced. The peak transconductance of the device
with 0.08um channel is only 50% of that of the device with 0.15um.
176 SiGe MOSFET with different channel length Transconductance vs Vg
9.00E-04
8.00E-04
7.00E-04
6.00E-04 /mm) s e ( c 5.00E-04 L=0.10um L=0.12um 4.00E-04 nductan L=0.15um
sco L=0.08um n
a 3.00E-04 Tr
2.00E-04
1.00E-04
0.00E+00 0 0.5 1 1.5 2 2.5 3 3.5 4 Vg(V)
Figure 4.35 Gm vs Vg of SiGe with different channel length.
In this process simulation study where we varied the BF2 dose, although we changed the channel mesa height; that does not mean the channel length is simply decrease is equal to that of mesa decrease. Fortunately, ISE Tecplot can help us observe the dopant profiles of the transistors and determine the actual channel length. We draw a cut line 3nm under gate oxide and get the precise channel lengths by measuring the distance of source PN junction and drain PN junction, which is illustrated in Figure 4.36 for all of the four devices.
177 Ge mole fraction,Boron and Arsenic Concentration Distribution Along Channel 1E+22 8%
1E+21 Si B 7%
1E+20 Si As 6% 1E+19 SiGe Ge Frac 5% Ge 1E+18
Mo tion l 1E+17 4% e cm3) Source Channel Drain (#/ 1E+16 3%
1E+15 2% 1E+14
1% 1E+13
1E+12 0% 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22 0.24 0.26 0.28 0.3 Y Direction distance (um)
(a)
Ge mole fraction ,Boron and Arsenic Concentration distribution along Channel 1.00E+22 0.12
1.00E+21 0.1 1.00E+20
1.00E+19 0.08 1.00E+18
1.00E+17 0.06 /cm3)
(# Boron 1.00E+16 Arsenic Ge 0.04 1.00E+15
1.00E+14 Source Channel Drain 0.02 1.00E+13
1.00E+12 0 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22 0.24 0.26 0.28 0.3 Y Direction distance (um)
178 (b)
Ge mole fraction,Boron and Arsenic Concentration distribution along channel 1.00E+22 0.16
1.00E+21 0.14
1.00E+20 0.12 1.00E+19
0.1 1.00E+18 Boron ) 3 m
c 1.00E+17 0.08 Arsenic (#/ 1.00E+16 Ge 0.06
1.00E+15 Source Channel Drain 0.04 1.00E+14
0.02 1.00E+13
1.00E+12 0 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22 0.24 0.26 0.28 0.3 Y Direction distance (um)
(c)
179 Ge mole fraction, Boron and Arsenic Concentration distribution along
1.00E+22 Channel 0.16
1.00E+21 0.14
1.00E+20 0.12 1.00E+19
0.1 1.00E+18
1.00E+17 0.08
/cm3) Boron (# 1.00E+16 Source Channel Drain 0.06 Arsenic 1.00E+15 0.04 1.00E+14 Ge 0.02 1.00E+13
1.00E+12 0 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22 0.24 0.26 0.28 0.3 Y Direction distance (um)
(d)
Figure 4.36 Dopant profiles for 0.15 µm (a), 0.12 µm (b), 0.10 µm (c) and 0.08 µm
(d) SiGe MOSFETs.
From figures above, we get the precise channel lengths of the three SiGe
MOSFETs which is given in Table 4.10.
Table 4.10 Target and Measured Channel Lengths of SiGe MOSFETs
Experiment No. 1 2 3 4
Channel length goals 0.15 0.12 0.10 0.08
Measured Channel 0.15 0.11 0.09 0.06 length( µm )
180
For the very short channel MOSFETs, we are very concerned about the
short channel effect. All of the threshold voltages in Table 4.5 are measured
when Vd is 0.1v. When Vd increases to 2v, for the transistor with 0.15 µm and
0.11 µm channel length, they still keep good subthreshold characteristics, but the
transistors with 0.09 µm channel and 0.06 µm channel length show very severe short channel effect as seen in Figure 4.37. The figure alos shows the leakage currents of the two shorted channel transistors are over 1×10−4 A (extremely high)
when the bias of drain is 2v, which is the supply voltage of deep submicron
MOSFET,
SiGe MOSFETs Subthrshold Performances
1
0.1
0.01
0.001
0.0001 L=0.05um 1E-05 ) A (
Ig 1E-06 L=0.09um
1E-07 L=0.11um
1E-08 L=0.15um 1E-09
1E-10
1E-11 00.511.522.533.54 Vg(V)
Figure 4.37 Log Id vs. Vg for SiGe MOSFETs with different channel lengths when
Vd is 2v.
181
We tried to measure the DIBL of the SiGe MOSFETs with four different
channel lengths from 0.15 µm , 0.11 µm , 0.09 µm and 0.06 µm when Vd is 0.1v and 1.1v. Table 4.11 shows that when the channel length is more than 0.11 µm ,
the transistor can work well, the short channel effect is suppressed and the DIBL
is small. When the channel is less than 0.11 µm , the transistor shows serious
short channel effects as known in Figure 4.34. We cannot get the DIBL for the
0.09 µm and 0.06 µm channel length SiGe MOSFETs because when the Vd is
1.1v, the device simulator warns the leak current of the transistors is too large, so the device simulator cannot measure the threshold voltage or subthreshold slope for them.
Table 4.11 Comparison of DIBL for SiGe MOSFETs with Different Channel
Lengths when Vd=0.1V and Vd=1.1V.
Experiment No. 1 2 3 4
Channel length 0.15 0.11 0.09 0.06
DIBL(mv/V) 48.63 71.32 No output No output
Subsequently, reduced Vd to 0.5V and measure the DIBL used the Id vs
Vg curves when Vd is 0.1 and 0.5V. The 0.15 µm and 0.11 µm channel length
transistors’ performances are again very good and the DIBL for 0.09 µm and 0.06
µm were obtained but found to be much larger as shon in table 4.12.
182 Table 4.12 Comparison of DIBL for SiGe MOSFETs with Different Channel
Lengths when Vd=0.1V and Vd=0.5V.
Experiment No. 1 2 3 4
Channel length 0.15 0.11 0.09 0.06
DIBL(mv/V) 45.3 68.4 208 433
For planar MOSFET, usually, the device speed scales up as the gate
length is reduced. But for the vertical MOSFET, we find things are different. The
RF performances of these different channel length transistors were measured.
The peak cutoff frequency from the RF simulation results are shown in Table
4.132. For the shortest channel length device, no FT could be obtained.
Table 4.13 SiGe MOSFET Peak fT for Vd= 2.5V with Various Channel Lengths
Experiment No. 1 2 3 4
Channel length 0.15 0.11 0.09 0.06
Peak Cutoff 48.42 34.93 24.10 N/A
frequency(GHz)
When the vertical channel SiGe MOSFET’s channel length is shortened simply shortened, the Ge implant energy and dose are not changed. But because the structure of device is changed, the Ge peak mole fraction and the location of the peak also changed, with respect to the channel is seen in Figure 4.33. But the Ge is still linearly distributed in the channel and the Ge mole fraction
183 increases. While the channel region’s Boron implant is reduced, both the As in
both source and drain diffuse into channel, the As concentration increases
dramatically. As a result, the scattering in the channel will be much worse, the
electron mobility will be degraded. The speed of the device goes down.
4.4 Summary and Conclusions
In this chapter, we have explored optimizing SiGe vertical N-channel
MOSFET structures by using variations in the process fabrication, including
investigating the effects of varying with channel doping, gate oxide and channel
scaling in the device structure. We have examined and compared the
performance of various device structures by using process and device modeling
and compared our simulation results with the transistors in chapter 3.
After changing the gate oxide from 10nm to 4nm and adjusting the
threshold voltage to a reasonable voltage of about 0.5V, the transistor showed
good both DC and AC performances when the channel was larger than 0.11 µm .
The peak cutoff frequency reached 50.75GHz when the Germanium implant
dose was 2.05E17/ cm2 . But when the channel length was less than 0.11 µm , we observed severe short channel effects and a low cutoff frequency happened.
That means we need to do more optimization fabrication process if we continue to scale down the channel length below about 0.10. In general, the optimized strained SiGe vertical channel MOSFET appear promising and a possible alternative for the conventional planar MOSFET when the channel length is over about 0.10 µm .
184 Bibliography
[1] Taur and T. Ning, “Fundamentals of Modern VLSI Devices,” Chapter 4,
pp168 Cambridge University Press, Cambridge, UK, 1998.
[2] S.M. Sze, “Physics of Semiconductor Devices,” Chapter 2, Wiley-
Interscience Publication, New York, USA, 1981.
[3] Kanaan Kano, “Semiconductor Devices,” Chapter 13, Prentice Hall
International, NJ, USA, 1998.
[4] Taur and T. Ning, “Fundamentals of Modern VLSI Devices,” Chapter 4,
pp164 Cambridge University Press, Cambridge, UK, 1998.
185 Chapter 5
Conclusions and Future Work
5.1 Generalized Conclusions
In this study, we have investigated the formation and characteristics of the
strained SiGe vertical channel MOSFET and a Si control vertical MOSFET.
Transistors were virtually fabricated with a channel length below 0.15 µm without sophisticated lithography with the whole process compatible with a regular
CMOS process. Our work has sought to understand and compare the performance of strained SiGe vertical channel MOSFET and Si control vertical channel MOSFET. We observed the advantages and disadvantages of the vertical SiGe MOSFET. The study examined not only the transistor DC performance but also the RF performance of devices. We did multiple optimizations for vertical transistors by changing the channel doping, gate oxide thickness and Ge mole fraction in channel, and investigated scaling down of the channel length.
The results were obtained by using a commercial numerical device simulator by ISE. Qualitatively good agreement in results was obtained in comparison to the previous experiment results of Chen et al. [1][2]. Discrepancy as observed can be attributed in part to the various assumptions in the materials parameters and device physics incorporated in the modeling software. Overall,
186 numerical device modeling provides a useful tool for understanding and
predicting the characteristics of the strained SiGe vertical channel MOSFET.
5.2 Future Work
In this study, because we want to use standard CMOS fabrication process
to construct the devices, no novel advanced technology was included. We found
the transistors had significant short-channel effects when the channel length of
SiGe MOSFET is scaled to less than 0.11 µm . The primary reason is that the source and drain As profiles extend excessively into the channel and degrade the mobility, perhaps more complicated fabrication technology can be used in future to scale the devices to several tens nanometer. For example, perhaps we can use epi technology to grow and dope the channel layer on the silicon substrate to get a higher quality strained SiGe layer. Also the dielectric pocket source or drain structure in vertical MOSFET like in Figure 5.1 can suppress the punch trough effect[3].
Figure 5.1 Concept of the dielectric pocket vertical MOSFET [3]
187 More work on the simulation can help us understand the transistors more precisely. When the transistor dimension becomes less than 100nm, we need to use more sophisticated models like Monte Carlo simulation to observe the characters of transistors.
188 Bibliography
[1] C.Xiangdong, “Hole and Electron mobility enhancement in strained SiGe
Vertical MOSFETs,” IEEE Transactions on Electron Devices, vol. 48, pp.
1975-1980, 2001.
[2] C.Xiangdong, “Electron mobility enhancement in strained SiGe vertical n-
type metal-oxide-semiconductor filed-effect transistors,” Applied Physics
Leters, vol. 78, N.3, 15 January, 1974.
[3] D. Donaghy, S. Hall, C. H. de Groot, V. D. Kunz, and P. Ashburn, “Design
of 50-nm Vertical MOSFET Incorporating a Dielectric Pocket,” IEEE
Transactions on Electron Devices, vol. 51, no.1,pp158-161, January 2004.
189