Land Grid Array (LGA) Package Rework
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Printed Circuit Board Rework and Repair Equipment from the Rework Company Welcome…
Lead-Free Rework printed circuit board rework and repair equipment from the rework company Welcome… ....to the APE Rework Equipment Catalog. Many changes are taking place in our industry with the influence of RoHs regulations and the acceptance of Lead-Free materials in equipment manufacture. There are few exceptions and gener- ally this requirement regulates the international electronics community. Lead-Free materials require more stringent con- trols during production. A higher degree of manufacturing complications will result in a greater demand for quality rework. To address these demands we have introduced several models of Vision/Reflow machines to meet every budget while maintaining the rigorous requirements for Lead-Free manufacture. We are confident that we can provide a solu- tion for your application and look forward to providing a personal service in caring for your rework needs. Bill Scheu.......President and CEO International Service and Support: A.P.E. USA Headquarters A.P.E. USA Headquarters Kaisertech 2 North Blackwater Lane 2 North Blackwater Lane Unit 12, M3 Trade Park Key Largo, FL 33037 Key Largo, FL 33037 Manor Way, Eastleigh, Tel: 305-451-4722 Tel: 305-451-4722 Hampshire England, SO50 9YA Fax: 305-451-3374 Fax: 305-451-3374 Tel: 44-(0)23 8065 0065 USA E-mail: [email protected] Canada E-mail: [email protected] UK Fax: 44-(0)23 8065 0060 E-mail: [email protected] Motorola Yip In Tsoi & Jacks, Ltd. American Tec Co Ltd Radio Products Service Division 523 Mahaprutharam Road Flat A 1st Floor, Block 1 1313 E. Algonquin Road Bangrak, Bangkok Cyber-Tech Zone, Gaoxin Ave 7 South Shaumburg, IL 60196-1081 Thailand 10500 Nansham District, Shenzhen 518057 Tel: 800-442-4210 Tel: 662-353-8667 Tel: 86-7556-135-0555 Radio Products Fax: 800-622-6210 Maylasia Fax: 665-353-8686 China Fax: 86-7556-135-0531 Service Division www.yipjacks.com E-mail: [email protected] Primetec Pte Ltd 3S Electronics & Automation KTI 4012 Ang Mo Kio Avenue 10 Technologies Ltd. -
FC-PBGA, Flip Chip Plastic Ball Grid Array
TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. Table of Contents Slide 1. FC-PBGA Package Configurations 3 2. Printed Circuit Board Design for FC-PBGA 11 3. Surface Mount Assembly 16 4. Component Level Qualification 29 5. Board-Level Reliability 31 6. Thermal Performance 38 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a TM 2 Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. TM FC-PBGA Package Configurations Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. -
Manufacturing and Reliability Challenges with QFN
Manufacturing and Reliability Challenges With QFN Dr. Craig Hillman and Cheryl Tulkoff DfR Solutions SMTA DC Chapter Ashburn, VA February 25, 2009 QFN as a ‘Next Generation’ Technology What is ‘Next Generation’ Technology? Materials or designs currently being used, but not widely adopted (especially among hi-rel manufacturers) Carbon nanotubes are not ‘Next Generation’ Not used in electronic applications Ball grid array is not ‘Next Generation’ Widely adopted © 2004 - 2007 2 Introduction (cont.) Why is knowing about ‘Next Generation’ Technologies important? These are the technologies that you or your supply chain will use to improve your product Cheaper, Faster, Stronger, ‘Environmentally-Friendly’, etc. And sooner then you think! © 2004 - 2007 3 Reliability and Next Gen Technologies One of the most common drivers for failure is inappropriate adoption of new technologies The path from consumer (high volume, short lifetime) to high rel is not always clear Obtaining relevant information can be difficult Information is often segmented Focus on opportunity, not risks Can be especially true for component packaging BGA, flip chip, QFN © 2004 - 2007 4 Component Packaging Most of us have little influence over component packaging Most devices offer only one or two packaging styles Why should you care? Poor understanding of component qualification procedures Who tests what and why? © 2004 - 2007 5 Component Testing Reliability testing performed by component manufacturers is driven by JEDEC JESD22 series (A & B) Focus is -
(SOIC) Package
Freescale Semiconductor, Inc. Document Number: AN2409 Application Note Rev. 3.0, 10/2014 Small Outline Integrated Circuit (SOIC) Package 1 Introduction Contents 1 Introduction. .1 This application note provides guidelines for handling and assembly of Freescale Small Outline Integrated Circuit (SOIC) 2 Scope . .1 package during Printed Circuit Board (PCB) assembly. 3 Small Outline Integrated Circuit . .2 Guidelines for PCB design, rework, and package performance 4 Printed Circuit Board Guidelines . .4 information such as Moisture Sensitivity Level (MSL) rating, board level reliability, mechanical and thermal resistance data are 5 Board Assembly . .10 included for reference. 6 Repair and Rework Procedure . .14 7 Board Level Reliability . .16 2 Scope 8 Thermal Characteristics . .18 9 Case Outline Drawing, MCDS and MSL Rating 20 This document contains generic information that encompasses various Freescale SOIC packages assembled internally or at 10 Package Handling . .21 external subcontractors. Specific information about each device is 11 References . .26 not provided. To develop a specific solution, actual experience and development efforts are required to optimize the assembly process 12 Revision History . .27 and application design per individual device requirements, industry standards (such as IPC and JEDEC), and prevalent practices in the assembly environment. For more details about the specific devices contained in this note, visit www.freescale.com or contact the appropriate product application team. © Freescale Semiconductor, Inc., 2014. All rights reserved. Small Outline Integrated Circuit 3 Small Outline Integrated Circuit Figure 1 shows the standard SOIC offerings through Freescale. The exposed pad (denoted as -EP) version is also displayed. Figure 1. Standard Freescale SOIC Offerings 3.1 Package Description The SOIC is a surface mount integrated circuit package. -
Recommendations for Board Assembly of Infineon Ball Grid Array Packages
Recommendations for Board Assembly of Infineon Ball Grid Array Packages Additional Information Please read the Important Notice and Warnings at the end of this document Revision 4.0 www.infineon.com page 1 of 18 2020-11-09 Recommendations for Board Assembly of Infineon Ball Grid Array Packages Table of Contents Table of Contents Table of Contents ........................................................................................................................... 2 Acronyms and Abbreveations ........................................................................................................... 3 1 Package Description ............................................................................................................... 4 1.1 BGA Package Type ................................................................................................................................... 4 1.3 Package Features and General Handling Guidelines ............................................................................. 5 2 Printed Circuit Board .............................................................................................................. 7 2.1 Routing .................................................................................................................................................... 7 2.2 Pad Design ............................................................................................................................................... 7 3 PCB Assembly ....................................................................................................................... -
PDF Package Information
This version: Apr. 2001 Previous version: Jun. 1997 PACKAGE INFORMATION 1. PACKAGE CLASSIFICATIONS This document is Chapter 1 of the package information document consisting of 8 chapters in total. PACKAGE INFORMATION 1. PACKAGE CLASSIFICATIONS 1. PACKAGE CLASSIFICATIONS 1.1 Packaging Trends In recent years, marked advances have been made in the electronics field. One such advance has been the progression from vacuum tubes to transistors and finally, to ICs. ICs themselves have been more highly integrated into LSIs, VLSIs, and now, ULSIs. With increased functions and pin counts, IC packages have had to change significantly in the last few years in order to keep-up with the advancement in semiconductor development. Functions required for conventional IC packages are as follows: 1) To protect IC chips from the external environment 2) To facilitate the packaging and handling of IC chips 3) To dissipate heat generated by IC chips 4) To protect the electrical characteristics of the IC Standard dual-in-line packages (DIP), which fulfill these basic requirements, have enjoyed wide usage in the electronics industry for a number of years. With increasing integration and higher speed ICs, and with the miniaturization of electronic equipment, newer packages have been requested by the industry which incorporate the functions listed below: 1) Multi-pin I/O 2) Ultra-miniature packages 3) Packages suited to high density ICs 4) Improved heat resistance for use with reflow soldering techniques 5) High throughput speed 6) Improved heat dissipation 7) Lower cost per pin In response to these requests, OKI has developed a diversified family of packages to meet the myriad requirements of today’s burgeoning electronics industry. -
Quad Flat No-Lead (QFN) Evauation Test
National Aeronautics and Space Administration Quad Flat No-Lead (QFN) Evaluation Testing Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California Jet Propulsion Laboratory California Institute of Technology Pasadena, California 6/17 National Aeronautics and Space Administration Quad Flat No-Lead (QFN) Evaluation Testing NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Success Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California NASA WBS: 724297.40.43 JPL Project Number: 104593 Task Number: 40.49.02.35 Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena, CA 91109 http://nepp.nasa.gov 6/17 This research was carried out at the Jet Propulsion Laboratory, California Institute of Technology, and was sponsored by the National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not constitute or imply its endorsement by the United States Government or the Jet Propulsion Laboratory, California Institute of Technology. Copyright 2017. California Institute of Technology. Government sponsorship acknowledged. Acknowledgments The author would like to acknowledge many people from industry and the Jet Propulsion Laboratory (JPL) who were critical to the progress of this activity including the Rochester Institute of Technology (RIT). The author extends his appreciation to program managers of the National Aeronautics and Space -
Classification of Semiconductor Package
www.connect.co.jp www.jccherry.com Technical Data Classification of semiconductor package SIP ZIP Single In-line Package Zigzag In-line Package A package having leads on a single side of the body. A package having Zig-zag formed leads on a single side of the body. DIP PGA Dual In-line Package Pin Grid Array A package having leads in parallel rows A package having pins on top or bottom on two opposite sides of the body for face in a matrix layout of at least three through-hole insertion. rows and three columns. SDIP Shrink DIP A package which reduced the lead pitch of DIP. SOP SON Small Outline Package Small Outline Non-leaded Package A package having gull-wing-shaped leads A package having single-inline terminal on two opposite sides of the body. pads along two opposite edges of the bottom face. The terminal pads may or may not be exposed on the package sides. TSOP Thin SOP SOJ A package height of SOP exceeds 1.0 mm, Small Outline J-leaded Package and 1.2 mm or less. A package having J-shaped leads on two opposite sides of the body. SSOP Shrink SOP A package which reduced the lead pitch of SOP. 50-01 www.connect.co.jp www.jccherry.com Classification of semiconductor package QFP LGA Quad Flat Package Land Grid Array A package having gull-wing-shaped leads A package having lands on top or bottom on four sides of the body. face in a matrix of at least three rows and three columns. -
Building Your Prototype
Building Your Prototype Prototype Construction Techniques Part Numbers Package Types Specification Sheets Schematic Diagrams Practical Advice T. Grotjohn, [email protected] Prototype Construction Techniques 1) Protoboard Use DIP components Keep your wires neat and color coded Prone to bad connections Maximum operating speed: ~ few MHz 2) Wire Wrap Often done using wire wrap sockets on a vector board Use DIP components Wire used is good for digital signals Be careful with high current lines because the wire is small. Typical wire: 30 gauge 0.34 Ω/m 28 gauge 0.21 Ω/m 3) Soldered Board Single solder points board Tied solder points board (Your mini project #1) PCB: printed circuit board PCB can be made for ECE 480 projects in the ECE Shop: See the shop’s web page. (Also see the next page) . Printed Circuit Board System General Information T-Tech Protyping Machine ECE 482 Student Project Design Department of Electrical and Computer Engineering, 1999 Michigan State University, East Lansing, Michigan, USA Part Numbers Typical Part Number: DM8095N Prefix: Indicates the manufacture of the part. See two pages in Attachment 1. Suffixes: Indicates temperature range: “military”, “industrial”, “commercial” Also the suffixes are used to indicate package types. The ECE shop deals most often with the following electronic part suppliers. Allied Electronics (www.alliedelec.com) Digi Key (www.digikey.com) Newark Electronics (www.newark.com) For other (non-electronic) supplies, suppliers often used are Grainger (www.grainger.com) McMaster Carr (www.mcmaster.com) Package Types DIP: Dual Inline Package Easiest to use. Works in protoboards, solder boards, wire wrapping, easiest to solder components to PCB This is your choice for ECE 480. -
NSQF-Test and Repair Technician- IT
Revision made by NSDA_25 May 2015 QUALIFICATION FILE – CONTACT DETAILS OF SUBMITTING BODY Name and address of submitting body: Electronics Sector Skills Council of India, 422, Okhla Industrial Estate, Phase – III, New Delhi - 110020 Name and contact details of individual dealing with the submission Name: Rakesh Mathur Position in the organisation: Senior Vice President Address if different from above: Same as above. Tel number(s) T: +91-11-46035050 M: +91-9810 285 345 e-mail address: [email protected] List of documents submitted in support of the Qualifications File 1. Qualification Pack for Test and Repair Technician IT Hardware 2. Occupation Map for the selected job roles in the Sub-sector 3. RFP for development of National Occupational Standards 4. Composition of NOS Subcommittee 5. Mapping of Manpower skills in IT Hardware and Electronics Industry – MAIT (2009) http://www.essc-india.org/Essc/reports/MAIT0Report2008_15711.pdf 6. Approval of QP/ NOSs a) Minutes of the GC meeting 7. ESSCI IMaCS LMIS Report 8. List of Companies and industry associations which participated in the development of these qualifications packs 9. Procedure for Assessment of Assessing Bodies and Assessors 1 QUALIFICATION FILE SUMMARY Qualification Title Test and Repair Technician- IT Hardware Classification code ELE/Q4602 Body/bodies which will assess Electronics Sector Skills Council of India candidates Body/bodies which will award the Electronics Sector Skills Council of India certificate for the qualification. Body which will accredit providers Electronics Sector Skills Council of India to offer the qualification. Test Repair Technician: Occupation(s) to which the qualification gives access Also called ‘IT Repair Technician’, or ‘Hardware Technician’, the Test Repair Technician diagnoses and performs rework and repairs on the faulty module in the hardware. -
Design for Flip-Chip and Chip-Size Package Technology
As originally published in the IPC APEX EXPO Proceedings. Design for Flip-Chip and Chip-Size Package Technology Vern Solberg Solberg Technology Consulting Madison, Wisconsin Abstract As new generations of electronic products emerge they often surpass the capability of existing packaging and interconnection technology and the infrastructure needed to support newer technologies. This movement is occurring at all levels: at the IC, at the IC package, at the module, at the hybrid, the PC board which ties all the systems together. Interconnection density and methodology becomes the measure of successfully managing performance. The gap between printed boards and semiconductor technology (wafer level integration) is greater than one order of magnitude in interconnection density capability, although the development of fine-pitch substrates and assembly technology has narrowed the gap somewhat. All viable efforts are being used in filling this void utilizing uncased integrated circuits (flip-chip) and incorporating more than one die or more than one part in the assembly process. This paper provides a comparison of different commonly used technologies including flip-chip, chip-size and wafer level array package methodologies detailed in a new publication, IPC-7094. It considers the effect of bare die or die-size components in an uncased or minimally cased format, the impact on current component characteristics and reviews the appropriate PCB design guidelines to ensure efficient assembly processing. The focus of the IPC document is to provide useful and practical information to those who are considering the adoption of bare die or die size array components. Introduction The flip-chip process was originally established for applications requiring aggressive miniaturization. -
Implementation and Solder Reflow Guidelines for Pb-Free Packages XAPP427 (V2.7) December 20, 2017 Author: Amjad Esfahani
Application Note: Packaging Implementation and Solder Reflow Guidelines for Pb-Free Packages XAPP427 (v2.7) December 20, 2017 Author: Amjad Esfahani Summary Recent legislative directives and corporate driven initiatives around the world have called for the elimination of Pb and other hazardous substances in electronics used in many sectors of the electronics industry. The Pb-free program at Xilinx was established in 1999 as a proactive effort to develop and qualify suitable material sets and processes for Pb-free applications. Xilinx has taken the leadership position by quickly forming partnerships with our customers and suppliers, and by participating in industry consortiums to provide technical solutions that are aligned with industry requirements. Xilinx has researched alternatives to Pb compounds and has selected matte Sn lead finish for lead-frame packages and SnAgCu solder balls for BGA packages. In addition, suitable material sets have been chosen and qualified for higher reflow temperatures (240°C–260°C) that are required by Pb-free soldering processes. Pb-free products from Xilinx are designated with an additional “G” or “V” in the package designator portion of the part number. For reflow soldering applications, SnAgCu solder has been chosen by the industry as the most viable Pb-free solder to replace eutectic SnPb solder. Compared with other Pb-free alloys, SnAgCu has better characteristics in terms of cost and processability as well as comparable or better reliability than eutectic SnPb solder. However, SnAgCu alloy has a much higher melting temperature (217°C) than the standard eutectic SnPb solder. Thus, assembly processes must be optimized accordingly to achieve the best yields and reliability.