Si3N4 Deposition & the Virtual Chemical Vapor Deposition Lab
Making a transistor, the general process A closer look at chemical vapor deposition and the virtual lab Images courtesy Silicon Run Educational Video, VCVD Lab Screenshot Why Si3N4 Deposition…Making Microprocessors
http://www.sonyericsson.com/cws/products/mobilephones /overview/x1?cc=us&lc=en
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On a wafer, billions of transistors are housed on a single square chip. One malfunctioning transistor could cause a chip to short-circuit, ruining the chip. Thus, the process of creating each microscopic transistor must be very precise.
Wafer image: http://upload.wikimedia.org/wikipedia/fr/thumb/2/2b/PICT0214.JPG/300px-PICT0214.JPG What size do you think an individual transistor being made today is? Size of Transistors
One chip is made of millions or billions of transistors packed into a length and width of less than half an inch. Channel lengths in MOSFET transistors are less than a tenth of a micrometer. Human hair is approximately 100 micrometers in diameter.
Scaling of successive generations of MOSFETs into the nanoscale regime (from Intel). Transistor: MOS
We will illustrate the process sequence of creating a transistor with a Metal Oxide Semiconductor(MOS) transistor. Wafers – 12” Diameter
½” to ¾”
Source Gate Drain conductor Insulator n-Si n-Si p-Si
Image courtesy: Pro. Milo Koretsky Chemical Engineering Department at OSU IC Manufacturing Process IC Processing consists of selectively adding material (Conductor, insulator, semiconductor) to, removing it from or modifying it Wafers
Deposition / Photo/ Ion Implant / Pattern Etching / CMP
Oxidation Anneal Clean Clean Transfer
Loop
(Note that these steps are not all the steps to create a transistor. Some steps are skipped. This is purely to show the various stages in the loop to create a transistor.) Graphics copy-write Pro. Milo Koretsky Chemical Engineering Department at OSU Making a Transistor: Starting Silicon Wafer Wafers
Clean
Deposition /
Oxidation
Transfer
Pattern
Photo/ Loop
Si
Etching Etching /
CMP
Ion Ion Implant / Anneal
Graphics copy-write Pro. Milo Koretsky Chemical Engineering Department at OSU Clean substrate
Clean Deposition /
Oxidation Polished Silicon Wafer
Transfer
Pattern
Photo/
Loop
Etching Etching / CMP
Si
Ion Ion Implant / Anneal
Graphics copy-write Pro. Milo Koretsky Chemical Engineering Department at OSU Chemical Vapor Deposition: Si3N4
Clean
Process 200 Wafers at a Time
Deposition /
Oxidation
Transfer
Pattern
Photo/
Loop
Etching Etching / CMP
Si
Ion Ion Implant / Anneal
Graphics copy-write Pro. Milo Koretsky Chemical Engineering Department at OSU Spin Coating of Photoresist
Clean
Deposition / Oxidation
mask
Transfer
Pattern
Photo/
Loop
Etching Etching / CMP
Si
Ion Ion Implant / Anneal
Graphics copy-write Pro. Milo Koretsky Chemical Engineering Department at OSU Develop Photoresist
Clean
Deposition /
Oxidation
Transfer
Pattern
Photo/
Loop
Etching Etching / CMP
Si
Ion Ion Implant / Anneal
Graphics copy-write Pro. Milo Koretsky Chemical Engineering Department at OSU Plasma Etch Si3N4
Clean
Deposition /
Oxidation
Transfer
Pattern
Photo/
Loop
Etching Etching / CMP
Si
Ion Ion Implant / Anneal
Graphics copy-write Pro. Milo Koretsky Chemical Engineering Department at OSU Plasma Etch: Strip Photoresist
Clean
Deposition /
Oxidation
Transfer
Pattern
Photo/
Loop
Etching Etching / CMP
Si
Ion Ion Implant / Anneal
Graphics copy-write Pro. Milo Koretsky Chemical Engineering Department at OSU Ion Implantation
Clean
IONS IONS IONS
Deposition /
Oxidation
Transfer
Pattern
Photo/
Loop
Etching Etching / CMP Si
1.75 u
Ion Ion Implant / Anneal 1/50th of a human hair
Graphics copy-write Pro. Milo Koretsky Chemical Engineering Department at OSU Anneal
• Clean before anneal Clean
Activate (& diffuse) the dopant
Deposition / Oxidation
HEAT HEAT HEAT
Transfer
Pattern
Photo/
Loop
Etching Etching / CMP
Si
Ion Ion Implant / Anneal
Graphics copy-write Pro. Milo Koretsky Chemical Engineering Department at OSU The Final Steps…a completed transistor
Gate: +
Source - Drain: +
- - e e Si
Graphics copy-write Pro. Milo Koretsky Chemical Engineering Department at OSU Chemical Vapor Deposition A Closer Look: Si3N4
Reactions:
__SiCl2H2 (g) + __NH3 (g) Si3N4 (s) + HCl (g) + H2 (g) Dichlorosilane Ammonia Silicon Hydrogen chloride Hydrogen nitride
__HCl (g) + __NH3 (g) ___NH4 Cl(g) NH4Cl (gas) NH3 (gas) Hydrogen chloride Ammonia Ammonium chloride H2 (gas) DCS (gas)
Silicon nitride
DCS (gas)
NH3 (gas) Graphics copy-write Pro. Milo Koretsky Chemical Engineering Department at OSU Chemical Vapor Deposition A Closer Look: Si3N4 Reactions:
3 SiCl2H2 (g) + 4 NH3 (g) 1 Si3N4 (s) + 6 HCl (g) + 6 H2 (g) Dichlorosilane Ammonia Silicon Hydrogen chloride Hydrogen nitride NH4Cl (gas) NH3 (gas) H2 (gas) DCS (gas) 1 HCl (g) + 1 NH3 (g) 1 NH4 Cl(g) Hydrogen chloride Ammonia Ammonium chloride
Silicon nitride
DCS (gas)
NH3 (gas) Overall Reaction:
3 SiCl2H2 (g)+10 NH3 (g) Si3N4 (s) + 6 NH4Cl (g)+ 6 H2 (g) Dichlorosilane Ammonia Silicon Ammonium chloride Hydrogen (DCS) nitride
Graphics copy-write Pro. Milo Koretsky Chemical Engineering Department at OSU Concentration
What factors do you think affect the reaction and film growth? Temperature
Reaction/Deposition Time Virtual CVD Overview Choosing the Virtual CVD reactor parameters
Pressure is Fixed Factors that Effect Reaction and Film Growth: Concentration Absolute flow rates of PV = nRT NH3 to SiCl2H2
Ratio of NH3 to SiCl2H2 NH4Cl (gas) NH3 (gas) H2 (gas) Pressure (fixed) SiCl2H2 (gas)
SiCl2H2 (gas)
NH3 (gas)
Graphics copy-write Pro. Milo Koretsky, Chemical Engineering Department at OSU and Silicon Run Educational Video Factors that Effect Reaction and Film Growth: Temperature There are 5 First order reaction (thermal): temperature zones A B Remember
(18.12, Addison-Wesley, Chemistry) 1 k Energy B Rate = [A] Ea,f
A Ea, f k k exp 0 RT Reaction coordinate The Arrhenius Equation
Factors that Effect Reaction and Film Growth: Temperature
What can you do with the 5 temperature zones??? PV = nRT NH4Cl (gas) NH3 (gas) H2 (gas) SiCl2H2 (gas)
SiCl2H2 (gas)
NH3 (gas)
Graphics copy-write Pro. Milo Koretsky, Chemical Engineering Department at OSU and Silicon Run Educational Video Factors that Effect Reaction and Film Growth: Deposition Time aka Reaction Time
Reaction/Deposition Time = the amount of time the reactor runs How do you think deposition time effects the film thickness??? Virtual CVD Overview Choosing the Virtual CVD reactor parameters
Pressure is Fixed
Each run costs $ Measurement – Thickness & Uniformity
Film thickness is determined by the amount of material that reacts and is grown on the wafer Uniformity describes the evenness of film thickness on the wafer 45% Uniformity 100% Uniformity
1000 1000
800 800
600 600
400 400
200 200
Film Thickness [A] Thickness Film [A] Thickness Film 0 0 -150 -50 50 150 -150 -50 50 150 x position x position Measurement – Thickness & Uniformity
Film thickness is determined by the amount of material that reacts and is grown on the wafer Uniformity describes the evenness of film thickness on the wafer
NH4Cl (gas) NH3 (gas) H2 (gas) SiCl2H2 (gas) 200 50% Overall Efficiency 150
100 Wafer # Wafer
50
0 0 2000 4000 6000 8000 10000 SiCl2H2 (gas) Thickness [A]
NH3 (gas) 79% Overall Efficiency Measurement via Ellipsometer
Light Source The ellipsometer is used to measure the Detector thickness and refractive index of Light Control transparent films. It is made of a light source and polarizer Analyzing Polarizing on one side and a analyzer and detector Polarizer Sheet on the other side. Substrate
Analyzer & Light Source, Detector Control & Polarizing Light from the source is polarized Sheet and reflected off the film. The analyzer is rotated till no light passes through it. The angle of rotation depends on the thickness of the film. Virtual CVD Overview Choosing the locations on the wafer to measure
Each measurement costs $ Virtual Chemical Vapor Deposition (VCVD) Program Semiconductor Manufacturing Fab VCVD Program
Photo Courtesy of http://webmedia.national.com/gallery/06/06_rgb.jpg Your Objectives:
Determine how temperature, flow rates, and
reaction time impact deposition of Si3N4 Minimize cost of testing process used to determine the impact of these parameters Extra Credit: Find an optimized “recipe” that produces high uniformity (within wafer and between wafers) and meets a target thickness of 1000 Angstroms Economy of Transistors
~$300 /chip X ~200 chips/wafer
http://www.nitride.co.jp/english X 200 wafers/furnace /products/wafer.html load = $12 Million per furnace load http://www.dvhardware.net/article16696.html Let’s Get Started
Open VCVD Program...